WO2023151279A1 - 芯片封装组件及其制作方法 - Google Patents

芯片封装组件及其制作方法 Download PDF

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Publication number
WO2023151279A1
WO2023151279A1 PCT/CN2022/120713 CN2022120713W WO2023151279A1 WO 2023151279 A1 WO2023151279 A1 WO 2023151279A1 CN 2022120713 W CN2022120713 W CN 2022120713W WO 2023151279 A1 WO2023151279 A1 WO 2023151279A1
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WO
WIPO (PCT)
Prior art keywords
wiring layer
fan
layer
bridging
insulating layer
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PCT/CN2022/120713
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English (en)
French (fr)
Inventor
朱凯
缪桦
黄立湘
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深南电路股份有限公司
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Publication of WO2023151279A1 publication Critical patent/WO2023151279A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present application relates to the technical field of packaging, in particular to a chip packaging component and a manufacturing method thereof.
  • chip performance improvement there are two main directions for chip performance improvement: one is large chips, that is, increasing the chip size, so as to realize more functions on the chip. This is also called System on Chip (SOC), but the larger the chip size , the higher the manufacturing cost, the more difficult it is to guarantee the yield rate; the second is small chip integration, also called system-in-package (System in Package, SIP), which is to integrate multiple smaller-sized chips together in the form of packaging, so that Improve the overall performance of the chip.
  • SOC System on Chip
  • SIP System in Package
  • the silicon interposer Si interposer
  • the embedded multi-die interconnect bridge Embedded Multi-die Interconnect Bridge, EMIB.
  • the silicon bridge used in the embedded multi-chip interconnection bridge is smaller in size, and the silicon bridge can only be added at the position where chip interconnection communication is required, so the design is more flexible; more importantly, the embedded The multi-chip interconnection bridge integrates the connection between the silicon bridge and the chip into the manufacture of the packaging substrate, which shortens the supply chain and is more conducive to controlling the overall cost.
  • the present application provides a chip package assembly and a manufacturing method thereof, which can solve the above-mentioned problem of poor chip bridge connection caused by inaccurate placement and alignment of silicon bridges.
  • the present application provides a chip package assembly
  • the chip package assembly includes a bridge wiring layer, a fan-out wiring layer and a plurality of chips
  • the bridge wiring layer is arranged on one side of the fan-out wiring layer
  • the chip is connected to the
  • the fan-out wiring layer is provided with one side of the bridging wiring layer, and at least two chips each have some pins connected to the bridging wiring layer so as to communicate through the bridging wiring layer.
  • the bridging wiring layer includes bridging lines and a first insulating layer, the first insulating layer wraps part of the bridging lines, and the reserved areas of the bridging lines are connected to pins of different chips.
  • the fan-out wiring layer includes a fan-out line and a second insulating layer, the fan-out line is arranged in the second insulating layer, the second insulating layer is connected to the bridge wiring layer, and is coplanar with the side of the bridge wiring layer close to the chip , the other pins of the chip are connected to the fan-out lines.
  • a solder resist layer is provided on a side of the fan-out wiring layer far away from the bridging wiring layer, and the solder resist layer covers the fan-out lines and the second insulating layer, and some connection points of the fan-out lines are reserved.
  • a side of the fan-out line away from the bridging wiring layer is connected to a plurality of solder balls, and the solder balls are connected to an external circuit board.
  • the bridging line is connected with the fan-out line.
  • the present application provides a circuit board assembly, the circuit board assembly includes a circuit board and a chip packaging assembly, the chip packaging assembly is connected to the circuit board, and the chip packaging assembly is the above-mentioned chip packaging assembly.
  • the present application provides a method for manufacturing a chip package assembly.
  • the manufacturing method includes: obtaining a carrier board, and laying a temporary bonding layer on the carrier board; laying a first insulating layer on the temporary bonding layer, and then Remove the preset area of the first insulating layer; lay the first conductive layer on the first insulating layer, and then remove the preset area of the first conductive layer to obtain the bridge circuit; lay the first insulation on the bridge circuit again layer, and then remove the preset area of the first insulating layer to obtain a bridging wiring layer; lay a second insulating layer on the bridging wiring layer, and then open a window on the second insulating layer; lay a second insulating layer on the second insulating layer Two conductive layers, and finally make the fan-out circuit; judge whether it is necessary to add a layer of fan-out circuit, if so, then regard the fan-out circuit as the above-mentioned bridge wiring layer, repeat the above
  • the second insulating layer is coplanar with the side of the bridge wiring layer close to the chip.
  • the surface area of the bridge wiring layer facing the chip is much smaller than the surface area of the chip facing the bridge wiring layer.
  • the present application provides a chip package assembly, the chip package assembly includes a bridge wiring layer, a fan-out wiring layer and a plurality of chips, and the bridge wiring layer is arranged on the fan-out One side of the wiring layer, the chip is connected to the side of the fan-out wiring layer provided with the bridging wiring layer, at least two chips each have some pins connected to the bridging wiring layer to communicate through the bridging wiring layer, and the rest of the chip leads The pin connects to the fan-out routing layer.
  • the technical solution can realize chip interconnection by setting a bridge wiring layer on the fan-out wiring layer; this manufacturing method first determines and manufactures the bridge wiring layer structure according to the position of the chip pins, and then fabricates the fan-out wiring layer based on the position of the bridge wiring layer. Out of the line, so as to realize the precise positioning connection between the bridge wiring layer and the chip.
  • FIG. 1 is a schematic structural view of a first embodiment of a chip package assembly provided by the present application
  • Fig. 2 is a schematic flow chart of the first embodiment of the manufacturing method of the chip package assembly provided by the present application;
  • Fig. 3 is the schematic flow chart of etching bridging circuit that the present application provides
  • FIG. 4 is a schematic diagram of a cross-sectional structure of the chip package assembly after step S104 in FIG. 2 is completed;
  • FIG. 5 is a schematic diagram of the cross-sectional structure of the chip package assembly after step S106 in FIG. 2 is completed;
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a chip package assembly after adding a layer of fan-out lines in step S107 in FIG. 2;
  • Fig. 7 is a schematic structural view of the first embodiment of the circuit board assembly provided by the present application.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a chip package assembly provided by the present application.
  • the chip package assembly includes a plurality of chips 11 , bridging wiring layers 12 , fan-out wiring layers 13 and solder balls 14 .
  • a plurality of pins 111 are provided on the chip 11 .
  • the bridge wiring layer 12 includes a bridge line 121 and a first insulating layer 122, the bridge line 121 is disposed in the first insulating layer 122, and part of the reserved area is exposed on the surface of the first insulating layer 122 away from the fan-out wiring layer 13 , the reserved area is connected to some pins 111.
  • the fan-out wiring layer 13 includes a fan-out line 131 and a second insulating layer 132, the fan-out line 131 is disposed in the second insulating layer 132, the second insulating layer 132 wraps the bridging wiring layer 12, and exposes part of the bridging line 121 and the rest Part pin 111 is connected.
  • a side of the fan-out wiring layer 13 is partially provided with a plurality of bridging wiring layers 12
  • a side of the fan-out wiring layer 13 away from the bridging wiring layer 12 is provided with a plurality of solder balls 14 .
  • some pins 111 of the chips 11 are connected to the bridge lines 121 in the bridge wiring layer 12 to realize the interconnection of multiple chips 11 .
  • the other pins 111 of the chip 11 are connected to the fan-out circuit 131 , the solder balls 14 are connected to the fan-out circuit 131 , and the solder balls 14 are also connected to an external circuit board, so that the chip 11 is connected to the external circuit board.
  • the solder balls 14 can also be replaced with other conductive connectors, such as pins, metal pillars and the like.
  • the way of connecting the bridging line 121 to the pin 111 includes welding, pasting with conductive adhesive, and the like.
  • the shape of the bridging wiring layer 12 can also be adjusted so as to accurately connect the chip 11; a plurality of pins can also be set in the first insulating layer 122, so that the bridging line 121 and the fan-out line 131 are electrically connected. connect.
  • FIG. 2 is a schematic flowchart of the first embodiment of the manufacturing method of the chip package assembly provided by the present application.
  • the manufacturing method of the chip package assembly includes the following steps:
  • S101 Obtain a carrier board, and lay a temporary bonding layer on the carrier board.
  • the carrier is preferably a glass carrier, a stainless steel carrier and a silicon wafer carrier, and the shape of the carrier can be square, rectangular, or circular.
  • the temporary bonding layer can be thermally sensitive, photosensitive, or mechanically peelable. By making a temporary bonding layer on the carrier board, it is to facilitate the separation of the carrier board and the chip package assembly before ball planting in the later stage.
  • the first insulating layer is preferably a silicon dioxide insulating layer, a silicon nitride insulating layer or a photosensitive polyimide insulating layer, and a silicon dioxide insulating layer is deposited on the entire surface of the temporary bonding layer by chemical vapor deposition. Either a silicon nitride insulating layer, or laying a photosensitive polyimide insulating layer on the temporary bonding layer by coating, and then selectively etching or developing.
  • the first insulating layer is preferably an inorganic insulating layer, because the processing precision of the inorganic insulating layer is higher, which can improve the precision of chip connection.
  • the first insulating layer is used for finer bridging line requirements, so the thickness of the silicon dioxide insulating layer or silicon nitride insulating layer is 100nm-5 ⁇ m; the thickness of the photosensitive polyimide insulating layer is 2 ⁇ 15 ⁇ m.
  • the excess part is etched away by plasma; if the first insulating layer is If the photosensitive polyimide insulating layer is used, then the excess photosensitive polyimide insulating layer can be peeled off by direct exposure, development and curing.
  • the bridging circuit After sputtering a layer of the first conductive layer on the first insulating layer, the bridging circuit is made, and the material of the bridging circuit is preferably copper, nickel, cobalt or titanium-copper alloy.
  • FIG. 3 is a schematic flow chart of making a bridge circuit provided by the present application.
  • the steps of making a bridging line include:
  • a photoresist layer is fabricated on the surface of the first conductive layer, and a pattern of bridging lines is fabricated.
  • the photoresist layer includes photoresist material and dry film material.
  • an exposure machine is required for exposure, which can make the bridge line pattern finer; when using a dry film material, it is generally exposed by an automatic exposure machine or laser direct imaging technology, and the size of the bridge line pattern relatively bigger.
  • the fineness of the bridge circuit is high, and the photoresist material is preferred.
  • the line width and line spacing are generally 1-15 ⁇ m.
  • the thickness of the sputtered first conductive layer is limited, generally less than or equal to 500nm, in order to reduce the interconnection resistance of the bridge circuit, pattern plating can be used to thicken the first conductive layer to the required line thickness of the bridge circuit.
  • S133 Stripping off the photoresist or the dry film, and removing the redundant first conductive layer.
  • etching is preferred to remove the redundant first conductive layer.
  • FIG. 4 is a schematic cross-sectional structure diagram of the chip package assembly after step S104 in FIG.
  • the bridge circuit 24 is sealed with the first insulating layer 23, the first insulating layer 23 is preferably a silicon dioxide insulating layer, a silicon nitride insulating layer or a photosensitive polyimide insulating layer, and is chemically A silicon dioxide insulating layer or a silicon nitride insulating layer is deposited on the entire surface of the bridge circuit 24 by vapor deposition, or a photosensitive polyimide insulating layer is laid on the bridge circuit 24 by coating.
  • the bridge circuit 24 is disposed in the first insulating layer 23, and different positions of the bridge circuit 24 are connected to different chip pins.
  • the preset part of the bridging line 24 can be exposed to connect to the chip pins, and the remaining part can be sealed, so as to protect the bridging line 24 .
  • the purpose of removing the preset part of the first insulating layer 23 is to leave space for the subsequent fan-out circuit.
  • the excess part is etched away by using plasma through a photoresist pattern mask. ; If the first insulating layer 23 is a photosensitive polyimide insulating layer, then the excess photosensitive polyimide insulating layer can be peeled off by direct exposure, development and curing.
  • a bridge wiring layer is obtained, wherein the surface area of the bridge wiring layer facing the chip is much smaller than the surface area of the chip facing the bridge wiring layer.
  • the bridging wiring layer is used to connect chip pins, and since the first insulating layer 23 seals the bridging line 24, the bridging line 24 is not connected to other lines.
  • the bridging line 24 may also reserve a pin to connect with the fan-out line.
  • the second insulating layer is preferably an organic insulating material, including epoxy resin, phenolic resin, polyimide, BT, ABF, ceramic base and the like. According to the design requirements of the subsequent fan-out lines, the second insulating layer is opened so that the fan-out lines can be interconnected with the chip pins through the opening of the second insulating layer.
  • the second insulating layer and the temporary bonding layer completely wrap the bridging wiring layer, and the second insulating layer is coplanar with a side of the bridging wiring layer close to the carrier board.
  • the ways of opening windows on the second insulating layer include: exposure, development, curing, laser drilling and plasma etching.
  • the window opening of the target position can be obtained by direct exposure, development, and curing; while the epoxy resin, phenolic resin and other insulating layers are used, laser drilling can be used To obtain the window, it is also possible to make a photoresist pattern and use plasma etching to obtain the window at the target position.
  • S106 Lay a second conductive layer on the second insulating layer, and then fabricate a fan-out circuit.
  • FIG. 5 is a schematic cross-sectional structure diagram of the chip package assembly after step S106 in FIG. Two insulating layers 25 and fan-out lines 26 .
  • the fan-out circuit 26 is fabricated on the second insulating layer 25 , and the fan-out circuit 26 covers a part of the surface of the second insulating layer 25 and the hole wall and bottom of the opening position of the second insulating layer 25 .
  • the second conductive layer is preferably obtained by sputtering, and the material of the second conductive layer includes titanium copper alloy or copper;
  • the second conductive layer can be obtained by sputtering titanium-copper alloy or copper, or by electroless copper plating.
  • the step of making the fan-out line on the second insulating layer includes: making a photoresist layer on the second conductive layer on the surface of the second insulating layer 25, performing patterned copper plating according to the set photoresist layer, thereby obtaining the fan-out line 26, Finally, the photoresist layer is stripped and the redundant second conductive layer is etched away.
  • the photoresist layer is preferably made of photoresist material or dry film material.
  • photoresist material an exposure machine is required for exposure, and the pattern is finer; when using dry film material, generally an automatic exposure machine or a laser is used to directly Imaging technology and other methods for exposure.
  • dry film material generally an automatic exposure machine or a laser is used to directly Imaging technology and other methods for exposure.
  • the photoresist material is preferred.
  • the bridging line 24 since the bridging line 24 does not need to be connected to the fan-out line 26 , therefore, it is not necessary to open a window to make the pins of the bridging line 24 leak out when the first insulating layer 23 is fabricated.
  • the first insulating layer 23 needs to open a window to make the pins of the bridging line 24 leak out when the first insulating layer 23 is manufactured, and the second insulating layer 25 needs to be in the corresponding position Opening the window exposes the pins of the bridging line 24 , thereby realizing the connection between the bridging line 24 and the fan-out line 26 .
  • FIG. 6 is a schematic cross-sectional structure diagram of a chip package assembly after adding a layer of fan-out lines in step S107 in FIG. 2.
  • the chip package assembly includes a carrier plate 21, a temporary bonding layer 22, a first insulating layer 23, The bridging line 24 , the second insulating layer 25 , the fan-out line 26 and the solder resist layer 27 .
  • the fan-out lines 26 that have been laid are regarded as a bridging wiring layer, and the second insulating layer 25 is laid on the fan-out lines 26 that have been laid, and then the second insulating layer 25 is opened. window, make a new fan-out line 26 on the second insulating layer 25, and then judge again whether it is necessary to add a layer of fan-out line 26, until the fan-out line 26 does not need to be added, lay a solder resist layer on the fan-out line 26 27.
  • solder resist layer it is necessary to open a window on the solder resist layer to expose the connection point of the fan-out circuit for subsequent installation of solder balls and connection with an external circuit board.
  • the bridge wiring layer is provided in the fan-out wiring layer to realize the interconnection of adjacent chips, and based on the manufacturing method of the chip package assembly proposed in this application, the bridge wiring layer is firstly fabricated accurately according to the position of the chip, Then, based on the bridge wiring layer, fan-out lines interconnected with other pins of the chip are made, so that the position of the wire layer connected to the chip pins in the bridge wiring layer can be precisely controlled, and the precision of chip connection is improved.
  • the present application provides a circuit board assembly, as shown in FIG. 7 , which is a schematic structural diagram of a first embodiment of the circuit board assembly provided by the present application.
  • the circuit board assembly includes a chip package assembly 31 , a circuit board 32 and solder balls 33 .
  • the chip package assembly 31 is the above-mentioned chip package assembly, and the chip package assembly 31 and the circuit board 32 are connected by solder balls 33 .
  • solder balls 33 can also be replaced with other conductive connectors, such as pins, metal pillars and the like.

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Abstract

本申请公开了一种芯片封装组件及其制作方法，芯片封装组件包括桥连布线层、扇出布线层以及多个芯片，桥连布线层设置于扇出布线层的一侧，芯片连接于扇出布线层设置有桥连布线层的一侧，至少两个芯片各有部分引脚连接桥连布线层，以通过桥连布线层连通，芯片其余引脚连接扇出布线层。本技术方案通过在扇出布线层上局部设置桥连布线层，能够实现芯片互连；本制作方法根据芯片引脚位置先确定并制作桥连布线层结构，随后基于桥连布线层的位置制作扇出布线层，从而实现桥连布线层与芯片精准定位连接。

Description

芯片封装组件及其制作方法
本申请以2022年2月9日提交的申请号为202210122766.1，名称为“芯片封装组件及其制作方法”的中国发明申请为基础，并要求其优先权。
技术领域
本申请涉及封装技术领域，特别是涉及一种芯片封装组件及其制作方法。
背景技术
目前，芯片性能提升主要是两个方向：一是大芯片，即增加芯片尺寸，从而在芯片上实现更多的功能，这个也叫片上集成系统(System on Chip，SOC)，但芯片尺寸越大，制造成本越高，良率也越难以保证；二是小芯片集成，也叫系统级封装(System in Package，SIP)，就是把多个尺寸较小的芯片通过封装的形式集成在一起，从而提高芯片的整体性能。
现有技术中的芯片堆叠封装工艺中，最常用的是硅转接板(Si interposer)方法和嵌入式多芯片互连桥接(Embedded Multi-die Interconnect Bridge，EMIB)。与硅转接板相比，嵌入式多芯片互连桥接中使用的硅桥尺寸更小，可以只在需要芯片互连通信的位置增加硅桥，因此设计更灵活；更重要的是，嵌入式多芯片互连桥接将硅桥与芯片的连接整合到了封装基板的制造中，缩短了供应链，更有利于控制整体成本。
然而，嵌入式多芯片互连桥接也存在着明显的技术挑战，硅桥尺寸较小，且后续对硅桥进行贴装时精度要求高，对位难度大，位置偏移风险高，容易导致芯片桥接不良。
申请内容
本申请提供一种芯片封装组件及其制作方法，能够解决上述硅桥贴装对位不准而导致的芯片桥接不良的问题。
为解决上述技术问题，本申请提供一种芯片封装组件，芯片封装组件包括桥连布线层、扇出布线层以及多个芯片，桥连布线层设置于扇出布线层的一侧，芯片连接于扇出布线层设置有桥连布线层的一侧，至少两个芯片各有部分引脚连接桥连布线层，以通过桥连布线层连通。
其中，桥连布线层包括桥连线路和第一绝缘层，第一绝缘层包裹部分桥连线路，桥连线路预留区域与不同的芯片的引脚连接。
其中，扇出布线层包括扇出线路和第二绝缘层，扇出线路设置于第二绝缘层中，第二绝缘层与桥连布线层连接，与桥连布线层靠近芯片的一侧共面，芯片的另外部分引脚连接扇出线路。
其中，扇出布线层远离桥连布线层的一侧设置阻焊层，阻焊层覆盖扇出线路和第二绝缘层，预留部分扇出线路的连接点。
其中，扇出线路远离桥连布线层的一侧连接多个锡球，锡球与外部电路板连接。
其中，桥连线路与扇出线路连接。
为解决上述技术问题，本申请提供一种线路板组件，线路板组件包括电路板以及芯片封装组件，芯片封装组件与电路板连接，且芯片封装组件为上文所述的芯片封装组件。
为解决上述技术问题，本申请提供一种芯片封装组件的制作方法，制作方法包括：获取载板，并在载板上铺设临时键合层；在临时键合层上铺设第一绝缘层，后把第一绝缘层的预设区域去除；在第一绝缘层上铺设第一导电层，后把第一导电层的预设区域去除，得到桥连线路；再次在桥连线路上铺设第一绝缘层，后将第一绝缘层的预设区域去除,获取桥连布线层；在桥连布线层上铺设第二绝缘层，后对第二绝缘层进行开窗；在第二绝缘层上铺设第二导电层，后制作扇出线路；判断是否需要增加一层扇出线路，若是，则将扇出线路视作上述桥连布线层，重复上述操作至完成扇出线路；若否，则在扇出线路上铺设阻焊层，并对阻焊层的预设部分进行开窗。
其中，第二绝缘层与桥连布线层靠近芯片的一侧共面。
其中，桥连布线层朝向芯片一侧的表面积远小于芯片朝向桥连布线层一侧的表面积。
本申请的有益效果是：区别于现有技术的情况，本申请提供了一种芯片封装组件，芯片封装组件包括桥连布线层、扇出布线层以及多个芯片，桥连布线层设置于扇出布线层的一侧，芯片连接于扇出布线层设置有桥连布线层的一侧，至少两个芯片各有部分引脚连接桥连布线层，以通过桥连布线层连通，芯片其余引脚连接扇出布线层。本技术方案通过在扇出布线层上设置桥连布线层，能够实现芯片互连；本制作方法根据芯片引脚位置先确定并制作桥连布线层结构，随后基于桥连布线层的位置制作扇出线路，从而实现桥连布线层与芯片精准定位连接。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，其中：
图1是本申请提供的芯片封装组件的第一实施例的结构示意图；
图2是本申请提供的芯片封装组件的制作方法的第一实施例的流程示意图；
图3是本申请提供的蚀刻桥连线路的流程示意图；
图4为图2中步骤S104完成后的芯片封装组件截面结构示意图；
图5为图2中步骤S106完成后的芯片封装组件截面结构示意图；
图6为图2中步骤S107中添加一层扇出线路后的芯片封装组件截面结构示意图；
图7是本申请提供的线路板组件的第一实施例的结构示意图。
具体实施方式
为使本申请解决的技术问题、采用的技术方案和达到的技术效果更 加清楚，下面将结合附图对本申请实施例的技术方案作进一步的详细描述。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
参阅图1，图1是本申请提供的芯片封装组件的第一实施例的结构示意图。本实施例中，芯片封装组件包括多个芯片11、桥连布线层12、扇出布线层13以及锡球14。
芯片11上设置有多个引脚111。
桥连布线层12包括桥连线路121和第一绝缘层122，桥连线路121设置于第一绝缘层122中，且部分预留区域暴露于第一绝缘层122远离扇出布线层13的表面，预留区域与部分引脚111连接。
扇出布线层13包括扇出线路131以及第二绝缘层132，扇出线路131设置于第二绝缘层132中，第二绝缘层132包裹桥连布线层12，暴露部分桥连线路121与其余部分引脚111连接。扇出布线层13的一侧局部设置多个桥连布线层12，扇出布线层13远离桥连布线层12的一侧设置多个锡球14。
本实施例中，芯片11的部分引脚111通过连接桥连布线层12中的桥连线路121实现多个芯片11互连。芯片11的其他引脚111连接扇出线路131，锡球14与扇出线路131连接，锡球14还与外部电路板连接，从而实现芯片11与外部电路板连接。锡球14还可以换为其他的导电连接件，例如引脚、金属柱等。
其中，桥连线路121与引脚111连接的方式包括焊接、导电胶粘贴等。
在其他实施例中，桥连布线层12的形状还可以调整，以便精准地连接芯片11；第一绝缘层122中还可以设置多个引脚，以使桥连线路121与扇出线路131导通连接。
参阅图2，图2是本申请提供的芯片封装组件的制作方法的第一实施例的流程示意图。
本实施例中，芯片封装组件的制作方法包括以下步骤：
S101：获取载板，并在载板上铺设临时键合层。
其中，载板优选玻璃载板，不锈钢载板和硅晶圆载板，另外载板的形状可以是正方形、长方形，也可以是圆形。
其中，临时键合层可以热敏型、光敏性、也可以是机械剥离型。通过在载板上制作临时键合层，是为了便于后期植球前分离载板与芯片封装组件。
S102：在临时键合层上铺设第一绝缘层，后把第一绝缘层的预设区域去除。
其中，第一绝缘层优选二氧化硅绝缘层、氮化硅绝缘层或者感光聚酰亚胺绝缘层，并且通过化学气相沉积的方式在临时键合层表面整板沉积一层二氧化硅绝缘层或者氮化硅绝缘层，或者用涂布的方式在临时键合层上铺设感光聚酰亚胺绝缘层，然后选择性蚀刻或显影。特别地，第一绝缘层优选无机绝缘层，因为无机绝缘层加工精度更高，可以提高芯片连接的精度。
本实施例中，通过在临时键合层上铺设第一绝缘层，能够有效保护后续制作的桥连线路，而把第一绝缘层的预设区域去除是为了将芯片引脚连接点的位置留出。在实际操作过程中，第一绝缘层用于较为精细的桥连线路需求，因此二氧化硅绝缘层或者氮化硅绝缘层的厚度为100nm～5μm；感光聚酰亚胺绝缘层的厚度为2～15μm。
蚀刻第一绝缘层的过程中，若第一绝缘层是二氧化硅绝缘层或者氮化硅绝缘层，那么通过光阻图形掩膜，利用等离子体将多余部分蚀刻掉；若第一绝缘层是感光聚酰亚胺绝缘层，那么直接进行曝光显影固化，就可以剥离多余的感光聚酰亚胺绝缘层。
S103：在第一绝缘层上铺设第一导电层，后把第一导电层的预设区域去除，得到桥连线路。
在第一绝缘层上溅射一层第一导电层后制作桥连线路，桥连线路的 材质优选为铜、镍、钴或者钛铜合金。
参阅图3，图3是本申请提供的制作桥连线路的流程示意图。
本实施例中，制作桥连线路的步骤包括：
S131：采用光刻胶或者干膜制作电路图像。
在第一导电层表面制作光阻层，并制作出桥连线路的图形。其中，光阻层包括光刻胶材料和干膜材料。当使用光刻胶材料时，需要曝光机进行曝光，能够使得桥连线路图形更精细；当使用干膜材料时，一般用自动曝光机或激光直接成像技术等方式进行曝光，桥连线路图形尺寸相对较大。一般来说，桥连线路精细程度高，优选光刻胶材料，线宽线距一般为1～15μm，当精度要求较高时，配合使用硅晶圆载板，精度可以达到亚微米级。
S132：进行图形电镀。
特别地，由于溅射第一导电层厚度有限，一般小于等于500nm，因此，为降低桥连线路的互连电阻，可以使用图形电镀加厚第一导电层至桥连线路所需线路厚度。
S133：剥离光刻胶或干膜，并去掉多余的第一导电层。
剥离光刻胶或干膜制作电路图像，去掉多余第一导电层，从而获取桥连线路。
其中，优选蚀刻的方式去掉多余第一导电层。
S104：再次在桥连线路上铺设第一绝缘层，后将第一绝缘层的预设区域去除，获取桥连布线层。
如图4所示，图4为图2中步骤S104完成后的芯片封装组件截面结构示意图，芯片封装组件包括载板21、临时键合层22、第一绝缘层23和桥连线路24。
在步骤S103的基础上，用第一绝缘层23将桥连线路24进行密封，第一绝缘层23优选二氧化硅绝缘层、氮化硅绝缘层或者感光聚酰亚胺绝缘层，并且通过化学气相沉积的方式在桥连线路24表面整板沉积一层二氧化硅绝缘层或者氮化硅绝缘层，或者用涂布的方式在桥连线路24上铺设感光聚酰亚胺绝缘层。桥连线路24设置于第一绝缘层23中，且 桥连线路24不同位置与不同的芯片引脚连接。
本实施例中，通过在桥连线路24上铺设第一绝缘层23，能够实现桥连线路24露出预设部分连接芯片引脚，其余部分密封，从而保护桥连线路24。而把第一绝缘层23的预设部分去掉，是为了给后续制作的扇出线路留出空间。
另外，去除第一绝缘层23预设部分的过程中，若第一绝缘层23是二氧化硅绝缘层或者氮化硅绝缘层，那么通过光阻图形掩膜，利用等离子体将多余部分蚀刻掉；若第一绝缘层23是感光聚酰亚胺绝缘层，那么直接进行曝光显影固化，就可以剥离多余的感光聚酰亚胺绝缘层。
通过上述步骤，获取了桥连布线层，其中，桥连布线层朝向芯片一侧的表面积远小于芯片朝向桥连布线层一侧的表面积。在本实施例中，桥连布线层用于连接芯片引脚，并且由于第一绝缘层23密封桥连线路24，因此桥连线路24不与其他线路连接。在其他实施例中，桥连线路24还可以留出引脚与扇出线路连接。
S105：在桥连布线层上铺设第二绝缘层，后对第二绝缘层进行开窗。
第二绝缘层优选有机绝缘材料，包括环氧树脂类、酚醛树脂类、聚酰亚胺类、BT类、ABF类、陶瓷基类等。根据后续制作的扇出线路的设计要求对第二绝缘层进行开窗，使得扇出线路能够通过第二绝缘层开窗与芯片引脚互连。
其中，第二绝缘层与临时键合层将桥连布线层完全包裹，并且第二绝缘层与桥连布线层靠近载板的一侧共面。对第二绝缘层进行开窗的方式包括：曝光、显影、固化，激光钻孔以及等离子蚀刻。当采用感光聚酰亚胺绝缘层时，那么直接进行曝光、显影、固化就能够获得目标位置的开窗；而采用环氧树脂类、酚醛树脂类等绝缘层时，可以采用激光钻孔的方式获得开窗，也可以制作光阻图形并用等离子蚀刻的方式获得目标位置的开窗。
S106：在第二绝缘层上铺设第二导电层，后制作扇出线路。
如图5所示，图5为图2中步骤S106完成后的芯片封装组件截面结构示意图，芯片封装组件包括载板21、临时键合层22、第一绝缘层 23、桥连线路24、第二绝缘层25和扇出线路26。
根据设计要求在第二绝缘层25上制作扇出线路26，扇出线路26覆盖了第二绝缘层25的局部表面以及第二绝缘层25的开窗位置的孔壁和底部。当第二绝缘层25为感光聚酰亚胺绝缘层时，第二导电层优选地使用溅射的方式获得，第二导电层的材料包括钛铜合金或铜；当第二绝缘层25采用环氧树脂类、酚醛树脂类等绝缘层时，第二导电层可以通过溅射钛铜合金或铜获得，还可以通过化学镀铜获取。
在第二绝缘层上制作扇出线路的步骤包括：在第二绝缘层25表面的第二导电层上制作光阻层，根据设置的光阻层进行图形电镀铜，从而获取扇出线路26，后剥离光阻层并蚀刻掉多余的第二导电层。
其中，光阻层优选地使用光刻胶材料或者干膜材料，当使用光刻胶材料时，需要曝光机进行曝光，图形较精细；当使用干膜材料时，一般用自动曝光机或激光直接成像技术等方式进行曝光。当扇出线路26的图形尺寸较小，精度要求较高时，优选光刻胶材料。
本实施例中，由于桥连线路24不需要与扇出线路26连接，因此，第一绝缘层23制作时不需要开窗使桥连线路24的引脚漏出。在其他实施例中，当桥连线路24需要与扇出线路26连接时，第一绝缘层23制作时需要开窗使桥连线路24的引脚漏出，且第二绝缘层25需要在对应位置开窗使桥连线路24的引脚露出，进而实现桥连线路24与扇出线路26的连接。
S107：判断是否需要增加一层扇出线路，若是，则将扇出线路视作上述桥连布线层，重复上述S105-S106步骤,至完成扇出线路；若否，则执行S108步骤。
如图6所示，图6为图2中步骤S107中添加一层扇出线路后的芯片封装组件截面结构示意图，芯片封装组件包括载板21、临时键合层22、第一绝缘层23、桥连线路24、第二绝缘层25、扇出线路26和阻焊层27。
当需要设置多层扇出线路26时，将已经铺设扇出线路26视为桥连布线层，在已经铺设的扇出线路26上铺设第二绝缘层25，后对第二绝 缘层25进行开窗，在第二绝缘层25上制作新的扇出线路26，然后再次判断是否需要增加一层扇出线路26，直至不需要增加扇出线路26时，在扇出线路26上铺设阻焊层27。
S108：在扇出线路上铺设阻焊层，并对阻焊层的预设部分进行开窗。
在实施操作过程中，需要对阻焊层开窗，将扇出线路的连接点露出，用于后续安装锡球，并与外部电路板连接。
通过上述方案，在扇出布线层中设置桥连布线层，能够实现相邻芯片互连，并且基于本申请中提出的芯片封装组件的制作方法，先根据芯片位置精确地制作桥连布线层，然后基于桥连布线层制作与芯片其他引脚互连的扇出线路，从而能够精准地控制桥连布线层中连接芯片引脚的导线层的位置，提高芯片连接的精度。
为解决上述技术问题，本申请提供一种线路板组件，如图7所示，图7是本申请提供的线路板组件的第一实施例的结构示意图。本实施例中，线路板组件包括芯片封装组件31、电路板32和锡球33。
其中，芯片封装组件31为上文所述的芯片封装组件，芯片封装组件31与电路板32通过锡球33连接。
在其他实施例中，锡球33还可以换为其他的导电连接件，例如引脚、金属柱等。
通过上述结构，实现了芯片封装组件31与外部电路板32的连接。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (15)

  1. 一种芯片封装组件，其中，所述芯片封装组件包括桥连布线层、扇出布线层以及多个芯片，所述桥连布线层设置于所述扇出布线层的一侧，所述芯片连接于所述扇出布线层设置有所述桥连布线层的一侧，至少两个所述芯片各有部分引脚连接所述桥连布线层，以通过所述桥连布线层连通。
  2. 根据权利要求1所述的芯片封装组件，其中，所述桥连布线层包括桥连线路和第一绝缘层，所述第一绝缘层包裹部分所述桥连线路，所述桥连线路预留区域与不同的所述芯片的所述引脚连接。
  3. 根据权利要求1所述的芯片封装组件，其中，所述扇出布线层包括扇出线路和第二绝缘层，所述扇出线路设置于所述第二绝缘层中，所述第二绝缘层与所述桥连布线层连接，与所述桥连布线层靠近所述芯片的一侧共面，所述芯片的另外部分引脚连接所述扇出线路。
  4. 根据权利要求3所述的芯片封装组件，其中，所述扇出布线层远离所述桥连布线层的一侧设置阻焊层，所述阻焊层覆盖所述扇出线路和所述第二绝缘层，预留部分所述扇出线路的连接点。
  5. 根据权利要求3所述的芯片封装组件，其中，所述扇出线路远离所述桥连布线层的一侧连接多个锡球，所述锡球与外部电路板连接。
  6. 根据权利要求3所述的芯片封装组件，其中，所述桥连线路与所述扇出线路连接。
  7. 一种线路板组件，其中，所述线路板组件包括电路板以及芯片封装组件，所述芯片封装组件与所述电路板连接，所述芯片封装组件包括桥连布线层、扇出布线层以及多个芯片，所述桥连布线层设置于所述扇出布线层的一侧，所述芯片连接于所述扇出布线层设置有所述桥连布线层的一侧，至少两个所述芯片各有部分引脚连接所述桥连布线层，以通过所述桥连布线层连通。
  8. 如权利要求7所述的线路板组件，其中，所述桥连布线层包括桥连线路和第一绝缘层，所述第一绝缘层包裹部分所述桥连线路，所述 桥连线路预留区域与不同的所述芯片的所述引脚连接。
  9. 如权利要求7所述的线路板组件，其中，所述扇出布线层包括扇出线路和第二绝缘层，所述扇出线路设置于所述第二绝缘层中，所述第二绝缘层与所述桥连布线层连接，与所述桥连布线层靠近所述芯片的一侧共面，所述芯片的另外部分引脚连接所述扇出线路。
  10. 如权利要求9所述的线路板组件，其中，所述扇出布线层远离所述桥连布线层的一侧设置阻焊层，所述阻焊层覆盖所述扇出线路和所述第二绝缘层，预留部分所述扇出线路的连接点。
  11. 如权利要求9所述的线路板组件，其中，所述扇出线路远离所述桥连布线层的一侧连接多个锡球，所述锡球与外部电路板连接。
  12. 如权利要求9所述的线路板组件，其中，所述桥连线路与所述扇出线路连接。
  13. 一种芯片封装组件的制作方法，其中，所述制作方法包括：
    获取载板，并在所述载板上铺设临时键合层；
    在所述临时键合层上铺设第一绝缘层，后把所述第一绝缘层的预设区域去除；
    在所述第一绝缘层上铺设第一导电层，后把所述第一导电层的预设区域去除，得到桥连线路；
    再次在所述桥连线路上铺设所述第一绝缘层，后将所述第一绝缘层的预设区域去除,获取桥连布线层；
    在所述桥连布线层上铺设第二绝缘层，后对所述第二绝缘层进行开窗；
    在所述第二绝缘层上铺设第二导电层，后制作扇出线路；
    判断是否需要增加一层所述扇出线路，若是，则将所述扇出线路视作上述所述桥连布线层，重复上述操作至完成所述扇出线路；若否，则在所述扇出线路上铺设阻焊层，并对所述阻焊层的预设部分进行开窗。
  14. 根据权利要求13所述的芯片封装组件的制作方法，其中，所述第二绝缘层与所述桥连布线层靠近所述芯片的一侧共面。
  15. 根据权利要求13所述的芯片封装组件的制作方法，其中，所 述桥连布线层朝向所述芯片一侧的表面积远小于所述芯片朝向所述桥连布线层一侧的表面积。
PCT/CN2022/120713 2022-02-09 2022-09-23 芯片封装组件及其制作方法 WO2023151279A1 (zh)

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CN110299294A (zh) * 2019-07-31 2019-10-01 中国电子科技集团公司第五十八研究所 一种三维系统级集成硅基扇出型封装方法及结构
CN112514062A (zh) * 2018-07-24 2021-03-16 国际商业机器公司 具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构
CN114388471A (zh) * 2020-10-06 2022-04-22 欣兴电子股份有限公司 封装结构及其制作方法
CN114725054A (zh) * 2020-12-18 2022-07-08 英特尔公司 包括桥的微电子结构

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CN105826304A (zh) * 2015-01-27 2016-08-03 联发科技股份有限公司 芯片封装
CN112514062A (zh) * 2018-07-24 2021-03-16 国际商业机器公司 具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构
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