CN112514062A - 具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构 - Google Patents

具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构 Download PDF

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CN112514062A
CN112514062A CN201980048351.0A CN201980048351A CN112514062A CN 112514062 A CN112514062 A CN 112514062A CN 201980048351 A CN201980048351 A CN 201980048351A CN 112514062 A CN112514062 A CN 112514062A
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interconnect
die
package
bridge device
interconnect bridge
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CN201980048351.0A
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J.鲁宾
L.克莱文格
C.L.阿尔文
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International Business Machines Corp
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International Business Machines Corp
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Abstract

提供了多芯片封装结构和用于构造多芯片封装结构的方法，其利用芯片互连桥器件，该芯片互连桥器件被设计为在封装结构中的相邻芯片(或裸片)之间提供高互连密度，以及通过所述芯片互连桥器件提供垂直电源分布迹线，以从封装衬底向连接到所述芯片互连桥器件的所述芯片供应电源(和接地)连接。

Description

具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多 芯片封装结构
技术领域
本披露总体上涉及半导体封装技术，并且具体地涉及实现芯片互连桥器件的多芯片封装结构。
背景技术
半导体制造和封装技术中的创新已经使得能够开发更小规模、更高密度的集成电路(IC)芯片(或裸片)，以及开发具有使得能够密集封装IC芯片(或裸片)的布线和面积阵列输入/输出(I/O)触点密度的高度集成芯片模块。对于某些应用，使用用于模块到板I/O互连(例如，焊盘栅格阵列(LGA)或球栅阵列(BGA)连接)的合适区域阵列连接技术，用安装到电路板(例如，系统板(或节点卡)、印刷电路板、印刷线路板等)的一个或多个多芯片模块(MCM)来构造高性能电子模块。MCM技术可用于形成具有用于计算机服务器应用的多个IC处理器芯片或用于定制应用的多个异构芯片等的高密度封装的第一级封装结构。
可以利用不同常规技术来构建MCM封装结构。例如，MCM可通过将多个半导体IC裸片直接连接到封装衬底来构造。这些半导体IC裸片可以使用接线键合、胶带键合或倒装键合而连接至该封装衬底的表面上。对于高性能和高密度封装，直接芯片附接(DCA)技术通常使用形成在半导体IC裸片的有源表面上的触点焊盘与形成在封装衬底上的芯片安装表面(或顶侧表面)上的触点焊盘的匹配阵列之间的焊料互连的区域阵列将IC裸片倒装接合到封装衬底。该封装衬底包括用于在安装到封装衬底的顶侧的IC裸片之间提供裸片到裸片连接的布线以及用于将顶侧触点焊盘连接到底侧触点焊盘的布线。
在常规MCM技术中，封装基底可以是例如玻璃陶瓷基底、或层压基底。例如，可使用低温共烧陶瓷(LTCC)衬底技术来制造多层陶瓷封装衬底。此外，可使用表面层压电路(SLC)技术来制造层压封装衬底，以制造具有内建层的低成本有机封装衬底，该内建层通过微通路垂直连接以支持焊料凸起的倒装芯片。
持续需要具有增加的集成功能和更小的占用面积大小的IC芯片，这导致IC芯片的I/O计数和I/O密度的增加。此外，高性能和高密度集成封装解决方案通常需要用于倒装芯片连接的小微凸块，其使用例如50微米或更小的互连间距以及10微米或更小的线宽和线间隔设计规则。虽然MCM封装结构允许异构IC裸片通过封装衬底直接连接(例如，DCA)到彼此，但是常规的基于陶瓷的封装衬底和层压衬底技术在最小可实现的触点焊盘间距、线宽和线间隔方面受到限制。照此，常规的陶瓷和有机叠层构建衬底是高密度封装的瓶颈，因为这样的衬底技术不能支持高密度I/O倒装芯片连接和高密度裸片到裸片互连所需的紧密间距。
为了解决这些限制，利用2.5-D封装技术来增加I/O密度并且为低电源裸片到裸片通信提供高密度路由。通常，2.5-D集成涉及在无源中介衬底(例如，硅、玻璃或细间距有机构造衬底)上倒装接合多个IC裸片，其中无源中介衬底接合至封装衬底。与封装衬底相比，内插器包括更细间距的布线、更高的触点焊盘密度和用于裸片到裸片互连的更短的距离。
用于2.5D封装的硅中介板由硅薄层组成，所述硅薄层设置在IC裸片与封装衬底之间，并且所述硅薄层包括穿硅过孔(TSV)以便为I/O重新分布和裸片到裸片通信提供具有高布线密度的平台。硅中介层需要大且昂贵的具有TSV的硅芯片以容纳顶表面上的多个芯片。遗憾的是，由于需要硅中介片芯片尺寸来容纳附着于硅中介片表面的多个裸片的占用面积，以及由于使用增加了制造成本和复杂性的TSV技术，硅中介片是昂贵的。
另一方面，用于2.5D封装的细间距有机构造中介板利用薄膜技术在常规有机层压衬底的顶部上构造细间距有机再分布层。虽然细间距有机再分布层为平台提供了高布线密度以用于I/O再分配和裸片到裸片通信，但是与基于硅的内插件解决方案相比，这种技术在细间距再分配层的数量和可实现的最小线间距方面受到限制。
其他2.5D封装解决方案利用嵌入在封装衬底中的硅桥器件来在相邻裸片之间提供更紧密的互连密度。硅桥器件比常规的硅中介板成本更低，因为硅桥器件小得多(它们仅连接到相邻裸片的外围区域)并且不利用昂贵的TSV。尽管硅桥器件在形式上简单，但常规桥器件经设计以仅包含用于裸片到裸片互连的布线，而不包含用于例如从封装衬底穿过桥器件到裸片的垂直电源分布的布线。
然而，随着IC裸片功能和密度的增加，需要增加电源引脚和接地引脚的数量来最小化接地跳动。照此，IC裸片通常被制造为具有分散在IC裸片背面上的I/O触点焊盘的区域阵列之上的电源/接地焊盘。当硅桥器件用于高密度裸片到裸片I/O互连时，桥器件阻挡通过桥结构到布置在由桥器件重叠的IC裸片的高密度I/O区域内的电源/接地焊盘的垂直电源分布。照此，必须从封装衬底到IC裸片的不被桥器件重叠的其他区域进行到这样的电源/接地焊盘的连接，并且然后通过IC裸片(以及通过桥器件中的横向互连)路由到被桥器件阻挡的电源/接地焊盘。该配置增加了电源/接地迹线的长度，因此增加了封装衬底内的电压降和IR加热。
发明内容
本发明的实施例包括多芯片封装结构，这些多芯片封装结构包括芯片互连桥器件，这些芯片互连桥器件被设计成用于在封装结构中的相邻芯片之间提供高I/O互连密度，以及通过所述芯片互连桥器件提供垂直电源分布迹线，以从封装衬底向连接到所述芯片互连桥器件的芯片供应电源(和接地)连接。例如，一个实施例包括一种封装结构，其包括封装衬底、连接到封装衬底的互连桥器件、连接到互连桥器件和封装衬底的第一集成电路裸片、以及连接到互连桥器件和封装衬底的第二集成电路裸片。互连桥器件包括用于提供第一和第二集成电路裸片之间的裸片到裸片连接的布线，以及用于提供封装衬底与第一和第二集成电路裸片之间的封装到裸片连接的布线，其中封装到裸片连接包括电源连接。
将结合附图在以下实施例的详细描述中描述其他实施例。
附图说明
图1示意性地示出了根据本发明的实施例的包括芯片互连桥器件的多芯片封装结构。
图2示意性地展示了根据本发明的另一个实施例的包括芯片互连桥器件的多芯片封装结构。
图3是在制造的中间阶段的桥晶圆的截面侧视图，其中，包括接合焊盘的桥晶圆的背面的初始层形成在第一临时载体衬底上。
图4是在形成包括细间距信号线和垂直层间通孔的信号互连和重分布层的堆叠之后的图3的桥晶圆的横截面侧视图。
图5是在形成包括桥晶圆的粗间距接线、竖直层间通孔和顶侧键合焊盘的电源分布层的堆叠之后的图4的桥晶圆的横截面侧视图。
图6是在桥晶圆的顶侧键合焊盘上形成倒装芯片凸块之后的图5的桥晶圆的截面侧视图。
图7是在将第二临时载体衬底键合至桥晶圆的前侧之后的图6的桥晶圆的横截面侧视图。
图8是在从桥晶圆的背侧去除第一临时载体基底，在所述桥晶圆的所述背面上的所述接合焊盘上形成焊料凸块，以及切割所述桥晶圆和所述第二临时载体衬底以形成单独的芯片互连桥器件之后图7的桥晶圆的截面侧视图。
图9是处于组装中间阶段的封装结构的截面侧视图，其中，图8的芯片互连桥器件连接至封装衬底。
图10是在从芯片互连桥中去除第二临时载体衬底的剩余部分并且将多个IC芯片连接至芯片互连桥器件和封装衬底之后图9的封装结构的横截面侧视图。
图11是在将桥晶圆和第一临时载体衬底划片以形成单独的芯片互连桥器件之后的图6的桥晶圆的截面侧视图。
图12是处于组装中间阶段的封装结构的横截面侧视图，其中，安装至临时芯片载体衬底的多个IC芯片连接至图11的芯片互连桥器件。
图13是在从芯片互连桥器件的底侧移除第一临时载体衬底的剩余部分并且将IC芯片和芯片互连桥器件的组件连接至封装衬底之后的图12的封装结构的截面侧视图。
图14是根据本发明的实施例的示出了使用分层焊接工艺来组装封装结构进行芯片对准的对准焊盘的布置的IC芯片的后侧表面的平面图。
具体实施方式
现在将关于多芯片封装结构更详细地讨论本发明的实施例，该多芯片封装结构包括芯片互连桥器件，这些芯片互连桥器件被设计成用于在封装结构中的相邻芯片之间提供高I/O互连密度，以及通过所述芯片互连桥器件提供垂直电源分布迹线，以从封装衬底向连接到所述芯片互连桥器件的芯片供应电源(和接地)连接。应当理解，附图中所示的各个层、结构和区域是未按比例绘制的示意性图示。此外，为了便于解释，在给定附图中可能未明确示出通常用于形成某种类型的半导体器件或结构的一个或多个层、结构和区域。这并不意味着从实际半导体结构中省略了未明确示出的任何层、结构和区域。
此外，应理解的是，本文讨论的实施例不限于在此示出和描述的具体材料、特征和工艺步骤。具体地，关于半导体工艺步骤，要强调的是，本文中所提供的描述不旨在涵盖形成功能半导体集成电路器件可能需要的所有工艺步骤。而是，为了描述的经济性，本文中有目的地不描述通常用于形成半导体器件的某些工艺步骤，例如湿式清洁和退火步骤。
此外，贯穿附图，相同或相似的参考号用于表示相同或相似的特征、元件、或结构，并且因此，将不针对每幅附图重复对相同或相似的特征、元件、或结构的详细说明。应理解，如在此使用的关于厚度、宽度、百分比、范围等的术语“约”或“基本上”旨在表示接近或近似，但不是精确地。例如，如在本文使用的术语“约”或“基本上”暗指可以存在小的误差界限，如小于规定量的1％或更少。
图1示意性地示出了根据本发明的实施例的包括芯片互连桥器件的多芯片封装结构。具体地，图1示意性地展示了封装体结构100，该封装体结构包括封装体衬底110、第一和第二芯片互连桥器件120和130(或“桥器件”)、多个IC裸片140、142和144以及封装体盖150。接合层152(例如，环氧树脂胶)将封装盖150接合至封装衬底110的顶侧上的外围表面区域。在IC裸片140、142、144与封装衬底110之间设置底部填充材料160，并且在IC裸片140、142和144的顶侧与封装盖150之间设置热界面材料162。底部填充材料160包括电绝缘粘合剂材料，用于保持(i)IC裸片140、142、144和封装衬底110之间，(ii)IC裸片140、142、144和桥器件120和130之间，以及(iii)桥器件120和130以及封装衬底110之间的倒装芯片连接的结构完整性。在替换实施例中，底部填充材料160可以由不同的底部填充材料层组成，例如，桥区中的一个底部填充材料层和桥区外部的另一底部填充材料层。热界面材料162包括导热膏，该导热膏被设计为将由IC裸片140、142和144产生的热能传导到封装盖150，其中封装盖150用作散热器以消散热能并冷却IC裸片140、142和144。
对于异构封装应用，IC裸片140、142和144可以包括用于实现给定应用的任何类型的集成电路和系统。出于说明性目的，图1的示例性封装结构100示出了三个IC裸片，其中，第一IC裸片140包括高带宽存储器(HBM)动态随机存取存储器(DRAM)器件，第二IC裸片142包括硬件加速器器件，并且其中，第三IC裸片144包括多核处理器器件。在其他实施例中，IC裸片140、142和144(以及其他附加的IC裸片)可以包括一个或多个存储器器件、中央处理单元(CPU)、微控制器、专用集成电路(ASIC)、现场可编程门阵列(FPGA)，以及其他类型的通用处理器或工作负载优化处理器，诸如图形处理单元(GPU)、数字信号处理器(DSP)、片上系统(SoC)和配置成执行一个或多个固定功能的其他类型的专用处理器或协处理器。
封装衬底110可以是陶瓷衬底、硅衬底或有机层压构建衬底、或适用于给定应用的任何其他类型的封装衬底技术。封装衬底110包括形成在封装衬底110的底侧上的焊球互连112(例如，球栅阵列(BGA)焊接互连)的区域阵列、垂直和水平延伸穿过封装衬底110的封装迹线网络114、以及形成在封装衬底110的顶侧中的第一凹腔116和第二凹腔118。在图1的示例性实施方式中，第一桥器件120布置在封装衬底110的第一凹腔116中，并且第二桥器件130布置在封装衬底110的第二凹腔118中。
第一桥器件120使用倒装芯片凸块连接170的区域阵列连接至第一和第二IC裸片140和142，并且第二桥器件130使用倒装芯片凸块连接的区域阵列172连接至第二和第三IC裸片142和143。进一步，第一桥器件120使用倒装芯片凸块连接180的区域阵列在第一凹腔116的底部处连接到封装衬底110的表面。类似地，第二桥器件130使用倒装芯片凸块连接182的区域阵列连接到第二凹腔118的底部处的封装衬底110的表面。IC裸片142和144使用倒装芯片凸块连接184和186的相应区域阵列连接到封装衬底110的顶侧。
在一个实施例中，倒装芯片凸块连接170和172的区域阵列包括用于相邻裸片之间的高密度I/O信号通信的微凸块，其中，取决于应用，倒装芯片微凸块连接170和172以约55微米或更小的触点间距形成。进一步，倒装芯片凸块连接180、182、184和186包括(i)封装衬底110与桥器件120和130以及(ii)封装衬底110与IC裸片142和144之间的I/O连接。在一个实施例中，倒装芯片凸块连接180、182、184和186具有比倒装芯片凸块连接170和172更粗糙的间距。在另一实施例中，倒装芯片凸块连接184和186包括细间距微凸块连接。在一个实施例中，取决于应用，倒装芯片凸块连接180、182、184和186的区域阵列被形成为具有约75微米或更大的触点间距。焊球互连112的区域阵列(例如)。取决于应用，封装衬底110的底侧上的焊球互连112(例如BGA C4)形成为具有约300微米或更大的触点间距。
第一桥器件120包括细间距布线122，该细间距布线用于连接微凸块170的区域阵列以提供第一和第二IC裸片140和142之间的高密度、高带宽I/O连接性。类似地，第二桥器件130包括用于连接微凸块172的区域阵列的细间距布线132，以便在第二和第三IC裸片142和144之间提供高密度、高带宽的I/O连接性。桥器件120和130的细间距布线122和132可以使用以下进一步详细讨论的桥制造技术用亚微米线宽和线间距设计规则形成。
此外，第一桥器件120包括竖直分布迹线124以提供从封装衬底110通过第一桥器件120到第一IC裸片140和/或第二IC裸片142的直接电源和接地连接。类似地，第二桥器件130包括垂直分布迹线134，以提供从封装衬底110通过第二桥器件130到第二IC裸片142和/或第三IC裸片144的直接电源和接地连接。如上所述，利用高密度IC裸片功能和I/O，多个电源和接地焊盘可以包括在IC裸片140、142和144的微凸块170和172的区域阵列内以最小化接地跳动。
在图1的封装结构中，第一和第二桥器件120和130被设计成用于通过桥器件120和130向布置在IC裸片140、142和144的高密度I/O区域阵列170和172内的电源/接地焊盘提供垂直电源/接地分布，该垂直电源/接地分布被桥器件120和130覆盖。照此，到IC裸片140、142和144的高密度I/O区域阵列170和172内的这种电源/接地焊盘的连接可以通过桥器件120和130从封装到裸片直接进行。例如，如图1所示，到第一IC裸片140的电源/接地连接可以沿着从封装衬底110的封装迹线114的路径布线，到封装衬底110与第一桥器件120之间的倒装芯片连接180，通过第一桥器件120到垂直迹线124，并且通过第一桥器件120与第一IC裸片140之间的倒装芯片连接170到第一IC裸片140。
这与不包括如图1中所示的竖直分布迹线124和134的常规桥器件相反。例如，假设图1中的第一桥器件120不包括垂直电源/接地分布布线124，并且到第一IC裸片140的倒装芯片连接170的区域阵列包括电源/接地连接。在这种情况下，到第一IC裸片140的电源/接地连接将必须沿着从封装衬底110的封装迹线114，到第二IC裸片142和封装衬底110之间的倒装芯片连接184，到第二IC裸片142外围的倒装芯片连接184和倒装芯片连接170之间的分布布线，以及通过第一桥器件120的重分布布线122连接到第一IC裸片140的倒装芯片连接170的区域阵列内的电源/接地连接的路径布线。此常规配置将显著增加电源/接地迹线的长度(与如上所述通过第一桥器件120从封装到裸片的直接连接相比)。
虽然为了便于说明，在图1中总体上说明了倒装芯片凸块连接170、172、180、182、184和186，但应理解的是，可以使用任何合适的倒装芯片凸块技术来实现倒装芯片凸块连接170、172、180、182、184和186。例如，倒装芯片凸块连接170、172、180、182、184和186可以使用受控塌陷芯片连接(C4)倒装芯片凸块技术来实现，其中，在球限制冶金(BLM)焊盘或凸块下金属化(UBM)焊盘上形成焊球。焊球可以通过锡膏印刷或电镀形成。在其他实施例中，倒装芯片凸块连接170、172、180、182、184和186可以是包括形成在金属焊盘上的金属柱结构(例如，铜柱)的芯片连接(C2)凸块。金属柱状凸块结构可以具有或可以不具有焊料端盖。在其他实施例中，倒装芯片凸块连接170、172、180、182、184和186可以是具有形成在UBM焊盘上的电镀金属的C2凸块。
在其他实施例中，包括Cu和Sn的焊料微凸块可以电镀在UBM焊盘上，其中，UBM焊盘包括无电镀镍和浸金。两个倒装芯片元件的接合可通过将一个倒装芯片元件上的CuSn焊料微凸块接合到另一倒装芯片元件上的UBM垫或通过将一个倒装芯片元件上的CuSn焊料微凸块接合到另一倒装芯片元件上的CuSn焊料微凸块来执行。在其他实施例中，一个倒装芯片元件上的铜柱凸块的区域阵列可接合到另一倒装芯片元件上的焊球的区域阵列。此外，形成于一个倒装芯片元件上的UBM垫上的高温焊料凸块的区域阵列可接合到形成于另一倒装芯片元件的触点垫上的低温焊料凸块的区域阵列。
如图1中进一步所示，在一些实施例中，第一IC裸片140(例如，HBMDRAM)的占用面积完全或基本上与互连桥器件120重叠，从而使得第一集成电路裸片140与封装衬底110之间的所有输入/输出、电源/接地和其他连接通过互连桥器件120路由。在封装结构的一些实施例中，可以存在小的IC裸片(相对于诸如加速器(例如，GPU)之类的大的IC裸片)，其具有桥器件，该桥器件完全支持较小的IC裸片的占用面积，同时仅与较大的IC裸片部分重叠。在这种情况下，桥器件可以是不规则形状的(例如，非矩形)，以便容纳附接到桥的较小和较大的IC裸片两者。形成完全支持小IC裸片的桥器件存在不同优点。例如，对于诸如HBM DRAM的小IC裸片，凸块占用面积的各个区域之间的间距可以非常小(例如，电源区域和信号I/O区域之间的间距可以是75微米或更小)。凸块区域之间的这种紧密间隔使得仅使用小IC裸片的凸块占用面积的一部分将小IC裸片安装至桥器件，同时仍在桥器件的区域之外容纳具有封装层压衬底的凸块非常困难。在这种情况下，可能不可能在桥器件的边缘附近接合一些凸块。另外，对于具有所有微凸块的IC裸片，可能难以将IC裸片倒装安装到桥器件和具有微凸块的封装层压衬底两者，因为它们都处于精细间距。因此，在这种情况下，更容易将整个IC裸片倒装安装到桥器件上。
图2示意性地示出了根据本发明的另一个实施例的包括芯片互连桥器件的多芯片封装结构。具体地，图2示意性示出了类似于图1的封装结构100的封装结构200，除了在图2的封装结构200中，与设置和安装在封装衬底110的凹陷空腔116和118内相比，第一桥器件120和第二桥器件130安装至封装衬底110的顶侧。
此外，在图2中所示的示例性实施例中，IC裸片142和144与封装衬底110之间的倒装芯片连接184和186的区域阵列包括形成在封装衬底110的顶侧上的支架结构210以偏移桥器件120和130的高度。此外，可以在IC裸片142和144的背面上的区域阵列触点焊盘上形成较大直径的焊料凸块(或较高凸块结构)212，以偏移桥器件120和130的高度。在一个实施例中，如图2示意性所示，支架结构210包括焊料涂覆的铜球，其设置在形成于封装衬底110的顶侧上的区域阵列触点焊盘上。在另一个实施例中，支架结构210可以包括铜柱、或具有焊料端盖的铜柱、或适用于给定应用的其他类型的支架结构。
现在将参见图4至图14进一步详细讨论用于制造芯片互连桥和构造包括芯片互连桥的多芯片封装结构的不同方法。通常，使用晶圆级扇出(WLFO)技术结合后段制程(BEOL)制造方法以及公共BEOL电介质和金属材料在临时载体衬底上形成根据本发明的实施例的互连桥，以形成包括多个布线层和层间过孔的桥结构，这些多个布线层和层间过孔提供用于封装裸片之间的高带宽I/O通信的高密度裸片到裸片互连布线，以及重分布层，所述重分布层用于将电源/接地连接从与所述封装衬底的所述底侧倒装芯片连接通过所述桥结构路由到与所述IC裸片的所述顶侧倒装芯片连接。此外，在一个实施例中，实现“芯片优先”封装组装工艺，该工艺包括将桥器件倒装键合至两个或更多个IC裸片，并且然后将桥器件和IC裸片的组件倒装键合至封装衬底。在另一个实施例中，实现“最后芯片”封装装配工艺，该工艺包括将桥器件倒装键合至封装衬底，并且然后将两个或更多个IC裸片倒装键合至桥器件和封装衬底的组装。
具体地，图3至图10示意性地示出了根据本发明的实施例的用于制造桥器件的工艺以及“最后芯片”封装体组装工艺。首先，图3是在制造的中间阶段的桥晶圆的横截面侧视图，其中，在第一临时载体衬底上形成包括接合焊盘的桥晶圆的背面的初始层。具体地，图3示出了第一临时载体衬底300(或载体晶圆)，在其上将使用WLFO和BEOL工艺技术来形成包括多个单独的桥器件的桥晶圆。例如，第一临时载体衬底300可以是玻璃衬底或硅衬底。此外，图3示出了桥接晶圆形成的初始阶段，其中在第一临时载体衬底300的表面上施加粘合层302。粘合剂层302由任何适合的粘合剂材料(例如，环氧树脂)形成，该粘合剂材料充当可以使用适合的释放技术(例如IR激光烧蚀)烧蚀或蒸发的释放层以在制造工艺流程中的稍后阶段释放第一临时载体衬底300。在另一实施例中，当第一临时载体衬底300包括硅载体衬底时，桥晶圆可以直接在硅载体衬底的表面上(没有粘合层302)形成，使得可以随后使用硅研磨工艺去除硅载体衬底。当利用粘合剂层接合到桥晶圆时，可以利用各种技术(例如，激光烧蚀)来释放玻璃或硅载体衬底。
接下来，在粘合剂层302上形成接合焊盘层310。接合焊盘层310包括钝化层312和接合焊盘314的区域阵列。在一个实施例中，通过沉积和图案化电介质/绝缘材料层(作为钝化层312)以形成沟槽，并且沉积金属材料层(例如，铜)以用金属材料填充沟槽以形成接合焊盘314来形成接合焊盘层310。然后执行化学机械抛光(CMP)工艺以去除过载金属材料并且使接合焊盘层310向下平坦化到钝化层312的表面。在另一实施例中，钝化层312可包含有机聚合物材料。尽管为了便于说明在图3中示出了接合焊盘层310的一小部分，但是接合焊盘层310是被形成以包括用于桥晶圆的多个桥器件的底侧接合焊盘的区域阵列。在替换实施例中，接合焊盘层310可在移除第一临时载体衬底300之后使用背面工艺模块来形成。在又一个实施例中，除了形成在桥接晶圆的正面上形成的重分布层之外或替代在桥接晶圆的正面上形成的重分布层，桥接晶圆可包括形成在桥接晶圆的背面上的有机重分布层的堆叠。
接下来，图4是在形成包括细间距信号线和垂直层间通孔的信号互连和重分布层320的堆叠之后的图3的桥晶圆的横截面侧视图。具体而言，信号互连和重分布层320的堆叠包括多个金属化层和金属互连结构，该多个金属化层包括层间电介质(ILD)层322，该金属互连结构包括垂直过孔324(和相关联的过孔接地焊盘)和嵌入在ILD层322中的水平布线326。ILD层322可以使用通常用于BEOL制造的电介质材料形成，包括但不限于氧化硅、氢化碳氧化硅(SiCOH)、SiCH、SiCNH或其他类型的硅基低k电介质(例如，k小于约4.0)，多孔电介质或已知的ULK(超低k)电介质材料(k小于约2.5)。ILD层322可使用已知的沉积技术来沉积，例如原子层沉积(ALD)、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、物理气相沉积(PVD)或旋涂沉积。
嵌入在ILD层322内的垂直过孔324和水平布线326共同提供高密度的裸片到裸片的I/O互连、以及用于将底侧键合焊盘312连接至桥晶圆的顶侧键合焊盘的重分布布线。垂直过孔324和水平布线326(包括过孔接地焊盘)可以使用通常用于BEOL制造的金属材料(包括但不限于铜、钴、钌等)来形成。例如，在一个实施例中，使用单和/或双镶嵌金属化工艺用铜形成垂直通孔324和水平布线326。此外，取决于用于形成ILD层322以及垂直过孔324和水平布线326的电介质和金属材料，可以使用已知的材料和沉积技术在金属沉积之前将薄扩散阻挡层和种子层沉积到在ILD层322中形成的线沟槽。
接下来，图5是在形成电源分布层330的堆叠之后的图4的桥晶圆的横截面侧视图，该电源分布层包括桥晶圆的粗间距接线、竖直层间通孔和顶侧键合焊盘。具体地，电源分配层330的堆叠包括多个绝缘层332和金属互连结构，该金属互连结构包括垂直过孔334(和相关联的过孔接地焊盘)、水平布线336和顶侧接合焊盘338。在一个实施例中，使用标准有机层压构建层来形成电源分布层330的堆叠，其中绝缘层332由有机材料(例如，聚酰亚胺、FR4等)形成。有机内建层的使用促进更厚的布线和互连的制造，以用于通过桥结构的电源分布的目的，同时还提供从顶侧焊盘338到信号互连和重分布层320的堆叠的垂直过孔连接。在其他实施例中，可以利用与用于制造信号互连和重分布层320的堆叠的BEOL工艺不同的设计规则，使用标准BEOL制造方法来制造电源分布层330的堆叠。图5所示的所得桥接晶圆结构包括厚度T，该厚度T在约50微米至约70微米的范围内。
图6是在桥晶圆的顶侧键合焊盘338上形成倒装芯片凸块340之后的图5的桥晶圆的截面侧视图。倒装芯片凸块340可以使用不同技术中的一种来形成。例如，倒装芯片凸块340可以是形成在UBM或BLM焊盘上的C4焊料凸块。在另一个实施例中，倒装芯片凸块340可以是使用化学镀技术在接合焊盘338上形成的电镀凸块(例如，镍、铜、金、镀锡凸块)。在另一实施例中，倒装芯片凸块可以是具有或不具有焊料端盖的铜柱结构。
接下来，图7是在将第二临时载体衬底360接合到桥晶圆的前侧之后的图6的桥晶圆的横截面侧视图。具体地，图7示出了示范性实施例，其中，可释放的粘合剂层350被施加到桥晶片的顶侧，并且其中，第二临时载体衬底360通过粘合剂层350接合到桥晶片。第二临时载体衬底360是在需要背侧工艺(例如，研磨掉第一临时载体衬底300和粘合层302，或者在底侧接合焊盘314上形成倒装芯片凸块等)时使用的可选结构。在另一实施例中，当不需要桥晶圆的背侧工艺时，桥晶圆可面朝下安装在晶圆切片带上，接着移除第一临时载体衬底300，且将桥晶圆切片成个别桥器件。
图8是在从桥晶圆的背侧去除第一临时载体衬底300之后图7的桥晶圆的横截面侧视图，在桥晶圆的背侧上的接合焊盘314上形成焊料凸块370(例如，C4焊料凸块)，以及沿着切割线D(由虚线示出)切割桥晶圆和第二临时载体衬底360以形成单独的芯片互连桥器件400。在组装工艺的替代实施例中，桥晶圆的背侧工艺包括移除第一临时载体衬底300，但不在桥晶圆的底侧接合焊盘314上形成倒装芯片凸块。在这种情况下，接合焊盘314将接合到在封装衬底的表面上形成的区域阵列倒装芯片凸块。在又一实施例中，如上所述，可在移除第一临时载体衬底300之后执行背侧工艺，以在桥晶圆的暴露的背侧上形成焊盘阵列或再分布层等。
图9是封装结构在组装的中间阶段的截面侧视图，其中，图8的芯片互连桥器件400连接至封装衬底410。封装衬底410包括形成于封装衬底410的表面上的接合焊盘412(或柱结构或焊料封盖凸块等)的区域阵列。在一个实施例中，图9中所示的封装衬底410的部分的表面区域是封装衬底410的凹腔的底面，桥器件400设置在该凹腔中(例如，图1)。在另一个实施方式中，图9中示出的封装衬底410的部分的表面区域是封装衬底410的上表面，封装衬底410上布置有桥器件400(例如，图2)。在又一实施例中，图9中所示的焊料凸块370可最初形成在封装衬底410的接合焊盘412上，其中桥器件400的底侧接合焊盘314将接合到封装衬底410的焊料凸块370。芯片互连桥器件400可以使用焊料回流或热压接合连接到封装衬底410。
接下来，图10是在从芯片互连桥器件400中去除第二临时载体衬底360(或晶圆切片带)的剩余部分并且将多个IC芯片420和430倒装芯片连接至芯片互连桥器件400之后的图9的封装结构的横截面侧视图。IC芯片420和430包括倒装芯片凸块422和432的相应细间距区域阵列，倒装芯片凸块422和432接合到桥器件400的顶侧上的细间距倒装芯片凸块340。此外，虽然在图10中未具体示出，但是IC芯片420和430将使用较粗间距倒装芯片连接(例如，C4连接、焊料覆盖的铜柱等)倒装芯片接合至封装衬底410，如以上参见图1和2所讨论的。IC芯片420和430可以使用焊料回流或热压结合连接到桥器件400和封装衬底410。
图11至图13示意性地示出了根据本发明的实施例的在图1至图6的桥接晶圆制造工艺之后的“芯片优先”封装体组装工艺。具体地，图11是在沿着切割线D(由虚线示出)切割桥晶圆和第一临时载体衬底300以形成单独的芯片互连桥器件400之后的图6的桥晶圆的截面侧视图。在该组装工艺中，第一临时载体衬底300在晶圆切割工艺期间保持接合至桥接晶圆，使得由切割工艺形成的各个桥接器件由第一临时载体衬底300的相应部分支撑，如图11所示。
接下来，图12是处于组装中间阶段的封装结构的截面侧视图，其中，安装至临时芯片载体衬底500的多个IC芯片420和430连接至图11的芯片互连桥器件400。使用任何合适的可释放的粘合剂层505将芯片载体衬底500结合到IC芯片420和430。在另一个实施例中，可以利用精密夹具来利用真空系统或可释放的粘合剂层临时保持IC芯片420和420。IC芯片420和430包括倒装芯片凸块422和432的相应细间距区域阵列，倒装芯片凸块422和432接合到桥器件400的顶侧上的细间距倒装芯片凸块340。此外，IC芯片420和430包括倒装芯片凸块424和434的区域阵列(例如，C4连接、焊料覆盖的铜柱等)，其可以粗间距或细间距形成。倒装芯片凸块424和434可以是尺寸与倒装芯片凸块422和432相同但间距松弛的凸块/柱。IC芯片420和430可以使用焊料回流或热压结合而连接到桥器件400上。
图13是在从桥器件400的底侧去除第一临时载体衬底300的剩余部分，以及将图12的IC芯片420和430以及芯片互连桥器件400的组件连接到封装衬底510之后的图12的封装结构的截面侧视图。封装衬底510包括形成在封装衬底510的顶侧表面中的凹腔512。封装衬底510包括形成在封装衬底510的顶侧表面上的接合焊盘512的区域阵列，接合焊盘512接合到IC芯片420和430的背侧上的区域阵列倒装芯片凸块424和434。此外，封装衬底510包括形成在凹腔512的底表面上的倒装芯片凸块516的区域阵列，倒装芯片凸块516接合至在桥器件400的底表面处暴露的接合焊盘的区域阵列的相应的接合焊盘314。应当理解，示例性芯片优先组装方案可用于组装包括安装到层压封装衬底的顶侧的桥结构的封装结构。
以上所讨论的示例性桥制造和组装封装技术利用WLFO技术和细间距BEOL图案化使得能够形成互连桥器件400，该互连桥器件在相邻芯片420与430之间提供高互连密度，同时使用桥器件400中的堆叠布线和通孔实现通过桥器件400的垂直电源分布，堆叠布线和通孔提供用于路由和分布封装衬底510和桥器件400的底侧之间的电源/接地凸块连接到IC芯片420和430与桥器件400的顶侧表面之间的电源/接地凸块连接的封装迹线。在一个替代实施例中，芯片互连桥可以用面板工艺和放松的特征尺寸建立在陶瓷或有机载体上。
在其他实施例中，实现焊料层级以组装包括封装衬底、桥器件和IC芯片的封装结构。焊料层级将取决于实现“芯片优先”还是“芯片最后”组装工艺来构建封装结构而变化。焊料分层结构考虑了倒装芯片凸块连接的潜在未对准，这可能在直接芯片附接操作期间由于以下原因而出现，例如，(i)构成IC裸片和互连桥器件的不同材料的热膨胀系数(CTE)的差异，以及(ii)较大的粗间距焊料凸块的表面张力，其可导致，例如，在焊料回流期间，较小的未对准，细间距焊料凸块。
例如，通过“芯片优先”组装过程，低温焊料可以用于IC芯片与桥器件之间的小的、精细间距的微凸块连接。低温焊料使得能够在较低温度下接合桥器件和IC芯片，这使得IC芯片和桥器件之间的差分膨胀最小化。以此方式，低温焊料将在低温下回流和接合，并且使IC裸片与桥互连结构之间的差分膨胀最小化。因此，当组件冷却时，收缩的IC裸片将不会在互连桥器件上引起相当大的应力，否则这可能引起互连桥器件的弯曲和开裂。
可以用“芯片最后”组装工艺来实现根据本发明的实施例的不同焊料层级结构。如上所述，通过“芯片最后”组装工艺，互连桥器件最初是直接芯片附接至封装衬底，之后是将IC裸片直接芯片附接至桥器件和封装衬底两者。在此组装工艺中，使用细间距凸块互连来接合IC裸片和桥器件，且使用粗间距凸块互连来接合IC裸片和封装衬底。如下面进一步详细解释的，在IC裸片和封装衬底之间接合较粗的间距凸块互连之前，可以利用不同的焊接层级来确保IC裸片和桥器件之间的精细间距凸块互连的对准和接合。
在一个实施例中，每个IC裸片包括具有两个尺寸C4的倒装芯片凸块，例如，150微米间距凸块(粗间距凸块)(如SAC305或SnBi95)和55微米间距凸块(细间距凸块)(如SAC305或SnBi95)。此外，桥器件包括细间距微凸块，这些细间距微凸块包括形成在桥器件的接合焊盘上的以138℃熔化的的低温熔化焊料(如SnBi(58％))。在焊料回流期间，桥器件的接合焊盘上的低温焊料将首先熔化并且拉动IC裸片的底侧上的相应细间距凸块，这导致IC裸片与桥器件和封装衬底两者对准。使用这种工艺，通过例如在一侧上使用小质量的低熔点焊料并且在另一侧上使用大量低熔点焊料，或通过在低熔点侧上使用将被拉入熔体中的冶金(例如金)，将元件结合到熔体中。
“芯片最后”组装方法的焊料层级结构的其他实施例利用IC裸片的背侧上的对准焊盘。例如，图14是根据本发明的实施例的IC裸片500的背侧表面的平面图，其示出了用于使用分层焊接工艺来组装封装结构的芯片对准的对准焊盘的布置。IC芯片500的背侧包括凸块互连区域502，该区域包括用于将IC裸片500直接芯片贴装到封装衬底的标准粗间距C4凸块，以及用于将IC裸片500直接芯片贴装到桥器件的细间距微凸块504(例如，55微米间距)。细间距微凸块504包括具有比凸块互连区域502中的粗间距凸块更低的熔化温度(例如，低20℃)的焊料。此外，IC裸片500的背侧包括在IC裸片500的拐角中的对准焊盘区域506，所述对准焊盘区域506具有带有最低熔化温度焊料的大间距对准焊盘，以及具有带有最低熔化温度焊料的精细间距(例如，20至40微米间距)的对准焊盘区域508。
在一个实施例中，焊料分层结构利用布置在IC裸片500的拐角上的对准焊盘区域506中的具有最大间距C4(例如，250微米间距)的三个尺寸C4以用于总体对准。特别地，IC裸片500在对准焊盘506上包括最低温度熔化的焊料(例如，118摄氏度)以进行总体对准。桥器件的精细间距凸块区域504(例如，55微米间距)具有次低温熔化焊料(例如，138摄氏度)，并且区域502中的标准C4凸块(例如，150微米间距)具有最高温度熔化焊料。
在另一个实施例中，焊料分层结构利用具有最小间距/大面积的三个尺寸的C4用于更精细的对准(比桥器件所需要的更精细)。具体地，精细间距对准区域(例如，20微米至40微米间距)具有用于超精细对准的具有最低温度熔化焊料(例如，118摄氏度)的焊料凸块。桥器件的精细间距凸块区域504(例如，55微米间距)具有次低温熔化焊料(例如，138摄氏度)，并且区域502中的标准C4凸块(例如，150微米间距)具有最高温度熔化焊料。
尽管在此已经参考附图描述了示例性实施例，但是应当理解的是，本发明不限于那些精确的实施例，并且在不脱离所附权利要求的范围的情况下，本领域技术人员可以在其中进行各种其他改变和修改。

Claims (20)

1.一种封装结构，包括：
封装衬底；
连接到所述封装衬底的互连桥器件；
连接到所述互连桥器件和所述封装衬底的第一集成电路裸片；以及
连接到所述互连桥器件和所述封装衬底的第二集成电路裸片；
其中，所述互连桥器件包括用于在所述第一和第二集成电路裸片之间提供裸片到裸片连接的布线，以及用于在所述封装衬底与所述第一和第二集成电路裸片之间提供封装到裸片连接的布线，其中，所述封装到裸片连接包括电源连接；
其中，所述互连桥器件以及所述第一和第二集成电路裸片连接到所述封装衬底的平面顶侧表面；
布置在所述封装衬底的所述平面顶侧表面与所述第一集成电路裸片和所述第二集成电路裸片之间的支架连接结构，其中所述支架连接结构提供所述封装衬底与所述第一集成电路裸片和所述第二集成电路裸片之间的裸片到封装连接，其中所述支架连接结构被配置以偏移安装到所述封装衬底的所述平面顶侧表面的所述互连桥器件的高度；以及
底部填充层，所述底部填充层安置于所述封装衬底的所述平面顶侧表面与所述第一和第二集成电路裸片之间，其中所述支架连接结构和所述互连桥器封装于所述底部填充层中。
2.如权利要求1所述的封装结构，其中，所述支架结构包括铜柱结构和焊料涂覆的铜球中的一个，所述铜柱结构和所述焊料涂覆的铜球形成在所述封装衬底的所述顶侧表面上的触点焊盘上。
3.如权利要求1所述的封装结构，其中：
所述第一集成电路裸片使用第一互连凸块阵列连接到所述互连桥器件的顶表面；
所述第二集成电路裸片使用第二互连凸块阵列连接到所述互连桥器件的所述顶面；
所述互连桥具有使用第三互连凸块阵列连接到所述封装衬底的所述平面顶侧表面的底表面；
所述第一和第二互连凸块阵列具有第一连接间距；
所述第三互连凸块阵列具有第二连接间距；以及
所述第一连接间距小于所述第二连接间距。
4.如权利要求3所述的封装结构，其中所述第一连接间距为55微米或更小，并且其中所述第二连接间距大于55微米。
5.如权利要求1所述的封装结构，其中，所述互连桥器件包括多层无机电介质材料和图案化的金属化的构建以提供层间通孔和横向迹线以形成所述互连桥器件的所述布线。
6.如权利要求5所述的封装结构，其中，所述多层无机电介质材料和所述图案化金属化的构建包括使用后段制程制造工艺形成的后段制程互连结构。
7.如权利要求5所述的封装结构，其中，所述互连桥器件包括具有图案化的金属化的至少一个有机电介质层，所述图案化的金属化提供用于所述封装到裸片连接的所述布线。
8.如权利要求1所述的封装结构，其中所述第一集成电路裸片包括存储器裸片，并且其中所述第二集成电路裸片包括处理器裸片。
9.如权利要求1所述的封装结构，其中，所述第一集成电路裸片的占用面积与所述互连桥器件的占用面积完全重叠，使得所述第一集成电路裸片与所述封装衬底之间的所有输入/输出都被路由通过所述互连桥器件。
10.如权利要求1所述的封装结构，其中，所述封装衬底包括陶瓷基底衬底和有机层压件构造衬底中的一个。
11.一种用于构造封装结构的方法，包括：
在第一载体衬底上构造互连桥晶圆，其中，所述互连桥晶圆包括形成在所述第一载体衬底上的第一接合焊盘层，第二接合焊盘层，以及所述第一与第二接合焊盘层之间的多个电介质层和金属化层，以在所述第二接合焊盘层的接合焊盘之间提供互连布线，并且在所述第一与第二接合焊盘层的接合焊盘之间提供互连布线；
将第二载体衬底附接到所述互连桥晶圆的所述第二接合焊盘层；
去除所述第一载体衬底以暴露所述第一接合焊盘层；
切割所述互连桥晶圆和所述第二载体衬底以形成互连桥器件，所述第二载体衬底的一部分连接到所述互连桥器件；
将所述互连桥器件的所述第一接合焊盘层直接芯片附接至封装衬底；
去除所述第二载体衬底的连接至所述互连桥器件的所述部分以暴露所述互连桥器件的所述第二接合焊盘层；以及
将第一集成电路裸片和第二集成电路裸片直接芯片附接至所述互连桥器件的所述第二接合焊盘层和所述封装衬底；
其中，所述互连桥器件的所述第二接合焊盘层的所述接合焊盘之间的所述互连布线在连接到桥器件的所述第一和第二集成电路裸片之间提供裸片到裸片互连；
其中所述第一接合焊盘层和所述第二接合焊盘层中的所述接合焊盘之间的所述互连布线提供所述封装衬底与所述第一和第二集成电路裸片之间的封装到裸片连接，其中所述封装到裸片连接包括电源连接；
其中，所述互连桥器件以及所述第一和第二集成电路裸片连接到所述封装衬底的平面顶侧表面；
其中，直接芯片附接包括在所述封装衬底的所述平面顶侧表面与所述第一和第二集成电路裸片之间形成支架连接结构，其中所述支架连接结构提供所述封装衬底与所述第一和第二集成电路裸片之间的裸片到封装连接，其中所述支架连接结构被配置以偏移安装到所述封装衬底的所述平面顶侧表面的所述互连桥器件的高度；以及
在所述封装衬底的所述平面顶侧表面与所述第一和第二集成电路裸片之间形成底部填充层，其中所述支架连接结构和所述互连桥器件被封装于所述底部填充层中。
12.如权利要求11所述的方法，其中，使用后段制程工艺逐层构造所述互连桥晶圆。
13.如权利要求11所述的方法，进一步包括：在将所述互连桥器件直接芯片附接至所述封装衬底之前，在所述互连桥器件的所述第一接合焊盘层的所述接合焊盘上形成互连凸块。
14.如权利要求11所述的方法，进一步包括：在将所述第一和第二集成电路裸片直接芯片附接至所述互连桥器件之前，在所述互连桥器件的所述第二接合焊盘层的所述接合焊盘上形成互连凸块。
15.一种用于构造封装结构的方法，包括：
在载体衬底上构造互连桥晶圆，其中，所述互连桥晶圆包括在所述第一载体衬底上形成的第一接合焊盘层，第二接合焊盘层，以及所述第一与第二接合焊盘层之间的多个电介质层和金属化层，以在所述第二接合焊盘层的接合焊盘之间提供互连布线，并且在所述第一与第二接合焊盘层的接合焊盘之间提供互连布线；
切割所述互连桥晶圆和所述载体衬底以形成互连桥器件，其中所述载体衬底的一部分连接到所述互连桥器件；
将第一集成电路裸片和第二集成电路裸片直接芯片附接至所述互连桥器件的所述第二接合焊盘层；
去除所述载体衬底的连接至所述互连桥器件的部分以暴露所述互连桥器件的所述第一接合焊盘层；以及
将所述互连桥器件的所述第一接合焊盘层以及所述第一和第二集成电路裸片直接芯片附接至封装衬底；
其中，所述互连桥器件的所述第二接合焊盘层的所述接合焊盘之间的所述互连布线在连接到桥器件的所述第一和第二集成电路裸片之间提供裸片到裸片互连；
其中所述第一接合焊盘层和所述第二接合焊盘层中的所述接合焊盘之间的所述互连布线提供所述封装衬底与所述第一和第二集成电路裸片之间的封装到裸片连接，其中所述封装到裸片连接包括电源连接；
其中，所述互连桥器件以及所述第一和第二集成电路裸片连接到所述封装衬底的平面顶侧表面；
其中，直接芯片附接包括形成布置在所述封装衬底的所述平面顶侧表面与所述第一和第二集成电路裸片之间的支架连接结构，其中所述支架连接结构提供所述封装衬底与所述第一和第二集成电路裸片之间的裸片到封装连接，其中所述支架连接结构被配置以偏移安装到所述封装衬底的所述平面顶侧表面的所述互连桥器件的高度；以及
在所述封装衬底的所述平面顶侧表面与所述第一和第二集成电路裸片之间形成底部填充层，其中所述支架连接结构和所述互连桥器件被封装于所述底部填充层中。
16.如权利要求15所述的方法，其中，使用后段制程工艺逐层构造所述互连桥晶圆。
17.如权利要求15所述的方法，进一步包括：在将所述第一和第二集成电路裸片直接芯片附接至所述互连桥器件之前，在所述互连桥器件的所述第二接合焊盘层的所述接合焊盘上形成互连凸块。
18.如权利要求1所述的封装结构，其中，所述底部填充层包括电绝缘粘合剂材料。
19.如权利要求11所述的方法，其中，所述底部填充层包括电绝缘粘合剂材料。
20.如权利要求15所述的方法，其中，所述底部填充层包括电绝缘粘合剂材料。
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WO2024067275A1 (zh) * 2022-09-27 2024-04-04 江苏芯德半导体科技有限公司 一种具有高密度连接层的芯片封装方法及其芯片封装结构

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