WO2024067275A1 - 一种具有高密度连接层的芯片封装方法及其芯片封装结构 - Google Patents

一种具有高密度连接层的芯片封装方法及其芯片封装结构 Download PDF

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Publication number
WO2024067275A1
WO2024067275A1 PCT/CN2023/119916 CN2023119916W WO2024067275A1 WO 2024067275 A1 WO2024067275 A1 WO 2024067275A1 CN 2023119916 W CN2023119916 W CN 2023119916W WO 2024067275 A1 WO2024067275 A1 WO 2024067275A1
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layer
substrate
type
chip
metal wiring
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PCT/CN2023/119916
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English (en)
French (fr)
Inventor
潘明东
谢雨龙
陈文军
马国海
梅万元
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江苏芯德半导体科技有限公司
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Publication of WO2024067275A1 publication Critical patent/WO2024067275A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16153—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/16155—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H01L2224/16157—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to the technical field of semiconductor packaging, and more specifically to a chip packaging method with a high-density connection layer and a chip packaging structure thereof.
  • the packaging substrate is generally a substrate, which includes at least one dielectric layer, a circuit layer distributed on the dielectric layer, and the circuit layers between adjacent dielectric layers are electrically connected.
  • a packaging structure In order to meet the requirements of integrated and high-density packaging, a packaging structure often needs to have more circuits and pins, which requires more substrate layers to facilitate circuit layout design.
  • the present invention provides a chip packaging method with a high-density connection layer and a chip packaging structure thereof, in which a part of the circuit layer inside the substrate is replaced by a high-density connection layer, thereby reducing the number of substrate layers and thickness, reducing the difficulty of substrate layout and wiring, and improving the integration and performance of the circuit.
  • a chip packaging method with a high-density connection layer comprising the following steps:
  • S1 preparing a high-density connection layer, the high-density connection layer comprising a multi-layer metal wiring layer, and a surface of the multi-layer metal wiring layer has a conductive bump;
  • S2 preparing a substrate intermediate, the substrate intermediate including at least one dielectric layer and a circuit layer penetrating the dielectric layer, and mounting a high-density connection layer on the substrate intermediate;
  • S4 flipping the chip onto the surface of the substrate, the chip being provided with first-type bumps and second-type bumps, the first-type bumps being electrically connected to the first-type pads, and the second-type bumps being electrically connected to the second-type pads.
  • step S4 the chip packaging is continued, filler is filled between the bottom of the chip and the substrate, the surface of the chip is coated with a thermal interface layer, a heat sink is mounted on the thermal interface layer, the heat sink is connected to the surface of the substrate by an adhesive material, and solder balls are made on the circuit layer on the side of the substrate where the chip is not packaged, thereby completing the ball grid array packaging.
  • step S4 at least two chips are flipped on the surface of the substrate, the first-type bumps of two adjacent chips are located close to each other, and the first-type bumps of the two adjacent chips are both connected to the conductive bumps of the multi-layer metal wiring layer, so that the two adjacent chips are connected through a high-density connection layer.
  • the diameter of the first type of bumps is 25-65 ⁇ m
  • the center distance between adjacent first type bumps is 40-100 ⁇ m
  • the diameter of the second type of bumps is 60-150 ⁇ m
  • the center distance between adjacent second type bumps is 100-300 ⁇ m.
  • the high-density connection layer in step S1 is a double-sided high-density connection layer
  • the high-density connection layer further includes a plastic encapsulation layer 1 disposed on one side of the multi-layer metal wiring layer, and a copper column penetrating the plastic encapsulation layer 1 is disposed in the plastic encapsulation layer 1, and two ends of the copper column are respectively electrically connected to the conductive bumps on the lower surface of the multi-layer metal wiring layer and the circuit layer of the substrate intermediate;
  • the preparation of the high-density connection layer comprises the following steps:
  • S1-1A Preparing copper pillars on a substrate: preparing a substrate, sequentially adopting the processes of coating, exposure, and development, preparing a photoresist layer with patterned openings on the substrate, preparing copper pillars in the openings by electroplating or sputtering, and removing the photoresist layer;
  • S1-2A preparing a plastic encapsulation layer 1 for encapsulating a copper column: forming a plastic encapsulation layer 1 for encapsulating a copper column on a substrate, and exposing an end face of the copper column; if the plastic encapsulation layer 1 is higher than the copper column, exposing the end face of the copper column by grinding the surface of the plastic encapsulation layer 1;
  • S1-3A Preparing a multi-layer metal wiring layer on the surface of the plastic encapsulation layer: Preparing an insulating dielectric layer with a patterned opening on the surface of the plastic encapsulation layer, forming a multi-layer metal wiring layer in the opening by electroplating or sputtering, wherein the surface of the multi-layer metal wiring layer has conductive bumps, there are interconnections between adjacent metal wiring layers, and there are interconnections between the multi-layer metal wiring layer and the copper pillars; the metal wiring layer of the multi-layer metal wiring layer has 2 to 10 layers;
  • S1-4A removing the substrate: removing the substrate, grinding and thinning the first plastic packaging layer, so that the copper pillars away from the multi-layer metal wiring layer are exposed;
  • S1-5A Cut into individual pieces to obtain a double-sided high-density connection layer.
  • the high-density connection layer in step S1 further includes a second plastic encapsulation layer disposed on one side of the multi-layer metal wiring layer, wherein a silicon wafer is disposed in the second plastic encapsulation layer, and the silicon wafer is electrically connected to the conductive bumps on the surface of the multi-layer metal wiring layer;
  • the preparation of the high-density connection layer comprises the following steps:
  • S1-1B Flip-chip silicon wafer: prepare a silicon wafer that has been ground and thinned. The silicon wafer is cut from a wafer and does not contain any devices. Prepare a carrier wafer, attach a temporary bonding layer to the carrier wafer, grind and thin the silicon wafer to form a polished surface and a smooth surface, and flip-chip press the smooth surface of the silicon wafer onto the temporary bonding layer;
  • S1-2B preparing a second plastic sealing layer for wrapping the silicon wafer: plastic sealing the temporary bonding layer by injection molding to form a second plastic sealing layer for wrapping the silicon wafer, wherein the silicon wafer is wrapped inside the second plastic sealing layer;
  • S1-3B preparing a multi-layer metal wiring layer: peeling off the carrier wafer and the temporary bonding layer by debonding, first preparing an insulating dielectric layer with a patterned opening on the smooth surface of the silicon wafer, and forming the multi-layer metal wiring layer in the opening by electroplating or sputtering, wherein the surface of the multi-layer metal wiring layer has conductive bumps, and there are interconnections between adjacent metal wiring layers; the metal wiring layer of the multi-layer metal wiring layer has 2 to 10 layers;
  • S1-4B thinning the second plastic encapsulation layer: the thickness of the second plastic encapsulation layer after thinning is at least greater than the thickness of the silicon wafer;
  • the high-density connection layer in step S1 further includes a plastic encapsulation layer 3 disposed on one side of the multi-layer metal wiring layer;
  • the preparation of the high-density connection layer comprises the following steps:
  • S1-1C Preparing a third plastic sealing layer on a substrate: preparing a substrate, and preparing a third plastic sealing layer on the substrate by an injection molding or lamination process;
  • S1-2C preparing a multi-layer metal wiring layer: preparing an insulating dielectric layer with patterned openings on three surfaces of the plastic packaging layer, forming the multi-layer metal wiring layer in the openings by electroplating or sputtering, wherein the surface of the multi-layer metal wiring layer has conductive bumps, and there are interconnections between adjacent metal wiring layers; the metal wiring layers of the multi-layer metal wiring layer have 2 to 10 layers;
  • a chip packaging structure with a high-density connection layer comprising a substrate, a high-density connection layer embedded in the substrate, and a chip flipped on the surface of the substrate, the substrate having a surface dielectric layer, the high-density connection layer is located in the surface dielectric layer, the substrate below the surface dielectric layer comprises at least one dielectric layer, and a through-hole
  • the circuit layer of the dielectric layer, the high-density connection layer includes a multi-layer metal wiring layer, a plastic packaging layer located on one side of the multi-layer metal wiring layer, and a copper column penetrating the plastic packaging layer.
  • the upper and lower surfaces of the multi-layer metal wiring layer are provided with conductive bumps, and the two ends of the copper column are respectively electrically connected to the conductive bumps on one side of the multi-layer metal wiring layer and the circuit layer of the substrate.
  • the chip is provided with a first type of bump and a second type of bump.
  • the first type of bump is connected to the conductive bump of the multi-layer metal wiring layer through a first type of pad
  • the second type of bump is connected to the circuit layer of the substrate through a second type of pad.
  • the second type of pad is arranged through the surface dielectric layer.
  • At least two chips are flipped on the surface of the substrate, the first-type bumps of two adjacent chips are located close to each other, and the first-type bumps of the two adjacent chips are both connected to the conductive bumps of the multi-layer metal wiring layer, so that the two adjacent chips are connected through a high-density connection layer.
  • a chip packaging structure with a high-density connection layer includes a substrate, a high-density connection layer embedded in the substrate, and a chip flipped on the surface of the substrate.
  • the substrate has a surface dielectric layer, the high-density connection layer is located in the surface dielectric layer, the surface dielectric layer is provided with a second type of pad, the substrate below the surface dielectric layer includes at least one dielectric layer and a circuit layer penetrating the dielectric layer, the high-density connection layer includes a multi-layer metal wiring layer, and a second plastic sealing layer located on one side of the multi-layer metal wiring layer, a silicon wafer is provided in the second plastic sealing layer, conductive bumps are provided on the upper and lower sides of the multi-layer metal wiring layer, the silicon wafer is connected to the conductive bumps on one side of the multi-layer metal wiring layer, the chip is provided with a first type of bump and a second type of bump, the conductive bump on
  • a chip packaging structure with a high-density connection layer comprising a substrate, a high-density connection layer embedded in the substrate, and a chip flipped on the surface of the substrate, the substrate having a surface dielectric layer, the high-density connection layer being located in the surface dielectric layer, the surface dielectric layer being provided with a second type of pad, the substrate below the surface dielectric layer comprising at least one dielectric layer and a circuit layer penetrating the dielectric layer, the high-density connection layer comprising a multi-layer metal wiring layer, and a plastic sealing layer three located on one side of the multi-layer metal wiring layer, the multi-layer metal wiring layer being provided with a conductive bump, the chip being provided with a first type of bump and a second type of bump, the conductive bump being electrically connected to the first type of bump through the first type of pad, the second type of bump being electrically connected to the second type of pad, a filler being filled between the
  • the present invention provides a chip packaging method with a high-density connection layer and a chip packaging structure thereof, firstly prepares a high-density connection layer of a required structure, then mounts the high-density connection layer on a substrate intermediate, continues to complete the production of the substrate, embeds the high-density connection layer into the substrate, and then flips the chip onto the substrate to complete the packaging.
  • the chip packaging method interconnects the chip and the substrate using a wafer-level process, and the high-density connection layer with multiple metal wiring layers embedded in the substrate can replace a part of the circuit layer inside the substrate, thereby reducing the number of substrate layers; the high-density connection layer can be pre-fabricated using a micron-level photolithography machine, and the process route It is relatively simple and easy to implement, and reduces costs.
  • the specific structure of the high-density connection layer can be diversified, which increases the flexibility of the design and reduces the difficulty of substrate layout and wiring.
  • the substrate is combined with the high-density connection layer to reduce the thickness of the substrate, so that each device can be arranged in a more compact manner, thereby improving the integration and performance of the circuit.
  • the internal high-density connection layer of the chip packaging structure prepared by the present invention can be a single-sided high-density connection layer or a double-sided high-density connection layer.
  • the double-sided high-density connection layer has more interconnections with the substrate than the single-sided high-density connection layer, and the connection efficiency of the double-sided high-density connection layer is higher, which reduces the routing difficulty of the chip packaging structure.
  • FIG1 is a schematic structural diagram of a preparation process of a high-density connection layer according to Example 1 of the present invention.
  • FIG2 is a schematic diagram of the structure of a high-density connection layer attached to a substrate intermediate body according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of the structure of a high-density connection layer after being embedded in a substrate according to Embodiment 1 of the present invention
  • FIG4 is a diagram of a chip packaging structure according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram showing the distribution of first-type bumps and second-type bumps on a chip according to Embodiment 1 of the present invention
  • Example 6 is a schematic structural diagram of the preparation process of a high-density connection layer according to Example 2 of the present invention.
  • Example 7 is a chip packaging structure diagram of Example 2 of the present invention.
  • FIG8 is a schematic structural diagram of a preparation process of a high-density connection layer according to Example 3 of the present invention.
  • FIG9 is a chip packaging structure diagram of Embodiment 3 of the present invention.
  • FIG. 10 is a diagram of a chip packaging structure according to a fourth embodiment of the present invention.
  • a chip packaging structure is obtained by a chip packaging method with a high-density connection layer provided by an embodiment of the present invention, and the chip packaging structure includes a substrate 1, a high-density connection layer 2 embedded in the substrate 1, and at least two chips 3 flipped on the surface of the substrate 1.
  • Each chip 3 has a first type of bump 31 and a second type of bump 32.
  • the substrate 1 has a surface dielectric layer 103, and the high-density connection layer 2 is located in the surface dielectric layer 103.
  • the substrate below the surface dielectric layer 103 includes at least one dielectric layer 101 and a circuit layer 102 that penetrates the dielectric layer 101.
  • the high-density connection layer 2 is a double-sided high-density connection layer 2, that is, both the upper and lower surfaces can be electrically connected to other devices.
  • the high-density connection layer 2 includes a multi-layer metal wiring layer 21, and a plastic sealing layer 22 located on one side of the multi-layer metal wiring layer 21, and a copper column 23 is penetrated in the plastic sealing layer 22, and the upper and lower surfaces of the multi-layer metal wiring layer 21 are provided with conductive bumps 211, and the copper column 23 is electrically connected to the conductive bump 211 on one side of the multi-layer metal wiring layer 21.
  • the high-density connection layer 2 is embedded in the substrate 1, the copper pillar 23 is electrically connected to the circuit layer 102 of the substrate 1, the conductive bump 211 on the other side of the multi-layer metal wiring layer 21 is electrically connected to the first-type bump 31 of the chip 3 through the first-type pad 104, and the second-type bump 32 of the chip 3 is electrically connected to the second-type pad 105 of the substrate 1, and the second-type pad 105 is set through the surface dielectric layer 103.
  • the first-type bumps 31 of two adjacent chips 3 flipped on the surface of the substrate 1 are close to each other.
  • the first-type bump 31 of the chip 3 on the left is located on the right side of the lower surface of the chip 3, and the first-type bump 31 of the chip 3 on the right is located on the left side of the lower surface of the chip 3. In this way, it is conducive to connecting two adjacent chips 3 through the same high-density connection layer 2.
  • the chip packaging method adopted by the chip packaging structure comprises the following steps:
  • S1-1A Preparing copper pillars 23 on substrate 24: As shown in S1-1A, prepare a wafer-level substrate 24, sequentially adopt the coating, exposure, and development processes to prepare a photoresist layer with patterned openings on the substrate 24, and use electroplating or sputtering processes to prepare copper pillars 23 in the openings, and remove wherein the material of the substrate 24 is one of silicon, ceramics, and glass, and has a supporting function; the prepared copper column 23 has a height of 100 to 200 ⁇ m, and the copper column 23 is used as a conductive structure and subsequently connected to the circuit layer inside the substrate 1.
  • step S1-2A preparing a plastic encapsulation layer 22 wrapping the copper pillar 23: as shown in 1-2A, the substrate 24 formed in step S1-1A is encapsulated by injection molding to form a plastic encapsulation layer 22 wrapping the copper pillar 23, or an ABF lamination method can be used to form a plastic encapsulation layer 22 wrapping the copper pillar 23 on the substrate 24 and expose the end face of the copper pillar 23; if after plastic encapsulation, the plastic encapsulation layer 22 is higher than the copper pillar 23, the surface of the plastic encapsulation layer 22 is ground by a grinding process to expose the end face of the copper pillar 23.
  • S1-3A Preparing a multi-layer metal wiring layer 21 on the surface of the plastic packaging layer 22: As shown in 1-3A, an insulating dielectric layer 212 with a patterned opening is prepared on the surface of the plastic packaging layer 22, and the material of the insulating dielectric layer 212 is selected from one of PI, PBO, and BCB. A multi-layer metal wiring layer 21 is formed in the opening by electroplating or sputtering process, and there is interconnection between adjacent metal wiring layers.
  • the upper and lower surfaces of the multi-layer metal wiring layer 21 have conductive bumps 211, and the multi-layer metal wiring layer 21 is interconnected with the copper pillar 23 through the conductive bumps 211 on one side; the conductive bumps 211 on the other side of the multi-layer metal wiring layer 21 are used for subsequent connection with the pads or circuit layers of the substrate 1.
  • the metal wiring layer of the multi-layer metal wiring layer 21 is 2 to 10 layers, and the metal wiring layer of the multi-layer metal wiring layer 21 can be made of metal materials such as copper and aluminum as conductive materials.
  • S1-4A Removing the substrate 24: As shown in S1-4A, the substrate 24 is removed, and a portion of the plastic encapsulation layer 22 is ground off to thin the plastic encapsulation layer 22, so that the copper pillar 23 on the side away from the multi-layer metal wiring layer 21 is exposed.
  • step S1-5A The structure formed in step S1-4A is cut into individual pieces to obtain a double-sided high-density connection layer 2 (as shown in 1-5A).
  • the double-sided high-density connection layer 2 exposes the conductive bumps 211 on one side and the copper pillars 23 on the other side, which facilitates subsequent interconnection with the substrate 1 or the chip 3.
  • Step S2 Prepare a substrate intermediate 11, which includes at least one dielectric layer 101 and a circuit layer 102 penetrating the dielectric layer 101. As shown in FIG. 2 , mount the high-density connection layer 2 obtained in step S1 on the substrate intermediate 11 so that the copper pillar 23 is connected to the circuit layer 102 of the substrate intermediate 11.
  • the substrate 1 is further manufactured, a surface dielectric layer 103 is prepared on the substrate intermediate 11, the high-density connection layer 2 is embedded in the surface dielectric layer 103 of the substrate 1, and a first type of pad 104 and a second type of pad 105 are prepared on the surface dielectric layer 103.
  • the bottom of the first type of pad 104 is electrically connected to the conductive bump 211 of the multi-layer metal wiring layer 21, the top of the first type of pad 104 is exposed to the surface dielectric layer 103, the second type of pad 105 penetrates the surface dielectric layer 103, and the bottom of the second type of pad 105 is electrically connected to the circuit of the substrate intermediate 11.
  • Layer 102 is electrically connected.
  • each chip 3 is provided with two types of bumps, namely, first-type bumps 31 and second-type bumps 32.
  • the first-type bumps 31 of the two chips 3 are connected to the conductive bumps 211 of the multilayer metal wiring layer 21 through the first-type pads 104, so that the two adjacent chips 3 are connected through the high-density connection layer 2, and the second-type bumps 32 of the chip 3 are electrically connected to the second-type pads 105.
  • the diameter of the first-type bump 31 is 25 to 65 ⁇ m, and the spacing between the centers of two adjacent first-type bumps 31 is 40 to 100 ⁇ m.
  • the diameter of the second-type bump 32 is 60 to 150 ⁇ m, and the spacing between the centers of two adjacent second-type bumps 32 is 100 to 300 ⁇ m.
  • the high-density connection layer 2 provided in this embodiment is a double-sided high-density connection layer 2.
  • the double-sided high-density connection layer 2 has more interconnections with the substrate 1, and the connection efficiency of the double-sided high-density connection layer 2 is higher, which reduces the routing difficulty of the chip packaging structure.
  • a chip packaging structure is obtained by a chip packaging method with a high-density connection layer provided by an embodiment of the present invention.
  • the chip packaging structure includes a substrate 1, a high-density connection layer 2 embedded in the substrate 1, and a chip 3 flipped on the surface of the substrate 1, and BGA packaging (Ball Grid Array Package) is performed.
  • the chip 3 has a first type of bump 31 and a second type of bump 32.
  • the substrate 1 has a surface dielectric layer 103, the high-density connection layer 2 is located in the surface dielectric layer 103, and the substrate below the surface dielectric layer 103 includes at least one dielectric layer 101, and a circuit layer 102 penetrating the dielectric layer 101.
  • the high-density connection layer 2 is a single-sided high-density connection layer 2, that is, a single-sided electrical connection is achieved with other devices.
  • the high-density connection layer 2 includes a multi-layer metal wiring layer 21, and a second plastic sealing layer 26 located on one side of the multi-layer metal wiring layer 21.
  • a silicon wafer 25 is arranged in the second plastic sealing layer 26.
  • the upper and lower surfaces of the multi-layer metal wiring layer 21 are both provided with conductive bumps 211.
  • the silicon wafer 25 is connected to the conductive bumps 211 on one side of the multi-layer metal wiring layer 21.
  • the second plastic sealing layer 26 of the high-density connection layer 2 is fixed to the substrate intermediate 11 through the adhesive layer 20, so that the high-density connection layer 2 is embedded in the substrate 1.
  • the conductive bumps 211 on the other side of the multi-layer metal wiring layer 21 are electrically connected to the first-type bumps 31 of the chip 3 through the first-type pads 104.
  • the second-type bumps 32 of the chip 3 are electrically connected to the second-type pads 105 of the substrate 1.
  • the second-type pads 105 are arranged through the surface dielectric layer 103.
  • Specific BGA packaging filler 41 is filled between the bottom of chip 3 and substrate 1, and passive components 42 can be mounted as needed.
  • the surface of chip 3 is coated with thermal interface layer 43, and heat sink 44 is mounted on the thermal interface layer 43. Heat sink 44 is connected to the surface of substrate 1 through adhesive material 45.
  • Solder balls 46 are formed on the circuit layer 102 on the side of the substrate 1 where the chip 3 is not packaged.
  • the chip packaging method adopted by the chip packaging structure comprises the following steps:
  • S1-1B Flip-chip silicon wafer 25: Prepare a silicon wafer 25 after grinding and thinning as in 1-1B.
  • the silicon wafer 25 is cut from a wafer and does not contain any devices, but only serves as a support.
  • the smooth surface of the silicon wafer 25 is flip-chip pressed onto the temporary bonding layer 28.
  • the prepared silicon wafer 25 after grinding and thinning has a thickness of 50 to 100 ⁇ m, and the thickness of the entire high-density connection layer 2 is 80 to 200 ⁇ m.
  • S1-2B Prepare the second plastic sealing layer 26 for wrapping the silicon wafer 25: Use injection molding to seal the carrier wafer 27 with the temporary bonding layer 28 formed in step S1-1B to form the second plastic sealing layer 26 for wrapping the silicon wafer 25.
  • the silicon wafer 25 is wrapped inside the second plastic sealing layer 26, as shown in 1-2B.
  • S1-3B Preparation of multi-layer metal wiring layer 21: As shown in 1-3B, the carrier wafer 27 and the temporary bonding layer 28 are debonded and peeled off, and an insulating dielectric layer 212 with a patterned opening is first prepared on the smooth surface of the silicon wafer 25.
  • the material of the insulating dielectric layer 212 is selected from one of PI, PBO, and BCB.
  • a multi-layer metal wiring layer 21 is formed in the opening by electroplating or sputtering process. There are interconnections between adjacent metal wiring layers.
  • the multi-layer metal wiring layer 21 has conductive bumps 211 on the upper and lower surfaces.
  • the metal wiring layer of the multi-layer metal wiring layer 21 is 2 to 10 layers, and the metal wiring layer of the multi-layer metal wiring layer 21 can be made of metal materials such as copper and aluminum as conductive materials.
  • S1-4B Thinning the second plastic encapsulation layer 26: As shown in 1-4B, in order to reduce the overall thickness, the second plastic encapsulation layer 26 is thinned by grinding. Since the second plastic encapsulation layer 26 can increase the mechanical strength, the second plastic encapsulation layer 26 still needs to retain a certain thickness. It is required that the thickness of the second plastic encapsulation layer 26 after thinning is at least greater than the thickness of the silicon wafer 25.
  • step S1-5B The structure formed in step S1-4B is cut into individual pieces to obtain a single-sided high-density connection layer 2, as shown in 1-5B.
  • the high-density connection layer 2 uses a silicon wafer 25 and a second plastic encapsulation layer 26 to support a multi-layer metal wiring layer 21, making it convenient to directly mount the high-density connection layer 2 on the substrate 1 later.
  • the substrate intermediate 11 includes at least one dielectric layer 101 and a circuit layer 102 penetrating the dielectric layer 101, and mount the prepared high-density connection layer 2 on the substrate intermediate 11. Specifically, fix the second plastic encapsulation layer 26 on the substrate intermediate 11 through the adhesive layer 20.
  • Chip 3 is flipped onto the surface of substrate 1.
  • Chip 3 has first-type bumps 31 and second-type bumps 32.
  • the first-type bumps 31 of chip 3 are connected to the conductive bumps 211 of the multi-layer metal wiring layer 21 through the first-type pads 104, and the second-type bumps 32 of chip 3 are electrically connected to the second-type pads 105.
  • BGA packaging is continued. Specifically, filler 41 is filled between the bottom of chip 3 and substrate 1, and passive components 42 can be mounted as needed.
  • the surface of chip 3 is coated with a thermal interface layer 43, and a heat sink 44 is mounted on the thermal interface layer 43. Heat sink 44 is connected to the surface of substrate 1 through adhesive material 45.
  • Solder balls 46 are made on the circuit layer 102 on the side of substrate 1 where chip 3 is not packaged, and ball grid array packaging is completed.
  • a chip packaging structure is obtained by a chip packaging method with a high-density connection layer provided by an embodiment of the present invention.
  • the chip packaging structure includes a substrate 1, a high-density connection layer 2 embedded in the substrate 1, and a chip 3 flipped on the surface of the substrate 1, and BGA packaging (Ball Grid Array Package) is performed.
  • the chip 3 has a first type of bump 31 and a second type of bump 32.
  • the substrate 1 has a surface dielectric layer 103, and the high-density connection layer 2 is located in the surface dielectric layer 103.
  • the substrate below the surface dielectric layer 103 includes at least one dielectric layer 101 and a circuit layer 102 that penetrates the dielectric layer 101.
  • the high-density connection layer 2 is a single-sided high-density connection layer 2, that is, a single side is electrically connected to other devices.
  • the high-density connection layer 2 includes a multi-layer metal wiring layer 21 and a plastic sealing layer 29 located on one side of the multi-layer metal wiring layer 21.
  • the surface of the multi-layer metal wiring layer 21 is provided with a conductive bump 211.
  • the plastic encapsulation layer 29 of the high-density connection layer 2 is fixed to the substrate intermediate body 11 through the adhesive layer 20, so that the high-density connection layer 2 is embedded in the substrate 1, and the conductive bumps 211 of the multi-layer metal wiring layer 21 are electrically connected to the first-type bumps 31 of the chip 3 through the first-type pads 104, and the second-type bumps 32 of the chip 3 are electrically connected to the second-type pads 105 of the substrate 1, and the second-type pads 105 are arranged through the surface dielectric layer 103.
  • the surface of the chip 3 is coated with a thermal interface layer 43, and a heat sink 44 is mounted on the thermal interface layer 43.
  • the heat sink 44 is connected to the surface of the substrate 1 through an adhesive material 45, and solder balls 46 are made on the circuit layer 102 on the side of the substrate 1 where the chip 3 is not packaged.
  • the chip packaging method adopted by the chip packaging structure comprises the following steps:
  • S1-1C Preparing a third plastic encapsulation layer 29 on a substrate 24: As shown in 1-1C, prepare a substrate 24.
  • the material of the substrate 24 is one of silicon, ceramics, and glass, and has a supporting function.
  • a third plastic encapsulation layer 29 is made on the substrate 24.
  • the third plastic encapsulation layer 29 can use epoxy resin molding compound as the material and is completed by an injection molding process.
  • the third plastic encapsulation layer 29 can also use ABF as the material and is completed by lamination.
  • S1-2C Prepare a multi-layer metal wiring layer 21: As shown in 1-2C, prepare an insulating dielectric layer 212 with a patterned opening on the surface of the plastic encapsulation layer 29.
  • the material of the insulating dielectric layer 212 is selected from PI, PBO, and BCB.
  • a multi-layer metal wiring layer 21 is formed in the opening by electroplating or sputtering.
  • the surface of the multi-layer metal wiring layer 21 has conductive bumps 211, and there are interconnections between adjacent metal wiring layers.
  • the multi-layer metal wiring layer 21 has 2 to 10 metal wiring layers, and the metal wiring layers of the multi-layer metal wiring layer 21 can be made of metal materials such as copper and aluminum as conductive materials.
  • S1-3C Thinning the third plastic encapsulation layer 29: As shown in 1-3C, after removing the substrate 24, in order to reduce the overall thickness, the third plastic encapsulation layer 29 is thinned by grinding, but since the subsequent support is required by the third plastic encapsulation layer 29, the third plastic encapsulation layer 29 still needs to retain a certain thickness.
  • the thickness of the multi-layer metal wiring layer 21 is 30 to 70 ⁇ m, and the thickness of the third plastic encapsulation layer 29 is controlled so as to control the overall thickness of the high-density connection layer 2 to 50 to 200 ⁇ m.
  • step S1-4C The structure formed in step S1-3C is cut into individual pieces to obtain a single-sided high-density connection layer 2, as shown in 1-4C.
  • the substrate intermediate 11 includes at least one dielectric layer 101 and a circuit layer 102 penetrating the dielectric layer 101, and mount the prepared high-density connection layer 2 on the substrate intermediate 11. Specifically, fix the plastic encapsulation layer 29 on the substrate intermediate 11 through the adhesive layer 20.
  • the chip 3 has a first type of bump 31 and a second type of bump 32.
  • the first type of bump 31 of the chip 3 is connected to the conductive bump 211 of the multi-layer metal wiring layer 21 through the first type of pad 104.
  • the second type of bump 32 of the chip 3 is electrically connected to the second type of pad 105.
  • filler 41 is filled between the bottom of chip 3 and substrate 1, passive components 42 can be mounted as needed, a thermal interface layer 43 is coated on the surface of chip 3, a heat sink 44 is mounted on the thermal interface layer 43, the heat sink 44 is connected to the surface of substrate 1 through adhesive material 45, solder balls 46 are made on the circuit layer 102 on the side of substrate 1 where chip 3 is not packaged, and ball grid array packaging is completed.
  • the main difference between the present embodiment 4 and the embodiment 1 is that the chip 3 flip-mounted on the surface of the substrate 1 is a single chip.
  • a chip packaging structure is obtained by the chip packaging method with a high-density connection layer provided in an embodiment of the present invention, and the chip packaging structure includes a substrate 1, a high-density connection layer 2 embedded in the substrate 1, and a chip 3 flipped on the surface of the substrate 1.
  • the high-density connection layer 2 is a double-sided high-density connection layer 2, and the manufacturing process is the same as that of the high-density connection layer 2 in Example 1.
  • the chip 3 has a first type of bumps 31 and a second type of bumps 32.
  • the high-density connection layer 2 is embedded in the substrate 1, the copper pillar 23 is electrically connected to the circuit layer 102 of the substrate 1, the conductive bumps 211 on the other side of the multi-layer metal wiring layer 21 are electrically connected to the first type of bumps 31 of the chip 3 through the first type of pads 104, and the second type of bumps 32 of the chip 3 are electrically connected to the second type of pads 105 of the substrate 1, and the second type of pads 105 are arranged through the surface dielectric layer 103.
  • the bumps of the chip 3 can also all be the first type of bumps 31.
  • the BGA package can be completed. Specifically, filler 41 is filled between the bottom of the chip 3 and the substrate 1, and passive components 42 can be mounted as needed. A thermal interface layer 43 is coated on the surface of the chip 3, and a heat sink 44 is mounted on the thermal interface layer 43. The heat sink 44 is connected to the surface of the substrate 1 through an adhesive material 45. Solder balls 46 are made on the circuit layer 102 on the side of the substrate 1 where the chip 3 is not packaged, and the ball grid array package is completed.
  • the present invention provides a chip packaging method with a high-density connection layer and a chip packaging structure thereof.
  • a high-density connection layer 2 of a desired structure is first prepared, and then the high-density connection layer 2 is mounted on a substrate intermediate 11.
  • the production of the substrate 1 is continued to complete so that the high-density connection layer 2 is embedded in the substrate 1.
  • the chip 3 is flipped on the substrate 1 to complete the packaging.
  • the chip packaging method uses a wafer-level process to interconnect the chip 3 with the substrate 1.
  • the high-density connection layer 2 with multiple metal wiring layers 21 is embedded in the substrate 1 to replace a portion of the circuit layer 102 inside the substrate 1, thereby reducing the number of layers of the substrate 1.
  • the high-density connection layer 2 can be pre-fabricated using a micron-level photolithography machine, and the process route is relatively simple and easy, which reduces costs.
  • the specific structure of the high-density connection layer 2 can be diversified, which increases the flexibility of the design and reduces the difficulty of layout and wiring of the substrate 1.
  • the substrate 1 combined with the high-density connection layer 2 can reduce the thickness of the substrate 1, so that Each device can be arranged in a more compact manner, thereby improving the integration and performance of the circuit.
  • the high-density connection layer 2 inside the prepared chip packaging structure can be a single-sided high-density connection layer 2 or a double-sided high-density connection layer 2.
  • the double-sided high-density connection layer 2 has more interconnections with the substrate 1 than the single-sided high-density connection layer 2, and the double-sided high-density connection layer 2 has a higher connection efficiency, which reduces the routing difficulty of the chip packaging structure.

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Abstract

本发明公开了一种具有高密度连接层的芯片封装方法及其芯片封装结构，该方法包括步骤：S1：制备具有多层金属布线层的高密度连接层；S2：预备基板中间体，将高密度连接层贴装于基板中间体上；S3：继续完成基板的制作，高密度连接层嵌于基板内，在基本的表层介电层上制备第一类焊盘、第二类焊盘，使第一类焊盘与多层金属布线层连接，第二类焊盘与基板中间体的线路层连接；S4：将芯片倒装于基板表面，芯片设有第一类凸块、第二类凸块，第一类凸块与第一类焊盘连接，第二类凸块与第二类焊盘连接。制备的芯片封装结构以单面或双面的高密度连接层取代一部分基板内部的线路层，从而减少基板层数、厚度，降低排版布线的难度，提高集成度和性能。

Description

一种具有高密度连接层的芯片封装方法及其芯片封装结构 技术领域
本发明涉及半导体封装技术领域，更具体涉及一种具有高密度连接层的芯片封装方法及其芯片封装结构。
背景技术
现有技术中，倒装芯片封装是将工作面上制有凸点电极的芯片朝下，与封装衬底直接键合，通过芯片上呈阵列排布的凸点来实现芯片与封装衬底的互连。封装衬底一般选用基板，基板包括至少一层介电层、在介电层上分布的线路层，相邻介电层之间的线路层之间电连接。
为了满足集成化、高密度化的封装要求，一个封装结构往往需要设置更多的线路以及引脚数目，这就需要设置更多的基板层数，以便于布局设计电路。
然而，基板的层数越多，排版布线难度增加，制作工艺也越复杂，封装结构的集成度大大降低，无法满足集成化的需求，另外，也不可避免的导致成本增加。
因此，亟需一种能够减少基板层数、提高电路集成度和性能的芯片封装方法。
发明内容
为了解决上述问题，本发明提供了一种具有高密度连接层的芯片封装方法及其芯片封装结构，以高密度连接层取代一部分基板内部的线路层，从而减少基板层数、厚度，降低基板排版布线的难度，提高电路的集成度和性能。
根据本发明的一个方面，提供了一种具有高密度连接层的芯片封装方法，所述方法包括如下步骤：
S1：制备高密度连接层，高密度连接层包括多层金属布线层，多层金属布线层的表面具有导电凸块；
S2：预备基板中间体，基板中间体包括至少一层介电层、贯穿介电层的线路层，将高密度连接层贴装于基板中间体上；
S3：继续完成基板的制作，在基板中间体上制备表层介电层，高密度连接层嵌于基板的表层介电层内，表层介电层上制备第一类焊盘、第二类焊盘，第一类焊盘的底部与多层金属布线层的导电凸块电 连接，第一类焊盘的顶部暴露于表层介电层，第二类焊盘贯穿表层介电层，且第二类焊盘的底部与基板中间体的线路层电连接；
S4：将芯片倒装于基板表面，芯片设有第一类凸块、第二类凸块，第一类凸块与第一类焊盘电连接，所述第二类凸块与第二类焊盘电连接。
在一些实施方式中，所述步骤S4完成后，继续完成芯片的封装，对芯片底部与基板之间填充填料，芯片的表面涂覆有导热界面层，导热界面层上贴装有散热片，散热片与基板表面通过粘结材料连接，基板未封装芯片的一侧的线路层上制作焊球，完成球栅阵列封装。
在一些实施方式中，所述步骤S4中，倒装于基板表面的芯片至少设有两个，两个相邻芯片的第一类凸块位置相靠近，两个相邻芯片的第一类凸块均连接于多层金属布线层的导电凸块，使相邻的两个芯片通过高密度连接层相连接。
在一些实施方式中，第一类凸块的直径尺寸为25～65μm，相邻第一类凸块的中心间距尺寸为40～100μm，第二类凸块的直径尺寸为60～150μm，相邻第二类凸块的中心间距尺寸为100～300μm。
在一些实施方式中，步骤S1中所述高密度连接层为双面高密度连接层，高密度连接层还包括设于多层金属布线层一侧的塑封层一，塑封层一内设有贯穿塑封层一的铜柱，铜柱的两端分别与多层金属布线层下表面的导电凸块、基板中间体的线路层电连接；
所述高密度连接层的制备包括如下步骤：
S1-1A：在衬底上制备铜柱：预备衬底，依次采用涂胶、曝光、显影工艺，在衬底上制备图案化开口的光刻胶层，在开口内采用电镀或者溅射工艺制备铜柱，去除光刻胶层；
S1-2A：制备包裹铜柱的塑封层一：在衬底上形成包裹铜柱的塑封层一，并露出铜柱的端面；若塑封层一高于铜柱，通过研磨塑封层一表面，使铜柱的端面露出；
S1-3A：在塑封层一表面制备多层金属布线层：在塑封层一表面制备图案化开口的绝缘介质层，在开口内采用电镀或者溅射工艺形成多层金属布线层，多层金属布线层的表面具有导电凸块，相邻金属布线层之间存在互连，多层金属布线层与铜柱之间存在互连；所述多层金属布线层的金属布线层为2～10层；
S1-4A：去除衬底：去除衬底，研磨减薄塑封层一，使远离多层金属布线层一侧的铜柱露出；
S1-5A：切割成单颗，获得双面高密度连接层。
在一些实施方式中，步骤S1中所述高密度连接层还包括设于多层金属布线层一侧的塑封层二，塑封层二内设有硅片，硅片与多层金属布线层表面的导电凸块电连接；
所述高密度连接层的制备包括如下步骤：
S1-1B：倒装硅片：预备经过研磨减薄处理后的硅片，硅片由晶圆切割而成、且硅片中不包含器件，预备载体晶圆，在载体晶圆上贴合临时键合层，硅片研磨减薄后形成磨面和光面，将硅片的光面倒装压合于临时键合层上；
S1-2B：制备包裹硅片的塑封层二：采用注塑方式对临时键合层进行塑封，形成包裹硅片的塑封层二，硅片被包裹于塑封层二内部；
S1-3B：制备多层金属布线层：通过解键合剥离载体晶圆和临时键合层，在硅片的光面先制备图案化开口的绝缘介质层，在开口内采用电镀或者溅射工艺形成所述多层金属布线层，多层金属布线层的表面具有导电凸块，相邻金属布线层之间存在互连；所述多层金属布线层的金属布线层为2～10层；
S1-4B：减薄塑封层二：减薄后的塑封层二的厚度至少大于硅片的厚度；
S1-5B：切割成单颗，获得高密度连接层。
在一些实施方式中，步骤S1中所述高密度连接层还包括设于多层金属布线层一侧的塑封层三；
所述高密度连接层的制备包括如下步骤：
S1-1C：在衬底上制备塑封层三：预备衬底，采用注塑或层压工艺在衬底上制备塑封层三；
S1-2C：制备多层金属布线层：在塑封层三表面制备图案化开口的绝缘介质层，在开口内采用电镀或者溅射工艺形成所述多层金属布线层，多层金属布线层的表面具有导电凸块，相邻金属布线层之间存在互连；所述多层金属布线层的金属布线层为2～10层；
S1-3C：减薄塑封层三：去除衬底后，减薄塑封层三；
S1-4C：切割成单颗，获得高密度连接层。
根据本发明的另一个方面，提供了一种具有高密度连接层的芯片封装结构，所述芯片封装结构包括基板、嵌于基板内的高密度连接层、倒装于基板表面的芯片，基板具有表层介电层，高密度连接层位于表层介电层内，表层介电层下方的基板包括至少一层介电层、以及贯穿 介电层的线路层，高密度连接层包括多层金属布线层、位于多层金属布线层一侧的塑封层、以及贯穿塑封层的铜柱，多层金属布线层的上下面均设有导电凸块，铜柱的两端分别与多层金属布线层一侧的导电凸块、基板的线路层电连接，芯片设有第一类凸块、第二类凸块，第一类凸块通过第一类焊盘与多层金属布线层的导电凸块相连接，第二类凸块通过第二类焊盘与基板的线路层相连接，第二类焊盘贯穿设置于表层介电层。
在一些实施方式中，倒装于基板表面的芯片至少设有两个，两个相邻芯片的第一类凸块位置相靠近，两个相邻芯片的第一类凸块均连接于多层金属布线层的导电凸块，使相邻的两个芯片通过高密度连接层相连接。
根据本发明的另一个方面，提供了一种具有高密度连接层的芯片封装结构，所述芯片封装结构包括基板、嵌于基板内的高密度连接层、倒装于基板表面的芯片，基板具有表层介电层，高密度连接层位于表层介电层内，表层介电层设有第二类焊盘，表层介电层下方的基板包括至少一层介电层、以及贯穿介电层的线路层，高密度连接层包括多层金属布线层、以及位于多层金属布线层一侧的塑封层二，塑封层二内设有硅片，多层金属布线层的上下面均设有导电凸块，硅片与多层金属布线层一侧的导电凸块相连接，芯片设有第一类凸块、第二类凸块，多层金属布线层另一侧的导电凸块通过第一类焊盘与第一类凸块电连接，第二类凸块与第二类焊盘电连接，芯片底部与基板之间填充有填料，芯片的表面涂覆有导热界面，导热界面层上贴装有散热片，散热片与基板表面通过粘结材料连接，基板未封装芯片的一侧的线路层上制作焊球。
根据本发明的另一个方面，提供了一种具有高密度连接层的芯片封装结构，所述芯片封装结构包括基板、嵌于基板内的高密度连接层、倒装于基板表面的芯片，基板具有表层介电层，高密度连接层位于表层介电层内，表层介电层设有第二类焊盘，表层介电层下方的基板包括至少一层介电层、以及贯穿介电层的线路层，高密度连接层包括多层金属布线层、以及位于多层金属布线层一侧的塑封层三，多层金属布线层设有导电凸块，芯片设有第一类凸块、第二类凸块，导电凸块通过第一类焊盘与第一类凸块电连接，第二类凸块与第二类焊盘电连接，芯片底部与基板之间填充有填料，芯片的表面涂覆有导热界面，导热界面层上贴装有散热片，散热片与基板表面通过粘结材料连接， 基板未封装芯片的一侧的线路层上制作焊球。
与现有技术相比，本发明的有益效果是：本发明提供了一种具有高密度连接层的芯片封装方法及其芯片封装结构，先制备所需结构的高密度连接层，再将高密度连接层贴装于基板中间体，继续完成基板的制作，使高密度连接层嵌入基板内，然后将芯片倒装于基板完成封装，该芯片封装方法利用晶圆级工艺，将芯片与基板互连，具有多层金属布线层的高密度连接层嵌于基板能够取代一部分基板内部的线路层，从而可减少基板层数；高密度连接层可采用微米级的光刻机预先制作完成，工艺路线相对简单易行，降低成本；高密度连接层的具体结构可多样化，增加了设计的灵活性，减少了基板排版布线的困难程度，且基板结合高密度连接层，可以减少基板的厚度，使各器件能以更紧凑的方式排列，从而提高电路的集成度和性能；本发明制备而成的芯片封装结构内部高密度连接层，可以是单面的高密度连接层也可以是双面的高密度连接层，双面的高密度连接层相较于单面的高密度连接层与基板之间的互连增多，双面的高密度连接层的连接效率更高，降低了芯片封装结构的走线难度。
附图说明
图1是本发明实施例1的高密度连接层的制备过程结构示意图；
图2是本发明实施例1的高密度连接层贴装于基板中间体的结构示意图；
图3是本发明实施例1的高密度连接层嵌于基板后的结构示意图；
图4是本发明实施例1的芯片封装结构图；
图5是本发明实施例1的芯片上第一类凸块、第二类凸块的分布示意图；
图6是本发明实施例2的高密度连接层的制备过程结构示意图；
图7是本发明实施例2的芯片封装结构图；
图8是本发明实施例3的高密度连接层的制备过程结构示意图；
图9是本发明实施例3的芯片封装结构图；
图10是本发明实施例4的芯片封装结构图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结 合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
如图4所示，通过本发明实施例提供的具有高密度连接层的芯片封装方法制得芯片封装结构，该芯片封装结构包括基板1、嵌于基板1的高密度连接层2、以及倒装于基板1表面的至少两个芯片3。每个芯片3均具有第一类凸块31和第二类凸块32。基板1具有表层介电层103，高密度连接层2位于表层介电层103内，表层介电层103下方的基板包括至少一层介电层101、以及贯穿介电层101的线路层102。该高密度连接层2为双面高密度连接层2，即上下面均能与其他器件实现电连接，该高密度连接层2包括多层金属布线层21、以及位于多层金属布线层21一侧的塑封层一22，塑封层一22内贯穿有铜柱23，多层金属布线层21的上下面均设有导电凸块211，且铜柱23与多层金属布线层21一侧的导电凸块211电连接。高密度连接层2嵌于基板1内，铜柱23与基板1的线路层102电连接，多层金属布线层21另一侧的导电凸块211通过第一类焊盘104与芯片3的第一类凸块31电连接，芯片3的第二类凸块32与基板1的第二类焊盘105电连接，第二类焊盘105贯穿设置于表层介电层103。倒装于基板1表面的两个相邻芯片3的第一类凸块31位置相靠近，具体的，比如位于左边的芯片3的第一类凸块31位置处于该芯片3的下表面右侧，位于右边的芯片3的第一类凸块31位置处于该芯片3的下表面左侧，这样，有利于实现相邻的两个芯片3通过同一高密度连接层2相连接。
该芯片封装结构所采用的芯片封装方法，包括如下步骤：
S1：制备高密度连接层2，具体的，如图1所示：
S1-1A：在衬底24上制备铜柱23：如1-1A所示，预备晶圆级衬底24，依次采用涂胶、曝光、显影工艺，在衬底24上制备图案化开口的光刻胶层，在开口内采用电镀或者溅射工艺制备铜柱23，去除 光刻胶层；其中，衬底24的材料为硅、陶瓷、玻璃中的一种，具有支撑的作用；制备的铜柱23高度为100～200μm，该铜柱23作为导电结构，后续和基板1内部的线路层连接。
S1-2A：制备包裹铜柱23的塑封层一22：如1-2A所示，采用注塑方式对步骤S1-1A形成的衬底24进行塑封、形成包裹铜柱23的塑封层一22，也可以采用ABF压膜方式在衬底24上形成包裹铜柱23的塑封层一22，并露出铜柱23的端面；若塑封后，塑封层一22高于铜柱23，则通过研磨工艺，对塑封层一22表面进行研磨，使铜柱23的端面露出。
S1-3A：在塑封层一22表面制备多层金属布线层21：如1-3A所示，在塑封层一22表面制备图案化开口的绝缘介质层212，绝缘介质层212的材料选用PI、PBO、BCB中的一种，在开口内采用电镀或者溅射工艺形成多层金属布线层21，相邻金属布线层之间存在互连，多层金属布线层21的上下面具有导电凸块211，多层金属布线层21通过一侧的导电凸块211与铜柱23之间存在互连；多层金属布线层21另一侧的导电凸块211用于后续和基板1的焊盘或者线路层相连，多层金属布线层21的金属布线层为2～10层，多层金属布线层21的金属布线层可以以铜、铝等金属材质为导电材料。
S1-4A：去除衬底24：如1-4A所示，去除衬底24，研磨掉一部分塑封层一22，使塑封层一22减薄，使远离多层金属布线层21一侧的铜柱23露出。
S1-5A：步骤S1-4A形成的结构，切割成单颗，获得双面高密度连接层2(如1-5A所示)。双面高密度连接层2一侧暴露出导电凸块211、另一侧暴露出铜柱23，便于后续与基板1或者芯片3互连。
S2：预备基板中间体11，基板中间体11包括至少一层介电层101、贯穿介电层101的线路层102，如图2所示，将步骤S1制得的高密度连接层2贴装于基板中间体11上，使铜柱23与基板中间体11的线路层102相连。
S3：如图3所示，继续完成基板1的制作，在基板中间体11上制备表层介电层103，使高密度连接层2嵌于基板1的表层介电层103内，在表层介电层103上制备第一类焊盘104、第二类焊盘105，第一类焊盘104的底部与多层金属布线层21的导电凸块211电连接，第一类焊盘104的顶部暴露于表层介电层103，第二类焊盘105贯穿表面介电层103，且第二类焊盘105的底部与基板中间体11的线路 层102电连接。
S4：如图4所示，将至少两个芯片3倒装于基板1表面，每个芯片3均设置有两类凸块，分别为第一类凸块31和第二类凸块32，两个芯片3的第一类凸块31均通过第一类焊盘104、使芯片3与多层金属布线层21的导电凸块211相连接，使相邻的两个芯片3通过高密度连接层2相连接，芯片3的第二类凸块32与第二类焊盘105电连接。第一类凸块31的直径尺寸为25～65μm，相邻两个第一类凸块31的中心之间的间距尺寸为40～100μm。第二类凸块32的直径尺寸为60～150μm，相邻两个第二类凸块32的中心之间的间距尺寸为100～300μm。
本实施例提供的高密度连接层2为双面的高密度连接层2，双面高密度连接层2相较于单面高密度连接层2与基板1之间的互连增多，双面高密度连接层2的连接效率更高，降低了芯片封装结构的走线难度。
实施例2
如图7所示，通过本发明实施例提供的具有高密度连接层的芯片封装方法制得芯片封装结构，该芯片封装结构包括基板1、嵌于基板1的高密度连接层2、以及倒装于基板1表面的芯片3，并进行了BGA封装(Ball Grid Array Package球栅阵列封装)。芯片3均具有第一类凸块31和第二类凸块32。基板1具有表层介电层103，高密度连接层2位于表层介电层103内，表层介电层103下方的基板包括至少一层介电层101、以及贯穿介电层101的线路层102。该高密度连接层2为单面高密度连接层2，即单面与其他器件实现电连接，该高密度连接层2包括多层金属布线层21、以及位于多层金属布线层21一侧的塑封层二26，塑封层二26内设有硅片25，多层金属布线层21的上下面均设有导电凸块211，硅片25与多层金属布线层21一侧的导电凸块211相连接。高密度连接层2的塑封层二26通过粘结层20固定于基板中间体11，使高密度连接层2嵌于基板1内，多层金属布线层21另一侧的导电凸块211通过第一类焊盘104与芯片3的第一类凸块31电连接，芯片3的第二类凸块32与基板1的第二类焊盘105电连接，第二类焊盘105贯穿设置于表层介电层103。具体BGA封装：在芯片3底部与基板1之间填充有填料41，依需要还可贴装被动元件42，芯片3的表面涂覆有导热界面层43，导热界面层43上贴装有散热片44，散热片44与基板1表面通过粘结材料45连接， 基板1未封装芯片3的一侧的线路层102上制作焊球46。
该芯片封装结构所采用的芯片封装方法，包括如下步骤：
S1：制备高密度连接层2，具体的，如图6所示：
S1-1B：倒装硅片25：如1-1B预备经过研磨减薄处理后的硅片25，硅片25由晶圆切割而成、且硅片25中不包含器件，仅作为支撑作用；预备载体晶圆27，在载体晶圆27上贴合临时键合层28，硅片25研磨减薄后形成磨面和光面，将硅片25的光面倒装压合于临时键合层28上；预备的经过研磨减薄处理后的硅片25，硅片25厚度为50～100μm，整个高密度连接层2的厚度为80～200μm。
S1-2B：制备包裹硅片25的塑封层二26：采用注塑方式对步骤S1-1B形成的具有临时键合层28的载体晶圆27进行塑封，形成包裹硅片25的塑封层二26，硅片25被包裹于塑封层二26内部，如1-2B所示。
S1-3B：制备多层金属布线层21：如1-3B所示，通过解键合剥离载体晶圆27和临时键合层28，在硅片25的光面先制备图案化开口的绝缘介质层212，绝缘介质层212的材料选用PI、PBO、BCB中的一种，在开口内采用电镀或者溅射工艺形成多层金属布线层21，相邻金属布线层之间存在互连，多层金属布线层21上下面具有具有导电凸块211，多层金属布线层21的金属布线层为2～10层，多层金属布线层21的金属布线层可以以铜、铝等金属材质为导电材料。
S1-4B：减薄塑封层二26：如1-4B所示，为了减薄整体厚度，通过研磨减薄塑封层二26，由于塑封层二26能够起到增加机械强度的作用，因此塑封层二26仍然需要保留一定的厚度，要求减薄后的塑封层二26的厚度至少大于硅片25的厚度。
S1-5B：步骤S1-4B形成的结构，切割成单颗，获得单面的高密度连接层2，如1-5B所示。该高密度连接层2利用硅片25和塑封层二26共同支撑多层金属布线层21，方便后续将有高密度连接层2直接贴装在基板1中。
S2：预备基板中间体11，基板中间体11包括至少一层介电层101、贯穿介电层101的线路层102，将制得的高密度连接层2贴装于基板中间体11上，具体的，将塑封层二26通过粘结层20固定于基板中间体11上。
S3：继续完成基板1的制作，在基板中间体11上制备表层介电层103，使高密度连接层2嵌于基板1的表层介电层103内，在表层 介电层103上制备第一类焊盘104、第二类焊盘105，第一类焊盘104的底部与多层金属布线层21的导电凸块211电连接，第一类焊盘104的顶部暴露于表层介电层103，第二类焊盘105贯穿表面介电层103，且第二类焊盘105的底部与基板中间体11的线路102电连接。
S4：将芯片3倒装于基板1表面，芯片3具有第一类凸块31、第二类凸块32，芯片3的第一类凸块31通过第一类焊盘104、使芯片3与多层金属布线层21的导电凸块211相连接，芯片3的第二类凸块32与第二类焊盘105电连接。芯片3倒装于基板1后，继续完成BGA封装，具体的，对芯片3底部与基板1之间填充填料41，依需要还可贴装被动元件42，芯片3的表面涂覆有导热界面层43，导热界面层43上贴装有散热片44，散热片44与基板1表面通过粘结材料45连接，基板1未封装芯片3的一侧的线路层102上制作焊球46，完成球栅阵列封装。
实施例3
如图9所示，通过本发明实施例提供的具有高密度连接层的芯片封装方法制得芯片封装结构，该芯片封装结构包括基板1、嵌于基板1的高密度连接层2、以及倒装于基板1表面的芯片3，并进行了BGA封装(Ball Grid Array Package球栅阵列封装)。芯片3均具有第一类凸块31和第二类凸块32。基板1具有表层介电层103，高密度连接层2位于表层介电层103内，表层介电层103下方的基板包括至少一层介电层101、以及贯穿介电层101的线路层102。该高密度连接层2为单面高密度连接层2，即单面与其他器件实现电连接，该高密度连接层2包括多层金属布线层21、以及位于多层金属布线层21一侧的塑封层三29，多层金属布线层21的表面设有导电凸块211。高密度连接层2的塑封层三29通过粘结层20固定于基板中间体11，使高密度连接层2嵌于基板1内，多层金属布线层21导电凸块211通过第一类焊盘104与芯片3的第一类凸块31电连接，芯片3的第二类凸块32与基板1的第二类焊盘105电连接，第二类焊盘105贯穿设置于表层介电层103。具体BGA封装：在芯片3底部与基板1之间填充有填料41，依需要还可贴装被动元件42，芯片3的表面涂覆有导热界面层43，导热界面层43上贴装有散热片44，散热片44与基板1表面通过粘结材料45连接，基板1未封装芯片3的一侧的线路层102上制作焊球46。
该芯片封装结构所采用的芯片封装方法，包括如下步骤：
S1：制备高密度连接层2，具体的，如图8所示：
S1-1C：在衬底24上制备塑封层三29：如1-1C所示，预备衬底24，衬底24的材料为硅、陶瓷、玻璃中的一种，具有支撑的作用，在衬底24上制作塑封层三29，塑封层三29可选用环氧树脂模塑料为材料，通过注塑工艺完成，塑封层三29也可选用ABF为材料，通过层压完成。
S1-2C：制备多层金属布线层21：如1-2C所示，在塑封层三29表面制备图案化开口的绝缘介质层212，绝缘介质层212的材料选用PI、PBO、BCB中的一种，在开口内采用电镀或者溅射工艺形成多层金属布线层21，多层金属布线层21的表面具有导电凸块211，相邻金属布线层之间存在互连；多层金属布线层21的金属布线层为2～10层，多层金属布线层21的金属布线层可以以铜、铝等金属材质为导电材料。
S1-3C：减薄塑封层三29：如1-3C所示，去除衬底24后，为了减薄整体厚度，通过研磨减薄塑封层三29，但由于后续需要依靠塑封层三29进行支撑，因此塑封层三29仍需要保留一定的厚度。本实施例中，多层金属布线层21的厚度为30～70μm，控制塑封层三29的厚度，以便控制高密度连接层2的整体厚度在50～200μm。
S1-4C：步骤S1-3C形成的结构，切割成单颗，获得单面的高密度连接层2，如1-4C所示。
S2：预备基板中间体11，基板中间体11包括至少一层介电层101、贯穿介电层101的线路层102，将制得的高密度连接层2贴装于基板中间体11上，具体的，将塑封层三29通过粘结层20固定于基板中间体11上。
S3：继续完成基板1的制作，在基板中间体11上制备表层介电层103，使高密度连接层2嵌于基板1的表层介电层103内，在表层介电层103上制备第一类焊盘104、第二类焊盘105，第一类焊盘104的底部与多层金属布线层21的导电凸块211电连接，第一类焊盘104的顶部暴露于表层介电层103，第二类焊盘105贯穿表面介电层103，且第二类焊盘105的底部与基板中间体11的线路层102电连接。
S4：将芯片3倒装于基板1表面，芯片3具有第一类凸块31、第二类凸块32，芯片3的第一类凸块31通过第一类焊盘104、使芯片3与多层金属布线层21的导电凸块211相连接，芯片3的第二类凸块32与第二类焊盘105电连接。芯片3倒装于基板1后，继续完 成BGA封装，具体的，对芯片3底部与基板1之间填充填料41，依需要还可贴装被动元件42，在芯片3的表面涂覆有导热界面层43，导热界面层43上贴装有散热片44，散热片44与基板1表面通过粘结材料45连接，基板1未封装芯片3的一侧的线路层102上制作焊球46，完成球栅阵列封装。
实施例4
本实施例4与实施例1的主要区别在于，倒装于基板1表面的芯片3为单颗。
如图10所示，通过本发明实施例提供的具有高密度连接层的芯片封装方法制得芯片封装结构，该芯片封装结构包括基板1、嵌于基板1的高密度连接层2、以及倒装于基板1表面的一个芯片3。该高密度连接层2为双面高密度连接层2，与实施例1的高密度连接层2的制作工艺相同。
芯片3具有第一类凸块31和第二类凸块32。高密度连接层2嵌于基板1内，铜柱23与基板1的线路层102电连接，多层金属布线层21另一侧的导电凸块211通过第一类焊盘104与芯片3的第一类凸块31电连接，芯片3的第二类凸块32与基板1的第二类焊盘105电连接，第二类焊盘105贯穿设置于表层介电层103。在具体应用中，芯片3的凸块也可以全部为第一类凸块31。
在芯片3倒装于基板1后，可继续完成BGA封装，具体的，对芯片3底部与基板1之间填充填料41，依需要还可贴装被动元件42，在芯片3的表面涂覆有导热界面层43，导热界面层43上贴装有散热片44，散热片44与基板1表面通过粘结材料45连接，基板1未封装芯片3的一侧的线路层102上制作焊球46，完成球栅阵列封装。
本发明提供了具有高密度连接层的芯片封装方法及其芯片封装结构，先制备所需结构的高密度连接层2，再将高密度连接层2贴装于基板中间体11，继续完成基板1的制作，使高密度连接层2嵌入基板1内，然后将芯片3倒装于基板1完成封装，该芯片封装方法利用晶圆级工艺，将芯片3与基板1互连，具有多层金属布线层21的高密度连接层2嵌于基板1能够取代一部分基板1内部的线路层102，从而可减少基板1层数。高密度连接层2可采用微米级的光刻机预先制作完成，工艺路线相对简单易行，降低成本。高密度连接层2的具体结构可多样化，增加了设计的灵活性，减少了基板1排版布线的困难程度，且基板1结合高密度连接层2，可以减少基板1的厚度，使 各器件能以更紧凑的方式排列，从而提高电路的集成度和性能。制备而成的芯片封装结构内部的高密度连接层2，可以是单面的高密度连接层2也可以是双面的高密度连接层2，双面的高密度连接层2相较于单面的高密度连接层2与基板1之间的互连增多，双面的高密度连接层2的连接效率更高，降低了芯片封装结构的走线难度。
以上所述的仅是本发明的一些实施方式，应当指出，对于本领域的普通技术人员来说，在不脱离本发明的创造构思的前提下，还可以做出其它变形和改进，这些都属于本发明的保护范围。

Claims (5)

  1. 一种具有高密度连接层的芯片封装方法，其特征在于，所述方法包括如下步骤：
    S1：制备高密度连接层，所述高密度连接层包括多层金属布线层、设于多层金属布线层一侧的塑封层二，所述多层金属布线层的表面具有导电凸块，所述塑封层二内设有硅片，所述硅片与多层金属布线层表面的导电凸块电连接；
    所述高密度连接层的制备包括如下步骤：
    S1-1B：倒装硅片：预备经过研磨减薄处理后的硅片，所述硅片由晶圆切割而成、且硅片中不包含器件，预备载体晶圆，在所述载体晶圆上贴合临时键合层，所述硅片研磨减薄后形成磨面和光面，将所述硅片的光面倒装压合于临时键合层上；
    S1-2B：制备包裹硅片的塑封层二：采用注塑方式对临时键合层进行塑封，形成包裹硅片的塑封层二，所述硅片被包裹于塑封层二内部；
    S1-3B：制备多层金属布线层：通过解键合剥离载体晶圆和临时键合层，在硅片的光面先制备图案化开口的绝缘介质层，在开口内采用电镀或者溅射工艺形成所述多层金属布线层，所述多层金属布线层的表面具有导电凸块，相邻金属布线层之间存在互连；所述多层金属布线层的金属布线层为2～10层；
    S1-4B：减薄塑封层二：减薄后的塑封层二的厚度至少大于硅片的厚度；
    S1-5B：切割成单颗，获得高密度连接层；
    S2：预备基板中间体，所述基板中间体包括至少一层介电层、贯穿介电层的线路层，将高密度连接层贴装于基板中间体上；
    S3：继续完成基板的制作，在所述基板中间体上制备表层介电层，高密度连接层嵌于基板的表层介电层内，所述表层介电层上制备第一类焊盘、第二类焊盘，所述第一类焊盘的底部与多层金属布线层的导电凸块电连接，所述第一类焊盘的顶部暴露于表层介电层，所述第二类焊盘贯穿表层介电层，且所述第二类焊盘的底部与基板中间体的线路层电连接；
    S4：将芯片倒装于基板表面，所述芯片设有第一类凸块、第二类凸块，所述第一类凸块与第一类焊盘电连接，所述第二类凸块与第二 类焊盘电连接。
  2. 根据权利要求1所述的具有高密度连接层的芯片封装方法，其特征在于，所述步骤S4完成后，继续完成芯片的封装，对芯片底部与基板之间填充填料，所述芯片的表面涂覆有导热界面层，所述导热界面层上贴装有散热片，所述散热片与基板表面通过粘结材料连接，所述基板未封装芯片的一侧的线路层上制作焊球，完成球栅阵列封装。
  3. 根据权利要求1或2所述的具有高密度连接层的芯片封装方法，其特征在于，所述步骤S4中，倒装于基板表面的芯片至少设有两个，两个相邻所述芯片的第一类凸块位置相靠近，两个相邻所述芯片的第一类凸块均连接于多层金属布线层的导电凸块，使相邻的两个芯片通过高密度连接层相连接。
  4. 根据权利要求3所述的具有高密度连接层的芯片封装方法，其特征在于，所述第一类凸块的直径尺寸为25～65μm，相邻所述第一类凸块的中心间距尺寸为40～100μm，所述第二类凸块的直径尺寸为60～150μm，相邻所述第二类凸块的中心间距尺寸为100～300μm。
  5. 一种具有高密度连接层的芯片封装结构，其特征在于，采用如权利要求2所述的芯片封装方法制备而得，所述芯片封装结构包括基板、嵌于基板内的高密度连接层、倒装于基板表面的芯片，所述基板具有表层介电层，所述高密度连接层位于表层介电层内，所述表层介电层设有第二类焊盘，所述表层介电层下方的基板包括至少一层介电层、以及贯穿介电层的线路层，所述高密度连接层包括多层金属布线层、以及位于多层金属布线层一侧的塑封层二，所述塑封层二内设有硅片，所述多层金属布线层的上下面均设有导电凸块，所述硅片与多层金属布线层一侧的导电凸块相连接，所述芯片设有第一类凸块、第二类凸块，所述多层金属布线层另一侧的导电凸块通过第一类焊盘与第一类凸块电连接，所述第二类凸块与第二类焊盘电连接，所述芯片底部与基板之间填充有填料，所述芯片的表面涂覆有导热界面，所述导热界面层上贴装有散热片，所述散热片与基板表面通过粘结材料连接，所述基板未封装芯片的一侧的线路层上制作焊球。
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