CN104037098A - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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Publication number
CN104037098A
CN104037098A CN201310226454.6A CN201310226454A CN104037098A CN 104037098 A CN104037098 A CN 104037098A CN 201310226454 A CN201310226454 A CN 201310226454A CN 104037098 A CN104037098 A CN 104037098A
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Prior art keywords
layer
substrate
sacrifice layer
integrated circuit
intermediary
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CN201310226454.6A
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CN104037098B (zh
Inventor
孟宪樑
林威宏
梁裕民
何明哲
郭宏瑞
刘重希
李明机
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2224/921—Connecting a surface with connectors of different types
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Abstract

本发明提供了一种封装结构及其形成方法。通过选择性地将两个载体衬底接合在一起以及同时处理两个载体衬底来形成诸如中介层的封装结构。处理包括在载体衬底上方形成牺牲层。在牺牲层中形成开口且在开口中形成柱状物。衬底接合到牺牲层。再分配线可形成在衬底的相对侧上，并且可形成孔以提供至柱状物的电接触件。可进行分离工艺以将载体衬底分离开。集成电路管芯可附接到再分布线的一侧，然后去除牺牲层。本发明还公开了封装结构及其形成方法。

Description

封装结构及其形成方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及封装结构及其形成方法。
背景技术
现代集成电路的制造通常包括几个步骤。首先，在半导体晶圆上制造集成电路，半导体晶圆包括多个相同的半导体芯片，每个半导体芯片中包含有集成电路。然后，从晶圆上切割下半导体芯片并对其封装。封装工艺具有两个主要目的：保护易碎的半导体芯片和将内部集成电路连接到外部引脚。
在传统的封装工艺中，可利用倒装接合工艺将半导体芯片安装到封装元件上。底层填充物分布在半导体芯片和封装元件之间的间隙内，以防止在焊料凸块或焊料球中形成裂缝，其中，裂缝通常由热应力引起。封装元件可以是中介层（interposer），该中介层包括用于在相对侧之间布置电信号路线的金属连接件。可通过直接金属接合、焊料接合等将芯片接合到中介板上。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种方法，包括：
提供第一衬底；
在所述第一衬底的第一表面上方形成第一介电层；
在所述第一介电层上方形成图案化的牺牲层，所述图案化的牺牲层具有形成在其中的开口；
在所述图案化的牺牲层的开口中形成导电柱；
在所述图案化的牺牲层上方形成第二衬底；
在所述第二衬底中形成通孔；以及
将一个或多个集成电路管芯电连接到所述导电柱，所述集成电路管芯连接到所述第二衬底的与所述导电柱相对的一侧。
在可选实施例中，所述方法进一步包括：在将所述一个或多个集成电路管芯电连接到所述导电柱之前，在所述第二衬底上形成一个或多个再分配层，所述一个或多个再分配层夹置在所述第一衬底和所述第二衬底之间。
在可选实施例中，所述方法进一步包括：将所述第二衬底分割成多个衬底。
在可选实施例中，所述方法进一步包括：在形成所述图案化的牺牲层之前，在所述第一介电层上方形成导电层，其中，形成所述图案化的牺牲层包括暴露所述导电层的部分。
在可选实施例中，形成所述导电柱包括：将所述导电层用作晶种层。
在可选实施例中，利用释放膜将所述导电层附接到所述介电层。
在可选实施例中，所述方法，在电连接之后，进一步包括：去除所述第一衬底；去除所述图案化的牺牲层；以及，在去除所述图案化的牺牲层之后，在所述导电柱上形成电连接件。
在可选实施例中，所述方法，在电连接之后，进一步包括：去除所述第一衬底；在去除所述第一衬底之后，在所述导电柱上形成电连接件；以及，在形成所述电连接件之后，去除所述牺牲层。
根据本发明的另一方面，还提供了一种方法，包括：
提供接合到第二载体衬底的第一载体衬底；
在所述第一载体衬底和所述第二载体衬底上方分别形成第一牺牲层和第二牺牲层；
图案化所述第一牺牲层和所述第二牺牲层以形成开口；
用导电材料填充所述开口，从而形成柱状物；
在所述第一牺牲层和所述第二牺牲层上方分别提供第一中介层衬底和第二中介层衬底；
在所述第一中介层衬底和所述第二中介层衬底中分别形成第一通孔和第二通孔，所述第一通孔和所述第二通孔电接触所述开口中对应的导电材料；以及，
将所述第一载体衬底和所述第二载体衬底分离开。
在可选实施例中，所述的方法进一步包括：分别形成介于所述第一载体衬底与所述第一牺牲层之间的介电层以及所述第二载体衬底与所述第二牺牲层之间的介电层。
在可选实施例中，所述方法进一步包括：在所述第一中介层衬底上方形成一个或多个第一再分配层（RDL）且在所述第二中介层衬底上方形成一个或多个第二RDL。
在可选实施例中，所述方法进一步包括：在形成所述第一牺牲层之前，在所述第一载体衬底上方提供第一导电层，并且填充所述开口包括将所述第一导电层用作晶种层。
在可选实施例中，所述方法进一步包括：在分离之后，去除所述第一牺牲层。
在可选实施例中，所述方法进一步包括：在去除所述第一牺牲层之后，在所述柱状物上设置焊料。
在可选实施例中，所述方法进一步包括：在分离之前，在所述柱状物上设置焊料。
在可选实施例中，所述方法进一步包括：在所述设置之后，去除所述第一牺牲层。
在可选实施例中，所述方法进一步包括：将一个或多个集成电路管芯附接到所述第一中介层衬底；将所述第一载体衬底和所述第一中介层衬底分离开；以及，将所述第一中介层衬底分割成多个封装件。
根据本发明的又一方面，还提供了一种半导体器件，包括：中介层，具有延伸穿过所述中介层的多个通孔，所述中介层由预浸材料或玻璃形成；一个或多个再分配层，在所述中介层的第一表面上延伸；以及，导电柱，从所述中介层的第二表面延伸。
在可选实施例中，所述半导体器件进一步包括位于所述导电柱的端部上方的焊料。
在可选实施例中，所述焊料沿着所述导电柱的侧壁延伸。
在可选实施例中，所述半导体器件进一步包括一个或多个集成电路管芯，所述一个或多个集成电路管芯附接到所述一个或多个再分配层的最上面的再分配层。
在可选实施例中，所述半导体器件进一步包括模制底层填料，所述底层填料介于所述一个或多个集成电路管芯和所述一个或多个再分配层之间。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1-图9示出了根据不同实施例的制造封装件的中间阶段的截面图；
图10-图11示出了根据各种其他实施例的制造封装件的中间阶段的截面图；以及
图12示出了根据一些实施例的可用方法的流程图。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是说明，而不用于限制本发明的范围。
根据不同实施例，提供了封装结构及其形成方法。示出了形成封装结构的中间阶段。讨论了实施例的变化。通过不同的视图和示例性实施例，相同的参考数字用于表示相同的元件。
下文描述了形成可用作中介层的衬底的工艺。在使用相互接合的载体衬底和处理两个面的环境中描述该工艺。使用双面处理技术（其中，衬底是悬着的并且同时处理相对面）或按顺序（其中，处理衬底的一个面，然后翻转衬底以处理另一个面）处理被接合的载体衬底的相对面。在一些实施例中，理想情况是，期望在处理一个面时保护另一个面。然后分离载体衬底。在处理过程中，这样的实施例可实现更高的效率和降低翘曲。然而，在其他实施例中，可利用单个载体衬底和/或处理单个面。
先参见图1，示出了根据一个实施例的利用粘合层104将载体衬底102接合在一起。通常，在后续的处理步骤中，载体衬底102提供临时的机械和结构支撑，如下文详细介绍的。载体衬底102可包括例如玻璃、氧化硅、氧化铝、它们的组合和/或类似物。第一粘合层104可以是任何合适的粘合剂，如紫外线（UV）胶；当第一粘合层104曝光于UV光时，其会失去自身的粘性；并且，可通过层压、旋涂或其他合适的技术实施第一粘合层104。
导电箔106附接到已接合的载体衬底102。如下文进一步描述的，导电箔106用作形成导电通孔的晶种层。在一个实施例中，导电箔106可以是例如Ti、Cu、Ta、TiN、TaN及其组合中的一个或多个薄层。导电箔106可预先形成且按压到形成在接合的载体衬底102上方的覆盖层上。例如，在图1所示的实施例中，覆盖层108形成在接合的载体衬底102的上方。覆盖层可以是例如模制且按压到接合的载体衬底102上的预浸材料（pre-preg material）。例如，具有乙阶树脂（B-stage resin）结构的预浸材料，如，允许在树脂和硬化剂之间发生有限反应，因而覆盖在玻璃纤维上。利用热和/或压力将该材料层压在接合的载体衬底102上。在本实施例中，覆盖层108的厚度可介于大于25μm到大约80μm之间。
在其他实施例中，覆盖层108可以是味之素内置薄膜（ABF）或类似物。可利用第二粘合层110将导电箔106附接到覆盖层108，第二粘合层110可以是任何合适的粘合剂，如紫外线（UV）胶；当第二粘合层110曝光于UV光时，其会失去自身的粘合性；并且可通过分层、旋涂或其他合适的技术施加导电箔106。
在其他实施例中，通过利用CVD、PVD、层压、热压或其他类似技术沉积薄导电层（如Ti、Cu、Ta、TiN、TaN及其组合或类似物中的一个或多个薄层），从而可形成导电箔106。在该实施例中，第二粘合层110可施加到覆盖层108，且导电箔106可沉积在粘合层104上。
图2示出了根据一个实施例的在导电箔106上方形成并图案化的牺牲层212。如下文进一步的详细介绍，图案化牺牲层212以容纳在后续制造步骤中形成的导电材料，从而形成导电柱。类似地，牺牲层212的图案与用于中介板的外部电连接件的图案相对应，因此，牺牲层212的厚度可以对应于后续形成的导电柱的期望高度。在一个实施例中，牺牲层212可具有大约30μm到大约70μm之间的厚度，但是也可以使用其他厚度。可通过涂覆、层压或类似工艺由例如聚苯并恶唑（PBO）、聚酰亚胺、阻焊剂、基于聚合物的材料等形成牺牲层212。
图3示出了根据一个实施例的柱状物314的形成。柱状物314可由任何合适的导电材料形成，包括Cu、Ni、Pt、Al、它们的组合等；并且可通过任意数量的合适技术形成，包括电镀、PVD、CVD、电化学沉积（ECD）等。应注意到，在一些实施例中，例如在晶圆的整个表面上方沉积共形层（如，PVD和CVD）的那些，理想的是进行蚀刻或平坦化工艺（如，化学机械抛光（CMP））以从牺牲层212的表面去除多余的导电材料。
此后，衬底316可附接在结构的相对侧，如图3所示。根据下文所述，例如，衬底316形成中介层的衬底。在一个实施例中，衬底316可包括使用例如热、压力、粘合剂、它们的组合等层压在结构上的一个或多个预浸材料层。也可使用其他介电材料，如ABF、玻璃、氧化硅、氧化铝、它们的组合和/或类似物。
接着参见图4，根据一个实施例，形成通孔418穿过衬底316。通孔418提供了衬底316的相对侧之间的电连接。在一个实施例中，通过使用光刻技术沉积和图案化掩模（如，光刻胶掩模、硬掩模或类似物，未示出）以形成通孔418。利用蚀刻工艺以去除衬底316的暴露部分，从而露出柱状物314的部分。
然后用导电材料填充开口，形成通孔418，如图4所示。通孔418可由任何合适的导电材料（包括Cu、Ni、Pt、Al、它们的组合或类似物）形成，并且可通过任意数量的合适技术形成，这些合适的技术包括电镀、PVD、CVD、ECD、分子束外延（MBE）等。应注意到，在一些实施例中，如在晶圆的整个表面的上方沉积共形层的技术（如PVD和CVD），理想的是进行蚀刻或平坦化工艺（如CMP），以去除衬底316的表面上的多余导电材料。
图4还示出了根据一个实施例的形成第一RDL420的后钝化互连件（PPI）工艺。可形成沿衬底316的表面延伸的第一RDL420，这用作第一再分配层以布线通孔至期望位置的电连接件。在一个实施例中，第一RDL420可通过首先使用合适的形成工艺（如CVD、PVD、或溅射）形成Ti、Cu、Ta、TiN、TaN、它们的组合或类似物的晶种层（未示出）来形成。然后可形成光刻胶（未示出）以覆盖晶种层，然后可图案化光刻胶以露出期望第一RDL420所在位置处的晶种层的部分。一旦形成并且图案化光刻胶，通过诸如电镀的沉积工艺在晶种层上形成导电材料，如Cu、Ni、Pt、Al、AlCu、Au或它们的组合。然而，虽然所讨论的材料和方法适合于形成导电材料，但这些材料和工艺仅是示例性的。
一旦形成导电材料，通过诸如灰化的合适的去除工艺可去除光刻胶。此外，去除光刻胶之后，通过利用导电材料作为掩模的合适的蚀刻工艺可去除被光刻胶覆盖的晶种层的部分。
实施例中可以使用一个或多个RDL。例如，图5示出了使用由介电层（如，聚苯并恶唑（PBO）、聚酰亚胺、阻焊剂、基于聚合物的材料或类似物）分隔开的三个RDL的一个实施例。使用延伸穿过介电层的孔（如孔542）可互连相邻的RDL。
图6示出了根据一个实施例的分离工艺和管芯附接工艺。分离工艺将两个接合的载体衬底102分离开。在使用UV光敏粘合剂将接合的载体衬底102接合在一起的实施例中。分离工艺可包括曝光于UV光，从而使得第一粘合层104失去其自身的粘合性并且将载体衬底分离开。可使用清洁工艺去除粘合剂的多余残渣。
可使用管芯附接工艺将一个或多个集成电路管芯接合在一起。集成电路管芯630可以是用于特定应用的任何合适的集成电路管芯。例如，集成电路管芯630可以是存储器芯片，如DRAM、SRAM、NVRAM和/或类似物、逻辑电路或类似物。应注意，集成电路管芯630可以是相同的或不同的。例如，图6示出了集成电路管芯630包括DRAM和逻辑管芯的一个实施例。如下所述，将组合的DRAM管芯和逻辑管芯共同封装在单个封装件中。在其他实施例中，所有的集成电路管芯630是相同的，如，多个存储器管芯。也可以使用其他配置。
使用电连接件632可将集成电路管芯630接合到上RDL420上。电连接件632可包括导电凸块，如C4焊料凸块或微凸块，其可由共晶焊料、无铅焊料或类似物形成。在一些实施例中，电连接件632可包括导电柱、凸块下金属化层（UBM）和/或类似物。电连接件632可以是焊料球、金属焊盘、金属柱和/或它们的组合，也可以由金、银、镍、钨、铝和/或其合金形成。
在管芯附接工艺之后，可在集成电路管芯630和最上层RDL420之间放置可选的模制底层填料740，如图7所示。使用可接受的分配设备分配模制底层填料740，该模制底层填料740可以是液体环氧树脂、可变形凝胶、硅橡胶、它们的组合和/或类似物。
此外，可施加模塑料742或密封剂。在一个实施例中，模塑料742是聚合物，但是也可由其他材料形成，如模塑填充物（MUF）、环氧树脂或类似物。模塑料742可与集成电路管芯630的顶面和边缘相接触，也可与RDL420的顶面相接触。例如，可使用压缩模制或转移模制对模塑料742模制。模塑料742的顶面可以高于集成电路管芯630的顶面，且集成电路管芯630可完全封装在模塑料742中。或者，可进行研磨工艺以去除模塑料742位于集成电路管芯630的顶面上方的部分，从而露出集成电路管芯630的顶面。例如，当将散热器接合到集成电路管芯630时，露出集成电路管芯630的顶面是期望的。
也可进行第二切边工艺，如切割工艺。通过较大晶圆（面板/衬底）的部分示出上述工艺。同样地，采用管芯切割、激光或其他机制将集成电路管芯630分离以形成独立的封装件的第二切边工艺可以使用。图7示出了第二切边工艺或切割工艺之后的封装件。
图8示出了根据一个实施例的导电箔106和牺牲层212的去除，从而露出柱状物314。在一个实施例中，导电箔106是铜层；通过利用磷酸（H3PO4）和过氧化氢(H2O2)的化学溶液并且具有2%的氢氟（HF）酸中的湿浸（也称之为DPP）或其他的清洁工艺，可进行去除工艺。在牺牲层212由聚合物形成的实施例中，可使用湿法剥离工艺进行去除工艺。
图9示出了根据一个实施例的在柱状物314上设置焊料球944之后的结构。焊料球944通过印制、电镀和/或类似物形成在柱状物314上且可包括铜、锡、共晶焊料、无铅焊料、镍、它们的组合和/或类似物。可进行后续的回流工艺，该回流工艺中，焊料球944被溶解，从而形成图9中所示的焊料球。在本实施例中，焊料沿柱状物314的侧壁延伸。
图10和11示出了另一个实施例。在本实施例中，在如图10所示的可去除导电箔106之后，进行图1-图7中所讨论的工艺。与图8所示的去除了导电箔106和牺牲层212的实施例相比，图10示出了去除了导电箔106的实施例，但是保留了牺牲层212。在本实施例中，暴露出柱状物314的顶面。
在导电箔106为铜层的一个实施例中，利用在磷酸（H3PO4）和过氧化氢(H2O2)的化学溶液并且具有2%的氢氟（HF）酸中的湿浸（也称之为DPP）或其他清洁工艺，可进行去除工艺。
图10中还示出了焊料球1050的设置。焊料球1050通过印制、电镀和/或其他类似物形成在柱状物314上，并且可包括铜、锡、共晶焊料、无铅焊料、镍、它们的组合和/或类似物。后续可进行使焊料球1050熔化的回流工艺，从而形成图10中所示的焊料球。
之后，如图11所示，去除牺牲层212。在牺牲层212由聚合物形成的实施例中，利用例如湿法剥离工艺可进行去除工艺。
图12示出了图1-图9中所描述的工艺的流程图。该工艺开始于步骤1202，准备载体衬底。例如，在两个载体衬底选择性地接合在一起的实施例中，在接合的载体衬底上方形成诸如预浸层的覆盖层，以及在覆盖层上设置导电层或箔，如上面参考图1所讨论的。接着，在步骤1204中，在导电层的上方形成并图案化牺牲层，这样形成开口从而露出上面参考图2所讨论的导电层的部分。在步骤1206中，导电柱形成在开口和衬底（如中介层衬底）中且位于牺牲层的上方，如上面参考图3所讨论的。在步骤1208中，形成穿过中介层衬底的通孔，且在中介层衬底的上方形成一个或多个RDL，如参考图4-图5所讨论的。接着，在步骤1210中，集成电路管芯电连接到RDL，然后分离载体衬底，如参考图6所讨论的。在步骤1212中施加模制底层填料并进行分割工艺，如参考图7所讨论的。在步骤1214中，去除导电箔和牺牲层，如参考图8所讨论的。在步骤1216中，焊料可设置在露出的柱状物上，如参考图9所讨论的。
步骤1218中示出了在去除牺牲层之前，在柱状物上设置焊料的可选方法，如参考图10所讨论的。之后，在步骤1220中，去除牺牲层，如参考图11所讨论的。
如上述讨论的实施例可减小形状因子。例如，在使用中介层，如硅中介层的情况下，先处理中介层，然后由于应力被设置在印刷电路板上。这种配置类型的总形状因子相对很高。本文使用的中介层结构，如聚合物中介层，可以减少衬底工艺和成本以及形状因子。
此外，如上述披露的实施例可降低合格管芯（KGD）的损失。例如，在通常的硅中介层的情形下，直到沿着硅中介层的背面露出通孔之后，才需测试硅中介层，而通常在接合KGD之后才会出现这种露出现象。因此，如果在硅中介层上形成通孔或RDL的过程中出现错误，可能会浪费KGD。在上述的实施例中，在接合KDG之前，可电测试通孔和RDL。这样，如果在本文讨论的中介层形成过程中出现错误，则不会浪费KGD。
此外，如上述披露的实施例可降低器件泄漏。例如，硅中介层内的通孔之间的距离通常非常小，这样硅本身很容易泄漏。因此，硅中介层可利用昂贵的钝化工艺来降低通孔之间的器件泄漏。在上述的实施例中，通孔距离相对较大，而中介层材料（如预浸材料、ABF、玻璃或其他）在器件泄漏方面更具隔离性，因此，可以省略一些钝化工艺。
如上述披露的一些实施例也可降低翘曲。例如，如上述披露的结构利用厚且对称的双核结构，其能在大部分工艺（如，固化、牺牲层涂覆、电镀等）中起到平衡翘曲的作用。此外，晶圆上芯片的处理期间仍保留单核结构，以支撑结构。
根据一些实施例，提供一种方法。该方法包括在衬底的上方形成第一介电层，和在第一介电层的上方图案化牺牲层，从而图案化后的牺牲层具有形成在其内的开口。在开口中形成导电柱，并且如果第二衬底被设置在图案化牺牲层的上方，在第二衬底中形成导电柱。在第二衬底中形成通孔，且一个或多个集成电路管芯电连接到导电柱，其中，集成电路管芯连接到第二衬底的与导电柱相对的一侧。
根据其他实施例，提供另一种方法。该方法包括提供接合到第二载体衬底的第一载体衬底，以及在第一载体衬底和第二载体衬底上方分别形成第一牺牲层和第二牺牲层。图案化牺牲层以形成开口，用导电材料填充开口以形成柱状物。在第一牺牲层和第二牺牲层上方分别提供第一中介层衬底和第二中介层衬底，且在第一中介层衬底和第二中介层衬底中分别形成第一通孔和第二通孔。可分离第一载体衬底和第二载体衬底。
根据其他实施例，提供一种半导体器件。一种半导体器件包括中介层，具有延伸穿过中介层的多个通孔，其中，中介层包括预浸渍材料、味之素内置薄膜（ABF）或玻璃。一个或多个再分配层延伸在中介层的第一表面的上方，且导电柱从中介层的第二表面延伸。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结构的工艺、机器、制造、材料组分、装置、方法或步骤本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种方法，包括：
提供第一衬底；
在所述第一衬底的第一表面上方形成第一介电层；
在所述第一介电层上方形成图案化的牺牲层，所述图案化的牺牲层具有形成在其中的开口；
在所述图案化的牺牲层的开口中形成导电柱；
在所述图案化的牺牲层上方形成第二衬底；
在所述第二衬底中形成通孔；以及
将一个或多个集成电路管芯电连接到所述导电柱，所述集成电路管芯连接到所述第二衬底的与所述导电柱相对的一侧。
2.根据权利要求1所述的方法，进一步包括：在将所述一个或多个集成电路管芯电连接到所述导电柱之前，在所述第二衬底上形成一个或多个再分配层，所述一个或多个再分配层夹置在所述第一衬底和所述第二衬底之间。
3.根据权利要求2所述的方法，进一步包括：将所述第二衬底分割成多个衬底。
4.一种方法，包括：
提供接合到第二载体衬底的第一载体衬底；
在所述第一载体衬底和所述第二载体衬底上方分别形成第一牺牲层和第二牺牲层；
图案化所述第一牺牲层和所述第二牺牲层以形成开口；
用导电材料填充所述开口，从而形成柱状物；
在所述第一牺牲层和所述第二牺牲层上方分别提供第一中介层衬底和第二中介层衬底；
在所述第一中介层衬底和所述第二中介层衬底中分别形成第一通孔和第二通孔，所述第一通孔和所述第二通孔电接触所述开口中对应的导电材料；以及
将所述第一载体衬底和所述第二载体衬底分离开。
5.根据权利要求4所述的方法，进一步包括：分别形成介于所述第一载体衬底与所述第一牺牲层之间的介电层以及所述第二载体衬底与所述第二牺牲层之间的介电层。
6.一种半导体器件，包括：
中介层，具有延伸穿过所述中介层的多个通孔，所述中介层由预浸材料或玻璃形成；
一个或多个再分配层，在所述中介层的第一表面上延伸；以及
导电柱，从所述中介层的第二表面延伸。
7.根据权利要求6所述的半导体器件，进一步包括位于所述导电柱的端部上方的焊料。
8.根据权利要求7所述的半导体器件，其中，所述焊料沿着所述导电柱的侧壁延伸。
9.根据权利要求8所述的半导体器件，进一步包括一个或多个集成电路管芯，所述一个或多个集成电路管芯附接到所述一个或多个再分配层的最上面的再分配层。
10.根据权利要求9所述的半导体器件，进一步包括模制底层填料，所述底层填料介于所述一个或多个集成电路管芯和所述一个或多个再分配层之间。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786262A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 互连芯片

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11037904B2 (en) * 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
WO2017131683A1 (en) * 2016-01-28 2017-08-03 Intel IP Corporation Integrated circuit packages
CN108022897A (zh) 2016-11-01 2018-05-11 财团法人工业技术研究院 封装结构及其制作方法
TWI637471B (zh) * 2016-11-01 2018-10-01 財團法人工業技術研究院 封裝結構及其製作方法
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法
US10930633B2 (en) 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
US11264359B2 (en) * 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US12094828B2 (en) 2020-07-17 2024-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Eccentric via structures for stress reduction
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
KR20220022762A (ko) 2020-08-19 2022-02-28 삼성전자주식회사 반도체 패키지
US20230099827A1 (en) * 2021-09-24 2023-03-30 Intel Corporation Technologies for high throughput additive manufacturing for integrated circuit components

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010951A (en) * 1998-04-14 2000-01-04 National Semiconductor Corporation Dual side fabricated semiconductor wafer
US20060214294A1 (en) * 2005-03-28 2006-09-28 Fujitsu Limited Semiconductor device and a semiconductor device manufacturing method
CN101355845A (zh) * 2007-07-25 2009-01-28 欣兴电子股份有限公司 具有导电凸块的基板及其工艺
US20110095418A1 (en) * 2009-10-26 2011-04-28 Hwan-Sik Lim Semiconductor package and method for fabricating the same
US20120175732A1 (en) * 2008-12-08 2012-07-12 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming Same
US20120211892A1 (en) * 2011-02-22 2012-08-23 Stats Chippac, Ltd. Semiconductor Device and Method of Forming WLCSP Structure Using Protruded MLP
JP2012186270A (ja) * 2011-03-04 2012-09-27 Toppan Printing Co Ltd 半導体パッケージの製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876088B2 (en) 2003-01-16 2005-04-05 International Business Machines Corporation Flex-based IC package construction employing a balanced lamination
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly
US7626829B2 (en) * 2004-10-27 2009-12-01 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
US7882628B2 (en) * 2007-05-30 2011-02-08 Intel Corporation Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
JP5269563B2 (ja) * 2008-11-28 2013-08-21 新光電気工業株式会社 配線基板とその製造方法
US10276486B2 (en) * 2010-03-02 2019-04-30 General Electric Company Stress resistant micro-via structure for flexible circuits
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US20120313190A1 (en) * 2011-06-09 2012-12-13 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Packaged device including interposer for increased adhesive thickness and method of attaching die to substrate
US8741691B2 (en) * 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
US9026872B2 (en) * 2012-08-16 2015-05-05 Xilinx, Inc. Flexible sized die for use in multi-die integrated circuit
US9320149B2 (en) * 2012-12-21 2016-04-19 Intel Corporation Bumpless build-up layer package including a release layer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010951A (en) * 1998-04-14 2000-01-04 National Semiconductor Corporation Dual side fabricated semiconductor wafer
US20060214294A1 (en) * 2005-03-28 2006-09-28 Fujitsu Limited Semiconductor device and a semiconductor device manufacturing method
CN101355845A (zh) * 2007-07-25 2009-01-28 欣兴电子股份有限公司 具有导电凸块的基板及其工艺
US20120175732A1 (en) * 2008-12-08 2012-07-12 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming Same
US20110095418A1 (en) * 2009-10-26 2011-04-28 Hwan-Sik Lim Semiconductor package and method for fabricating the same
US20120211892A1 (en) * 2011-02-22 2012-08-23 Stats Chippac, Ltd. Semiconductor Device and Method of Forming WLCSP Structure Using Protruded MLP
JP2012186270A (ja) * 2011-03-04 2012-09-27 Toppan Printing Co Ltd 半導体パッケージの製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786262A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 互连芯片
US10720401B2 (en) 2017-11-15 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
CN109786262B (zh) * 2017-11-15 2021-06-22 台湾积体电路制造股份有限公司 互连芯片
US11532585B2 (en) 2017-11-15 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package containing device dies and interconnect die and redistribution lines
US11978714B2 (en) 2017-11-15 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Encapsulated package including device dies connected via interconnect die

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