CN100435302C - 芯片内置基板的制造方法 - Google Patents

芯片内置基板的制造方法 Download PDF

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CN100435302C
CN100435302C CNB2005100742271A CN200510074227A CN100435302C CN 100435302 C CN100435302 C CN 100435302C CN B2005100742271 A CNB2005100742271 A CN B2005100742271A CN 200510074227 A CN200510074227 A CN 200510074227A CN 100435302 C CN100435302 C CN 100435302C
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山野孝治
荒井直
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Abstract

在本发明的内置半导体芯片的芯片内置基板的制造中，提高了与半导体芯片连接的布线的定位精度，抑制布线的连接不良的产生。该芯片内置基板的制造方法具有：在基板上设置半导体芯片的第1工序；形成与设置在上述基板上的上述半导体芯片电连接的芯片连接布线的第2工序，其特征在于包括：在上述第1工序之前，在上述基板上形成用于上述芯片连接布线的定位的对准端子的工序。由于形成了该对准端子，所以形成上述芯片连接布线时的定位精度变得良好。

Description

芯片内置基板的制造方法
技术领域
本发明涉及内置有半导体芯片的芯片内置基板的制造方法。
背景技术
现在，使用了半导体芯片等半导体器件的电子设备正在高性能化，要求在将半导体芯片安装到基板上时的高密度化、安装了半导体芯片后的基板的小型化、省空间化等。
因此，提案出了安装有半导体芯片的基板，即所谓的芯片内置基板，还提案出了用于将半导体芯片内置到基板中的各种结构。
另外，在形成芯片内置基板的情况下，有必要形成与半导体芯片连接的布线，正在进行与这些半导体芯片连接的布线的高密度化、高精细化。
专利文献1：日本特开2001-217381号公报
但是，在芯片内置基板中，如果使与半导体芯片连接的布线细微化，则该布线和半导体芯片的连接的精度有可能成为问题，会产生因与半导体芯片连接的布线连接的不良造成的生产率降低。
这是由于对与半导体芯片连接的布线进行布图(patterning)的照相平板印刷工序中的曝光位置精度不足而产生的问题，必须提高由现有的曝光位置精度决定的布线定位精度。
发明内容
因此，在本发明中，其课题就是提供一种解决了上述问题的新的有用的芯片内置基板的制造方法。
本发明的具体课题是在内置半导体芯片的芯片内置基板的制造中，提高与半导体芯片连接的布线的定位精度，抑制布线连接不良的产生。
在本发明中，通过以下的芯片内置基板的制造方法解决上述问题，包括：在基板上设置半导体芯片的第1工序；形成与设置在上述基板上的上述半导体芯片电连接的芯片连接布线的第2工序，其特征在于还包括：在上述第1工序之前，在上述基板上形成用于上述芯片连接布线的定位的对准端子(alignment post)的工序。
根据本发明，在形成上述芯片连接布线的情况下，由于形成成为该芯片连接布线的定位基准的对准端子，所以形成上述芯片连接布线时的定位精度良好，能够抑制布线连接不良的产生。
另外，如果在形成上述芯片连接布线的布图的保护层(regist)的步进曝光的定位中使用上述对准端子，则提高了用于形成芯片连接布线的保护层的布图精度，是适合的。
另外，如果在上述半导体芯片和形成在上述基板上的绝缘层上形成上述芯片连接布线，则是适合的。
另外，如果在上述基板上设置上述半导体芯片时的定位中使用上述对准端子，则设置半导体芯片的位置精度良好，是适合的。
另外，如果通过Cu电镀形成上述对准端子，则能够公用与其他布线工序一样的设备、材料，是适合的。
根据本发明，在内置半导体芯片的芯片内置基板的制造中，能够提高与半导体芯片连接的布线的定位精度，抑制布线的连接不良的产生。
附图说明
图1(A)-(D)是依照步骤说明实施例1的芯片内置基板的制造方法的图(其1)。
图2(E)-(H)是依照步骤说明实施例1的芯片内置基板的制造方法的图(其2)。
图3是模式地表示使用实施例1所记载的方法形成的芯片内置基板的截面图。
具体实施方式
接着，以下根据附图说明本发明的实施例。
[实施例1]
图1(A)～(D)、图2(E)～(H)是依照步骤表示本发明的实施例1的内置了半导体芯片的芯片内置基板的制造方法的图。
首先，在图1(A)所示的工序中，在基板11上形成例如由Cu构成的对准端子13。上述基板11可以使用各种材料，但例如可以使用由树脂材料构成的核心(core)基板。另外，也可以在上述基板11上直接接触地形成上述对准端子，但例如如本图所示那样，可以在形成在上述基板11上的基底层12上形成。上述基底层12例如由形成在上述基板11上的布线图案和形成在该布线图案之间的绝缘层构成。另外，在本图中，省略了上述基底层12的布线图案的图示。
上述对准端子13在后面的工序中，作为对与设置在上述基板11上的半导体芯片连接的芯片连接布线进行布图时的布图位置的基准而使用。另外，也可以作为在将半导体芯片设置到基板上时的位置基准而使用。
上述对准端子13例如能够通过基于半添加法的Cu的电解电镀的布图法而形成。在该情况下，由于用与形成上述芯片连接布线等的其他布线图案时一样的材料和方法来形成，所以能够共用材料和设备，是适合的。另外，对准端子不只限定于Cu的电镀法，也可以使用其他各种材料，用各种方法形成。
接着，在图1(B)所示的工序中，在上述基板11上的例如上述基底层12上设置半导体芯片14。在该情况下，在面对上述半导体芯片14的上述基板11的侧面，可以设置在本图中未图示的粘接层，该粘接层例如可以用带状的(接触膜)或蜡材料。
另外，在上述半导体芯片14上形成未图示的例如由Al构成的电极焊点，进而形成多个与该电极焊点电连接的布线端子15，使得在该半导体芯片14上竖起。
接着，在图1(C)所示的工序中，在上述基板11上层叠例如由环氧树脂构成的绝缘膜，使得覆盖上述半导体芯片14、对准端子13和基底层12，根据需要，在按压、加热的基础上使绝缘膜硬化，形成绝缘层16。进而，通过等离子处理对该绝缘层16进行成灰，使上述对准端子13和上述布线端子15的前端露出。另外，在该成灰后，也可以进行被称为除去工序的除去成灰后的残留物的基于酸性溶液的湿(wet)处理。
另外，在上述基板11的与形成上述绝缘层16的面相反的面上，可以形成由与该绝缘层16一样的材料构成的绝缘层17。通过形成该绝缘层17，缓和上述绝缘层16对上述基板11的应力，能够抑制上述基板11的颠倒。
接着，在图1(D)所示的工序中，通过Cu的无电解电镀形成后面的Cu的电解电镀时的成为种子层的Cu种子层18，使得覆盖上述绝缘层16、对准端子13和布线端子15。进而，在上述Cu种子层18上，对用于形成基于Cu电解电镀的布线图案的保护层19进行层叠。另外，也可以通过涂抹形成该保护层19。
接着，在图2(E)所示的工序中，进行上述保护层19的曝光和显影，对用于对与上述布线端子15连接的芯片连接布线进行布图的该保护层19进行布图。在该情况下，该保护层19的曝光将上述对准端子作为曝光的基准位置。因此，可以通过具有例如与在将器件形成在上述半导体芯片上时所使用的曝光装置一样的精度的步进装置，实施该曝光。以前，在进行这样的曝光时使用的接触对准器等的曝光装置其曝光位置的定位精度差，成为了形成布线时的连接不良的原因。因此，在本实施例中，在上述基板11上设置上述对准端子13，形成为了曝光位置精度的成为基准的识别标记。因此，可以在上述保护层19的曝光中，使用在半导体晶片上形成器件的所谓前工序中使用的具有细微并且正确的定位精度的步进装置。因此，与现有的接触对准器相比，曝光即保护层的布图的定位精度(对准精度)变得良好，布线的定位精度(对准精度)变得良好，能够抑制布线的连接不良等不良的产生。
另外，上述对准端子13在上述图1(B)所示的工序中，在通过芯片安装器，在上述基板11上设置上述半导体芯片14的情况下，也可以作为该芯片安装器的定位(对准)的基准点使用，能够使设置半导体芯片的定位精度良好。
这样，通过使用上述对准端子15，内置了半导体芯片的芯片内置基板的布线的对准精度变得良好，在安装芯片时将该对准端子作为定位的基准点使用，其效果进一步变大，能够进一步降低布线连接的不良的产生概率。
另外，上述对准端子13能够形成在上述基板11的各种位置上，但理想的是例如形成在设置上述半导体芯片14的附近周围。
接着，在图2(F)所示的工序中，在对上述保护层19进行了布图(通过显影被除去)的部分(图2(E)的开口部分20)上，将上述Cu种子层18作为种子层，通过Cu的电解电镀形成与上述布线端子15电连接的芯片连接布线21，进行上述保护层19的剥离。
接着，在图2(G)所示的工序中，通过蚀刻，除去被上述芯片连接布线21覆盖的部分以外的上述Cu种子层18。
接着，在图2(H)所示的工序中，形成焊锡保护层22，使得覆盖上述绝缘层16、对准端子13和上述芯片连接布线21，在该焊锡保护层22上设置通过上述芯片连接布线21的开口部分，在面对该开口部分的上述芯片连接布线21上，形成Ni/Au电镀层23。
进而，形成与该Ni/Au电镀层23电连接的焊锡点24，接着，根据需要，对各芯片分别进行基板切块，完成内置了半导体芯片的芯片内置基板。
另外，根据需要，在上述焊锡点24上，可以进一步连接半导体芯片，另外，可以安装其他的电子器件、电子部件等。
[实施例2]
接着，图3表示了模式地表示使用实施例1所记载的方法而形成的芯片内置基板的截面的一个例子。
参照图3，使用例如由树脂材料构成的基板111形成本实施例所示的芯片内置基板，在该基板111上，形成由布图了的布线层构成的基底层112。在上述基底层112上，通过例如由膜等构成的粘接层131，设置固定在基板上的半导体芯片114。
在上述半导体芯片114上，形成与形成在该半导体芯片114上的器件连接的例如由Al构成的电极焊点132。形成例如由SiN等构成的保护层133，使得覆盖形成上述器件的面和上述电极焊点132，进而在保护层133上形成外部保护层134。
另外，在形成在上述外部保护层134和上述保护层133上的开口部分上，形成与上述电极焊点132连接的通过例如Cu的电镀形成的布线135。进而，在上述外部保护层134上，形成与上述布线135连接的通过Cu电镀被布图的布线136，在该布线136上，同样形成通过Cu电镀被布图的布线端子115。本实施例的布线端子115与实施例1所记载的布线端子15对应。
另外，在上述基底层112上，形成通过例如Cu电镀形成的对准端子113。本实施例的对准端子113与实施例1所记载的对准端子13对应，具有同样的功能，起到同样的效果。
另外，在上述基板111上，在上述布线端子115和对准端子113周围，形成例如由环氧树脂构成的绝缘层116，使得覆盖上述基底层112、半导体芯片114、外部保护层134和布线136。该绝缘层116能够与实施例1所记载的绝缘层16一样地形成。
另外，在上述绝缘层116上，形成通过Cu电镀布图形成的芯片连接布线121。本实施例的芯片连接布线121与实施例1所记载的芯片连接布线21对应，能够通过与实施例1所记载的形成该芯片连接布线21的方法一样地形成。
即，将上述对准端子113作为步进曝光的基准位置，对形成在上述绝缘层116上的保护层进行曝光并布图，使用该保护层的布图，通过Cu电镀形成上述布线121。在该情况下，对准端子113具有与实施例1所记载的对准端子13一样的效果，保护层的布图的定位精度变得良好，布线的定位精度变得良好，能够抑制布线的连接不良等不良的产生。
另外，形成具有与实施例1所记载的焊锡保护层22、Ni/Au电镀层23和焊锡点24一样的结构的焊锡保护层122、Ni/Au电镀层123和焊锡点124，构成芯片内置基板。另外，与实施例1的情况一样，可以在上述基板111的与形成上述绝缘层116的面的相反侧的面上，形成由与该绝缘层116一样的材料构成的绝缘层117。通过形成该绝缘层117，缓和上述绝缘层116对上述基板111的应力，能够抑制上述基板111的颠倒。
另外，根据需要，例如沿着线137，对本实施例的基板切块而分片化。
对于本实施例所记载的对准端子113，例如高度(从与上述基底层112相接的部分到上述绝缘层116的上端面)是100μm，但并不只限于该数字。
另外，本实施例的对准端子113的截面例如是一边大致为80μm的大致长方形，但并不只限于该形状或该数字。
上述对准端子为了用于步进装置的对准，可以具有为了成为步进曝光的位置基准而被识别的形状。
另外，本实施例的对准端子例如通过Cu电镀而形成，但并不只限于此，可以通过各种材料、方法形成。
以上，说明了本发明的理想实施例，但本发明并不只限于上述特定的实施例，在权利要求所记载的范围内，可以有各种变形和变更。
根据本发明，在内置半导体芯片的芯片内置基板的制造中，能够提高与半导体芯片连接的布线的定位精度，抑制布线的连接不良的产生。

Claims (4)

1.一种芯片内置基板的制造方法，该基板包含半导体芯片，其特征在于包括：
在基板上设置半导体芯片的第1工序；
形成与设置在上述基板上的上述半导体芯片电连接的芯片连接布线的第2工序；
在上述第1工序之前，在上述基板上形成用于上述芯片连接布线的定位的对准端子的工序，其中
在上述半导体芯片上形成绝缘层，
在上述基板的设置上述半导体芯片一侧的相反侧的面上，形成由与上述绝缘层相同的材料构成而用于抑制该基板的颠倒的绝缘层。
2.根据权利要求1所述的芯片内置基板的制造方法，其特征在于：
将上述对准端子用于形成上述芯片连接布线的布图的保护层的步进曝光的定位。
3.根据权利要求1或2所述的芯片内置基板的制造方法，其特征在于：
将上述对准端子用于在上述基板上设置上述半导体芯片时的定位。
4.根据权利要求1或2所述的芯片内置基板的制造方法，其特征在于：
上述对准端子通过Cu电镀形成。
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