CN110581120B - 板级扇出封装基板的细线路结构及其制备方法 - Google Patents
板级扇出封装基板的细线路结构及其制备方法 Download PDFInfo
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- CN110581120B CN110581120B CN201910856548.9A CN201910856548A CN110581120B CN 110581120 B CN110581120 B CN 110581120B CN 201910856548 A CN201910856548 A CN 201910856548A CN 110581120 B CN110581120 B CN 110581120B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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CN201910856548.9A CN110581120B (zh) | 2019-09-11 | 2019-09-11 | 板级扇出封装基板的细线路结构及其制备方法 |
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CN201910856548.9A CN110581120B (zh) | 2019-09-11 | 2019-09-11 | 板级扇出封装基板的细线路结构及其制备方法 |
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CN110581120A CN110581120A (zh) | 2019-12-17 |
CN110581120B true CN110581120B (zh) | 2021-03-16 |
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CN201910856548.9A Active CN110581120B (zh) | 2019-09-11 | 2019-09-11 | 板级扇出封装基板的细线路结构及其制备方法 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN113299564A (zh) * | 2021-05-21 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | 一种板级扇出柔性封装基板的封装结构及其制备方法 |
CN113808958A (zh) * | 2021-09-17 | 2021-12-17 | 成都奕斯伟系统集成电路有限公司 | 一种芯片封装结构制作方法及芯片封装结构 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900547A (zh) * | 2015-06-05 | 2015-09-09 | 华进半导体封装先导技术研发中心有限公司 | 多元合金成分的微凸点制备工艺 |
CN107203099A (zh) * | 2016-03-18 | 2017-09-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006165175A (ja) * | 2004-12-06 | 2006-06-22 | Alps Electric Co Ltd | 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法 |
US9754835B2 (en) * | 2010-02-16 | 2017-09-05 | Deca Technologies Inc. | Semiconductor device and method comprising redistribution layers |
CN103745937B (zh) * | 2014-02-08 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | 扇出型圆片级封装的制作工艺 |
CN105575832A (zh) * | 2015-12-22 | 2016-05-11 | 华进半导体封装先导技术研发中心有限公司 | 一种多层堆叠扇出型封装结构及制备方法 |
CN108990298A (zh) * | 2018-07-26 | 2018-12-11 | 深圳崇达多层线路板有限公司 | 一种以镍为种子层及抗蚀层制作精细线路的方法 |
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2019
- 2019-09-11 CN CN201910856548.9A patent/CN110581120B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900547A (zh) * | 2015-06-05 | 2015-09-09 | 华进半导体封装先导技术研发中心有限公司 | 多元合金成分的微凸点制备工艺 |
CN107203099A (zh) * | 2016-03-18 | 2017-09-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Thin circuit structure of board level fan out packaging substrate and its preparation method Effective date of registration: 20211229 Granted publication date: 20210316 Pledgee: Guangdong Shunde Rural Commercial Bank Co.,Ltd. science and technology innovation sub branch Pledgor: Guangdong fozhixin microelectronics technology research Co.,Ltd.|Guangdong Xinhua Microelectronics Technology Co.,Ltd. Registration number: Y2021980016930 |
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Effective date of registration: 20230904 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
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