CN100573865C - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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Abstract
本发明公开了一种半导体封装,配置成包括:半导体晶片(110);树脂件(106),用于形成在其中安装此半导体晶片(110)的凹进(109);以及,布线(105),其由图形布线(105b)和接线柱部(105a)构成,图形布线(105b)形成为暴露于此树脂件(106)的上表面(106b),并且还与半导体晶片(110)相连接,以及,接线柱部(105a)一端与图形布线(105b)相连接,而其另一端则形成为暴露于树脂件(106)的下表面(106a)。
Description
技术领域
本披露涉及一种半导体封装及其制造方法,以及,特别涉及一种在三维空间中安装的半导体封装及其制造方法。
背景技术
近年来,迫切需要使其中安装有半导体封装的电子设备等小型化和薄型化。因此,提出了一种被称为所谓封装叠加(POP,package-on-package)的封装结构,其中,通过将半导体封装层叠可以进行三维安装,以改进半导体封装的安装密度(例如,参见专利文献1:日本专利未经审查的公开No.2002-158312)。
在这种半导体封装中,预先制成其中形成有布线的树脂基板,通过布线接合或者倒装晶片的方法等,在这种树脂基板上安装元件诸如半导体晶片,其后,用成型树脂或者环氧树脂形成密封树脂。
然后,通过用激光照射密封树脂,在树脂基板上形成用于露出布线的开口,并且还在开口中使用电镀法形成布线。结果,形成一种布线,其一端与树脂基板的布线相连接,而另一端则暴露于树脂基板的上表面。
通过形成这样延伸穿过密封树脂的布线,在树脂基板的上表面上可以安装另一半导体封装。在相关技术中,使用这样一种技术,可以进行半导体封装的三维安装。
然而,在相关技术的半导体封装中,需要树脂基板,因而存在半导体封装变得较高(较厚)的问题。尤其是,当将具有此树脂基板的半导体封装层叠以用于三维安装时,层叠之后的整体高度变高,而且,其中安装了此半导体封装的电子设备等的高度也难以减小。
此外,在相关技术的半导体封装中,配置成在树脂基板上安装半导体晶片,并进一步布置密封树脂以覆盖半导体晶片,因而,同样存在因为此配置使半导体封装变高的问题。
发明内容
本发明的实施方式提供一种能实现薄型化的半导体封装,以及此半导体封装的制造方法。
为了解决上述问题,本发明的特征在于采取了以下措施。
根据本发明一个或者更多实施例的第一方面,一种半导体封装,包括:树脂件,具有其中安装有半导体晶片的凹进;以及布线,具有图形布线部和接线柱部,图形布线部形成为从树脂件的第一表面露出,并且还与半导体晶片相连接,而接线柱部形成为在树脂件的厚度方向延伸,其中,接线柱部为通过电镀法形成的柱形,接线柱部中的一端与图形布线部相连接,以及,接线柱部的另一端形成第一电极,所述第一电极从树脂件的与第一表面相反的第二表面露出,以及,第一电极用于形成外连接端。
根据本发明的第一方面,不需要在相关技术中使用的树脂基板,使得成本降低并使半导体封装变薄。此外,半导体晶片安装于树脂件中形成的凹进内,使得与安装在树脂件上的配置相比,可以减小半导体封装的高度。
此外,根据本发明的一个或者更多实施例的第二方面,在半导体封装的第一方面中,凹进的深度大于或者等于半导体晶片的厚度。以及,接线柱部为柱形,且具有全部相同的截面直径,因而,与具有圆锥形电极等相比,可以改善电特性。
根据本发明的第二方面,能可靠地减少半导体封装的高度。
此外,根据本发明的一个或者更多实施例的第四方面,在半导体封装的第一方面至第三方面的任一方面中,半导体晶片安装在凹进中。
此外,根据本发明的一个或者更多实施例的第五方面,一种在树脂件上安装有半导体晶片的半导体封装的制造方法,包括:第一步骤,在支撑基板上形成图形布线部;第二步骤,在支撑基板上对应于半导体晶片安装位置的位置中,通过电镀法凸出并形成模部;第三步骤,利用抗蚀剂图形,通过用电镀法在图形布线部上形成接线柱部而形成布线;第四步骤,通过布置用于密封模部和接线柱部的树脂,形成树脂件;以及第五步骤,连同模部一起除去支撑基板,并在树脂件中形成凹进部。
根据本发明的第五方面,通过在第五步骤中除去支撑基板,在树脂件中形成对应于模部的凹进。所以,与形成树脂件之后单独形成凹进的方法相比,可以简单地形成具有高精度的凹进。
此外,根据本发明一个或者更多实施例的第六方面,半导体封装制造方法的第五方面进一步包括第六步骤,在凹进部中安装半导体晶片,并且还连接半导体晶片和图形布线部。
此外,根据本发明一个或者更多实施例的第七方面,在半导体封装制造方法的第五或者第六方面中,在第四步骤中,使用液态树脂作为树脂件的材料,并且在液态树脂布置在支撑基板上之后,使液态树脂固化并且形成树脂件。
根据本发明的第七方面,使用液态树脂作为树脂件的材料,从而,即使在图形布线部上形成多个接线柱部以使其在厚度方向延伸时,也能用树脂件可靠地密封接线柱部。
此外,根据本发明的一个或者多个实施例的第八方面,在半导体封装制造方法的第六或者第七方面中,在第六步骤中,通过布线接合使半导体晶片与图形布线相连接。
根据本发明的第八方面,通过布线接合使半导体晶片与图形布线相连接,因而可以使连接具有高可靠性。此外,使用液态树脂作为密封树脂的材料,从而,即使在通过布线使半导体晶片与图形布线部相连接时,也能避免由于液态树脂的布置而使布线变形。
此外,根据本发明的一个或者多个实施例的第九方面,在布线基板制造方法的第五至第八方面的任一方面中,在第一步骤中,在支撑基板上形成阻挡层之后,再形成图形布线部,而且在第五步骤中,通过阻挡层阻止支撑基板的去除。
根据本发明的第九方面,用阻挡层停止支撑基板的去除,因而,可以避免支撑基板的去除处理对阻挡层内侧的层的影响。此外,使得在支撑基板的去除中去除处理的控制更加方便,并且可以简化半导体封装的制造。
不同的实现方式可以包括下列优点的一个或者更多。例如,半导体晶片安装于树脂件中形成的凹进里,使得半导体封装的高度可以减小。此外,不再需要相关技术中使用的树脂基板,从而实现成本降低和半导体封装薄型化。
根据以下详细描述、附图以及权利要求,其他的特点和优点将更为清楚。
附图说明
图1是图示本发明一种实施方式的半导体封装的剖视图;
图2是图示层叠两个图1所示半导体封装的状态的剖视图;
图3是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第一步);
图4是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第二步);
图5是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第三步);
图6是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第四步);
图7是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第五步);
图8是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第六步);
图9是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第七步);
图10是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第八步);
图11是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第九步);
图12是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十步);
图13是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十一步);
图14是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十二步);
图15是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十三步);
图16是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十四步);
图17是图示按照下列工艺规程的本发明一种实施方式的半导体封装的制造方法的图(第十五步)。
具体实施方式
下面,结合附图描述实现本发明的最佳实施方式。
图1是示意性图示本发明一种实施方式的半导体封装100的剖视图,而图2则图示通过层叠两个半导体封装100进行三维安装的状态。此半导体封装100大致由布线105、树脂件106、半导体晶片110、以及密封树脂115等构成。
布线105配置成整体方式形成接线柱部105a和图形布线105b。在图中,图示两处布线105,并且,与半导体晶片110上形成的电极焊盘等相对应地形成若干布线105。此布线105用具有良好导电性的Cu(铜)形成。
这样形成接线柱部105a,使其在起基板作用的树脂件106的厚度方向(图中上下方向)延伸。此外,接线柱部105a为柱形,并且如下文所述用电镀方法形成。在此接线柱部105a的下端,通过顺序地叠放Ni(镍)层118b和Au(金)层118a形成第一电极118。
此第一电极118从树脂件106的下表面106a(与权利要求中所述的第二表面对应)露出。此外,接线柱部105a的上端,配置成与图形布线105b相连接。另外,在下文的叙述中,设定图中箭头X1所示的方向为向下方向,而图中箭头X2所示的方向为向上方向。
图形布线105b形成在树脂件106上,按预定图形延伸。此图形布线105b的上表面从树脂件106的上表面106b(与权利要求中所述的第一表面对应)露出。
在图形布线105b从上表面106b露出的表面上,类似地形成第二电极102和焊盘108,第二电极102中顺序叠放镍层102b和金层102a,焊盘108中顺序叠放镍层108b和金层108a。此第二电极102和焊盘108如下文所述共同形成。
半导体晶片110配置成安装在树脂件106中形成的凹进109里。在本实施方式中,半导体晶片110形成为面朝上,并且,通过布线接合法,使金属丝111布置在形成于半导体晶片110上表面的电极焊盘(未示出)与形成于布线105上的焊盘108之间。结果,半导体晶片110配置成通过金属丝111与布线105(接线柱部105a、图形布线105b)电连接。
另外,在半导体晶片110的下部布置模片固定膜层110A,并将此模片固定膜层110A配置成与凹进109的底面结合。此外,本实施方式配置成通过布线接合法连接半导体晶片110和布线105,但通过倒装晶片接合,也能连接半导体晶片110和布线105。在这种情况下,不再需要模片固定膜层110A或者凹进109。
树脂件106是一种如下所述液态树脂固化了的物质。作为此树脂件106的材料,例如,可以使用环氧液态填充材料或者液态模塑材料,并且也可以使用液晶聚合物。
此树脂件106如此形成,以使其覆盖布线105。然而,构成布线105的接线柱部105a的下表面(其上形成第一电极118),和构成布线105的图形布线105b的上表面,此两表面配置成从树脂件106露出。
如图2所示,如上述配置的半导体封装100,通过使位于上部的半导体封装100中由焊料球制成的外连接端120与位于下部的半导体封装100的第二电极102结合,在三维空间进行安装。在这种情况下,将树脂制成的NCF 127(Non-Conductive Film,不导电膜)布置在位于上部的半导体封装100与位于下部的半导体封装100之间。
在结合一对上下半导体封装100的情况下,将此NFC 127预先布置在位于下部的半导体封装100上。然后,在使位于上部的半导体封装100的外连接端120与位于下部的半导体封装100的第二电极102结合的情况下,同时固化NCF 127。结果,可以改进三维安装中半导体封装100的接合可靠性。另外,安装此NCF 127也并非不可缺少。
如上所述配置的半导体封装100具有一种配置,其中半导体晶片110安装在树脂件106中形成的凹进109里。所以,从侧面看,半导体晶片110的厚度与树脂件106的厚度处于叠加的状态,从而可以减小半导体封装100的高度。
此外,与相关技术的半导体封装不同,在根据本实施方式的半导体封装100中没有使用树脂基板。结果,能以相关技术中所用树脂基板的厚度,使半导体封装100的厚度变薄,而且还可以减少元件数,从而可以实现成本降低。
下面,参照图3至图17,描述如上所述配置的半导体封装100的制造方法。
为了制造半导体封装100,首先,制备如图3所示的导电材料(例如,铜)制成的支撑基板101。然后,使用电镀法,在此支撑基板101的下表面上形成阻挡层121。此阻挡层121具有一种结构,其中叠合了0.1-0.2μm厚的金层121a和0.1-3μm厚的镍层121b。在这种情况下,在除晶片安装对应位置A(下述模部107形成的位置)之外的其他地方形成阻挡层121,如图4所示。
作为具体的形成方法,通过光刻法,在支撑基板101上晶片安装对应位置A上,首先形成抗蚀剂图形(未示出)。然后,利用此抗蚀剂图形作为掩模,通过电镀,相继沉淀金层121a和镍层121b,然后,除去抗蚀剂图形。结果,在支撑基板101中除晶片安装对应位置A以外的位置中,形成了阻挡层121。
另外,在下面描述的后继步骤的电镀中,支撑基板101和阻挡层121形成电流传输通路,因而,支撑基板101和阻挡层121优选为导电材料。
在图5所示的下一步骤中,在阻挡层121上形成图形布线105b。通过光刻法在阻挡层121上形成光致抗蚀剂图形(未示出),并且利用此抗蚀剂图形作为掩模,通过电镀在阻挡层121上沉淀铜,然后除去抗蚀剂图形。
当如上所述形成图形布线105b时,在本实施方式中接着执行模部107的形成步骤。图6至图8图示模部107的制造处理。为了制造模部107,首先,形成具有开口103A的光致抗蚀剂图形103,如图6所示。在此光致抗蚀剂图形103中,布置一种膜状光致电导树脂膜,以覆盖支撑基板101,并且使用掩模(未示出),使与晶片安装对应位置A相对应的部分曝光并显影,从而,形成与晶片安装对应位置A相对应的开口103A。
下面,利用此光致抗蚀剂图形103作为掩模,通过电镀用沉淀铜形成模部107。图7图示在开口103A内形成模部107的状态。随后,如图8所示,经除去光致抗蚀剂图形103形成模部107。
此模部107形成为对应下文描述的半导体晶片110的形状和安装位置。具体地,从底部观看的模部107的形状,形成得稍大于从该平面观看的半导体晶片110的形状,并且模部107的高度(图8中用箭头T表示),设定得大于等于半导体晶片110的厚度(包括模片固定膜层110A的厚度)。所以,模部107形成由支撑基板101下表面向下凸出的形状。
当如上所述在支撑基板101上形成了模部107时,接着执行接线柱部105a的形成处理。为了形成接线柱部105a,形成光致抗蚀剂图形104,使光致抗蚀剂图形104覆盖在其上形成有图形布线105b和模部107的支撑基板101上。
在此光致抗蚀剂图形104中,首先利用旋涂器(spinner)等按预定厚度向支撑基板101施加光致抗蚀剂,或者布置具有预定厚度的光致抗蚀剂膜,通过光刻法使光致抗蚀剂形成图形,从而,形成具有开口104A的光致抗蚀剂图形104。图9图示具有开口104A的光致抗蚀剂图形104形成在支撑基板101上的状态。
然后,在图10的步骤中,使用此光致抗蚀剂图形104作为掩模,通过电镀沉淀铜,并且在开口104A内沉淀接线柱部105a。结果,形成由接线柱部105a和图形布线105b组成的布线105。
这样形成的接线柱部105a配置成在图中的上下方向(半导体封装100的厚度方向)延伸。以及,接线柱部105a的上端配置成与图形布线105b整体方式连接,而其下端则配置成从开口104A露出外部。
然后,在接线柱部105a从开口104A露出的端部上形成第一电极118。此第一电极118用电镀法相继叠加镍层118b和金层118a形成。当如上所述形成接线柱部105a(布线105)和第一电极118时,除去光致抗蚀剂图形104。图11图示除去光致抗蚀剂图形104的状态。
接着,在图12的步骤中,形成树脂件106。本实施方式的特征在于利用液态树脂作为树脂件106的材料。作为液态树脂,可以使用环氧液态填充材料或者液态模塑材料,并且也可以使用液晶聚合物。另外,使用液态填充材料或者液态模塑材料作为液态树脂时,在布置于支撑基板101上之后,进行固化处理。
这样,通过使用液态树脂作为树脂件106,即使在图形布线105b上形成许多接线柱部105a使其在图中向下方向延伸(凸出)时,液态树脂也能在接线柱部105a之间流畅地移动。结果,即使存在许多接线柱部105a,在树脂件106内也不会形成气隙,并且能可靠地密封布线105和半导体晶片110等。
另外,在布置树脂件106之后,为了使第一电极118从树脂件106可靠地露出,可以对树脂件106的下表面106a进行磨光处理。
接着,在图13的步骤中,进行的处理为通过蚀刻除去支撑基板101(包括模部107)。在这种情况下,所采用的蚀刻液溶解支撑基板101(铜)但不溶解阻挡层121。结果,支撑基板101的去除到达阻挡层121停止,而塑模部107的去除也在树脂件106处停止。
结果,可以避免蚀刻液对在树脂件106内形成的布线105的影响。此外,使支撑基板101去除过程中的去除处理控制更加方便,并且可以简化半导体封装100的制造。
另外,通过除去支撑基板101,形成一种配置,其中不存在用于支撑树脂件106的部件,但在除去支撑基板101时,树脂件106固化从而保证预定的刚性。所以,即使不存在支撑基板101时,也可以执行此后的各步骤。
图13图示去除了支撑基板101的状态。在此支撑基板101的去除处理中,也同步去除了在支撑基板101上形成的模部107。结果,在树脂件106中形成了与模部107的形状相对应的凹进109。如上所述,形成模部107,使其与半导体晶片110的形状和安装位置相对应。所以,利用此模部107作为模具所形成的凹进109的形成位置和形状,也都与半导体晶片110的安装位置和形状对应。
接着,在图14的步骤中,在树脂件106的下表面106a上形成抗蚀剂图形125,并且还在形成于上表面的阻挡层121上形成抗蚀剂图形126。抗蚀剂图形125形成在整个下表面106a上。另一方面,在阻挡层121上形成的抗蚀剂图形126采用光刻法形成图形,从而使抗蚀剂图形126形成在以下位置上(参见图2):第二电极102的位置,三维安装时位于上部的半导体封装100的外连接端120与第二电极102相连接;以及焊盘108的形成位置,焊盘108与下文描述的连接于半导体晶片110的金属丝111相连接。
接着,使用抗蚀剂图形125和126作为掩模,进行阻挡层121(金层121a、镍层121b)的蚀刻处理。结果,在保留第二电极102和焊盘108的情况下,除去了阻挡层121的其余部分。随后,通过除去抗蚀剂图形125、126,在布线105(图形布线105b)上形成第二电极102和焊盘108,如图15所示。
然后,在图16的步骤中,进行用于将半导体晶片110安装进凹进109中的处理。具体地,使用模片固定膜层110A将半导体晶片110面朝上安装在凹进109内。
如上所述,凹进109形成为与模部107相对应的形状,这样,从平面观看时的形状,形成得稍大于从平面观看时半导体晶片110的形状,而其深度(图16中用箭头T表示)则设定得深于或者等于半导体晶片110的厚度(包括模片固定膜层110A的厚度)。所以,在半导体晶片110安装于凹进109中的情况下,使半导体晶片110处于嵌入在树脂件106中的状态。
此后,使用布线接合装置,用金属丝111使形成在半导体晶片110上的电极焊盘与形成在布线105上的焊盘108相连接。结果,配置成在半导体晶片110和布线105之间形成电连接。在本实施方式中,在半导体晶片110的安装中使用布线接合法,使得半导体晶片110和布线105能以高可靠性低成本方式相连接。
接着,在图17的步骤中,形成用于密封半导体晶片110的密封树脂115。布置此密封树脂115以保护半导体晶片110和布线111。在密封树脂115的形成中,可以采用模塑法或者灌注法。
当这样形成密封树脂115时,通过将焊料球结合在第一电极118上而形成外连接端120。通过执行如上所述的步骤,可以形成图1所示的半导体封装100。
在根据上述本实施方式的制造方法中,通过除去支撑基板101,可以在树脂件106中同步方式形成对应于模部107的凹进109。所以,与形成树脂件106之后单独形成凹进109的方法相比,可以简单地形成具有高精度的凹进109。
此外,在根据本实施方式的制造方法中,使用光致抗蚀剂图形104,通过电镀法形成接线柱部105a。结果,使用光刻技术,在光致抗蚀剂图形104中形成开口104A,以形成接线柱部105a,因而,能以高精度形成具有高纵横比的图形。
这样,使用光致抗蚀剂图形104,通过电镀并形成接线柱部105a,能形成具有高精度的接线柱部105a。所以,即使层叠多个半导体封装100以执行如图2所示的三维安装时,也能在外连接端120与第二电极102之间可靠地形成连接。
此外,如上所述,通过具有高纵横比的开口104A形成接线柱部105a,可以形成在厚度方向具有全部一致截面的柱形接线柱部105和具有良好电特性的布线,并且也能较好地应对高频信号。
另外,在上述半导体封装的制造方法中,为了说明的方便,只例示了从一个支撑基板101上制造一个半导体封装100的过程,但实际上是制造所谓的多封装。就是说,在一个支撑基板101上形成多个半导体封装100之后,再通过在预定位置切割,制造单个的半导体封装100。
通过优选实施方式对本发明进行了描述,但本发明并不局限于上述特定的实施方式,并且,可以对上述实施方式进行多种修改和改进,而不脱离权利要求中所描述的要旨范围。
具体地,上述实施方式配置成使用贵金属金层121a,与镍层121b一起作为阻挡层121。然而,贵金属如金的使用可能会增加半导体封装100的制造成本。因此,可以配置成只使用镍层作为阻挡层121。然而,在这种情况下,例如,在图14所示的步骤中,在形成只带有镍层108b、102b的焊盘108和第二电极102之后,通过给定的非电镀,在焊盘108和第二电极102的镍(Ni)层108b、102b上形成金层108a、102a。
此外,在上述实施方式中,凹进109的深度设定为使半导体晶片110完全嵌入凹进109的深度,但也不是必须使用这种配置。就是说,只要使用这样的配置,即,从平面观看的状态下半导体晶片110与树脂件106处于部分交叠,就能使半导体封装100由于此交叠尺寸减薄。
Claims (5)
1.一种在树脂件上安装半导体晶片的半导体封装的制造方法,所述方法包括:
第一步骤,在支撑基板上形成图形布线部;
第二步骤,在所述支撑基板上对应于所述半导体晶片安装位置的位置中,通过电镀法凸出并形成模部;
第三步骤,利用抗蚀剂图形,通过用电镀法在所述图形布线部上形成接线柱部而形成布线;
第四步骤,通过布置用于密封所述模部和所述接线柱部的树脂,形成树脂件;以及
第五步骤,连同所述模部一起除去所述支撑基板,并在所述树脂件中形成凹进部。
2.根据权利要求1所述的半导体封装的制造方法,进一步包括:
第六步骤,在所述凹进部中安装所述半导体晶片,并且还将所述半导体晶片与所述图形布线部连接。
3.根据权利要求1或者权利要求2所述的半导体封装的制造方法,其中,在所述第四步骤中,使用液态树脂作为所述树脂件的材料,并且在所述液态树脂布置在所述支撑基板上之后,使所述液态树脂固化并且形成所述树脂件。
4.根据权利要求2所述的半导体封装的制造方法,其中,在所述第六步骤中,通过布线接合使所述半导体晶片与所述图形布线部连接。
5.根据权利要求1或者权利要求2所述的半导体封装的制造方法,其中,在所述第一步骤中,在所述支撑基板上形成阻挡层之后,再形成所述图形布线部,而且在所述第五步骤中,所述支撑基板的去除在所述阻挡层处停止。
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JP5215244B2 (ja) * | 2009-06-18 | 2013-06-19 | 新光電気工業株式会社 | 半導体装置 |
JP5485110B2 (ja) * | 2010-10-29 | 2014-05-07 | 新光電気工業株式会社 | 配線基板及びその製造方法、電子装置 |
US20120139095A1 (en) * | 2010-12-03 | 2012-06-07 | Manusharow Mathew J | Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same |
US8714725B2 (en) * | 2011-11-10 | 2014-05-06 | Xerox Corporation | Image receiving member with internal support for inkjet printer |
US8867231B2 (en) * | 2012-01-13 | 2014-10-21 | Tyco Electronics Corporation | Electronic module packages and assemblies for electrical systems |
CN103400772B (zh) * | 2013-08-06 | 2016-08-17 | 江阴芯智联电子科技有限公司 | 先封后蚀芯片正装三维系统级金属线路板结构及工艺方法 |
US20150342046A1 (en) * | 2014-05-23 | 2015-11-26 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board, method for maufacturing the same and package on package having the same |
US9748187B2 (en) * | 2014-12-19 | 2017-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer structure and method for wafer dicing |
KR101939046B1 (ko) * | 2017-10-31 | 2019-01-16 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
CN108962766B (zh) * | 2018-07-19 | 2021-01-22 | 通富微电子股份有限公司 | 封装结构及其形成方法 |
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US5241456A (en) * | 1990-07-02 | 1993-08-31 | General Electric Company | Compact high density interconnect structure |
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US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
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US6528869B1 (en) * | 2001-04-06 | 2003-03-04 | Amkor Technology, Inc. | Semiconductor package with molded substrate and recessed input/output terminals |
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