TWI389281B - 形成覆晶凸塊載體型封裝體之方法 - Google Patents

形成覆晶凸塊載體型封裝體之方法 Download PDF

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TWI389281B
TWI389281B TW097115674A TW97115674A TWI389281B TW I389281 B TWI389281 B TW I389281B TW 097115674 A TW097115674 A TW 097115674A TW 97115674 A TW97115674 A TW 97115674A TW I389281 B TWI389281 B TW I389281B
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TW200913192A (en
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Wai Yew Lo
Heng Keong Yip
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Freescale Semiconductor Inc
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Description

形成覆晶凸塊載體型封裝體之方法 發明領域
本發明係有關積體電路(ICs)的封裝，尤係有關一種形成一覆晶凸塊載體型之封裝體的方法。
 發明背景
現代的消費電子用品，譬如手機、數位相機、和數位音樂播放器等，會衍生出更小積體電路的需求。故，半導體製造者和封裝公司等會持續不斷地縮小封裝的電子裝置之足印，並又同時逐增電路的功能性。一種縮減封裝體尺寸的方法係使用一設有凸塊的晶粒，並將該晶粒以一面朝下的方式電連接於一基材或載體。此係被稱為覆晶總成，因為該晶粒係面朝下或翻覆的，而相較於導線接結技術，其晶片是面朝上且導線係連接於該晶片頂上的接墊與該晶片底部所附接的載體之間。雖覆晶技術並非嶄新的，但其現在才剛逐漸地變成愈來愈普遍。
第1圖示出一封裝的裝置10，其中有一半導體晶粒12係以導線16等電連接於短柱凸塊14。該等導線16會由該晶粒12的頂部延伸至該等短柱凸塊14。一塑膠材料18會覆蓋該等導線和該晶粒10頂面以供保護。第2圖示出一封裝的裝置20，其中有一半導體晶粒22係以凸塊26等電連接於一載體或基材24。一填充材料28會佈設於該晶粒22與載體24之間。焊球30等會附接於該載體24的相反面上來對其它的電 子裝置提供電連接。一塑膠材料32，如虛線所示，會被設成圍繞該晶粒22來完成該封裝體20。
該封裝製程會是非常複雜，因為須改變各種材料成分，如該載體、晶粒、焊球和模複合物等。時常會遭遇到因過熱和緊密容差所造成的問題。例如，該等焊球30有時會由該載體24掉落或脫離。若能提供一種製造一可靠的覆晶封裝式裝置之方法將會是有利的。
 發明概要
依據本發明之一實施例，係特地提出一種封裝一半導體積體電路的方法，包含：提供一片金屬箔；在該片金屬箔之一第一表面中形成多數凹穴；以一導電金屬鍍覆該等凹穴；在該金屬箔的第一表面和該等經鍍覆凹穴上形成一絕緣膜；在該絕緣膜中形成多數通道，其中該等通道會接觸該等經鍍覆凹穴之個別一者；以一導電金屬鍍覆該等通道；形成一焊劑阻抗膜於該等絕緣膜和經鍍覆通道上；加工該焊劑阻抗膜，以在該等通道上方形成曝露區域；以一導電金屬鍍覆該等通道上方的該等曝露區域；將一設有凸塊的半導體晶粒附接於該金屬箔的該第一表面，其中該等晶粒凸塊會接觸經鍍覆曝露區域之個別一者，藉以將該晶粒電連接於該等經鍍覆凹穴；及除去該片金屬箔以使該等經鍍覆凹穴的外表面曝露，藉以使該等經鍍覆的凹穴外表面形成通至該半導體晶粒的電互接物。
依據本發明之一實施例，係特地提出一種形成多數個 半導體封裝體的方法，該方法包含：提供一片金屬箔；在該片金屬箔之一第一表面中形成多數凹穴；以一導電金屬鍍覆該等凹穴；在該金屬箔的該第一表面和該等經鍍覆凹穴上形成一絕緣膜；在該絕緣膜中形成多數通道，其中該等通道會接觸該等經鍍覆凹穴之個別一者；以一導電金屬鍍覆該等通道；形成一焊劑阻抗膜於該等絕緣膜和經鍍覆通道上；加工該焊劑阻抗膜，以在該等通道上方形成曝露區域；以一導電金屬鍍覆該等通道上方的該等曝露區域；將多數個設有凸塊的半導體晶粒附接於該金屬箔的該第一表面，其中該等晶粒凸塊會接觸經鍍覆曝露區域之個別一者；包封該等半導體晶粒和該金屬箔的該第一表面；除去該片金屬箔，以使該等經鍍覆凹穴的外表面曝露，藉以使該等經鍍覆凹穴外表面形成通至該等半導體晶粒的電互接物；及進行一切割操作，來分開相鄰之各晶粒，藉以形成個別的半導體封裝體。
圖式簡單說明
以下之本發明的較佳實施例之詳細描述將可配合所附圖式來參閱而更佳地瞭解。本發明係藉舉例來說明，而不被所附圖式所限制，其中相同的標號係指類似的元件。應請瞭解該等圖式並不依照比例，且已被簡化以便容易瞭解本發明。
第1圖係為一傳統的凸塊晶片載體型封裝體之放大截面圖；第2圖係為一傳統的覆晶球柵陣列型封裝體之放大截 面圖；及第3-12圖係示出依據本發明一實施例之形成覆晶凸塊載體型封裝裝置的方法之各放大截面圖。
 較佳實施例之詳細說明
配合所附圖式被載示於後的詳細描述係意圖作為本發明之一目前較佳實施例的說明，而非用以代表本發明可被實施的唯一形式。應請瞭解相同或等效的功能亦可被以不同的實施例來達成，它們係意圖被包含在本發明的精神和範圍內。在該等圖式中，相同的編號會被用來標示所有相同的元件。
本發明提供一種形成半導體封裝體的方法，包含如下步驟：提供一片金屬箔，並在該片金屬箔之一第一表面中形成多數的凹穴。該等凹穴會被鍍以一導電金屬。一絕緣膜會被形成於該金屬箔的第一表面和該等被鍍的凹穴上。通道嗣會被切成於該絕緣膜中。該等通道會接觸一各自的被鍍凹穴。然後該等通道會被鍍以一導電金屬。一焊劑量阻抗膜會被覆設在該絕緣膜及被鍍的通道上，並被加工而在該等通道上形成曝露區域。該等曝露區域嗣會被鍍以一導電金屬。一設有凸塊之覆晶晶粒會被附接於該金屬箔的第一表面。該等晶粒凸塊會接觸一各自的被鍍曝露區域，而將該晶粒電連接於該等被鍍的凹穴。該片金屬箔會被移除，而曝露出該等被鍍凹穴的外表面，以使該等被鍍的凹穴外表面形成通至一印刷配線板或外部載體的電互接物。
一種形成多數個覆晶凸塊載體型封裝體100的方法現將參照第3~12圖說明於後。
現請參閱第3圖，一條或一片導電材料102會被提供。該導電材料片102可為方形、矩形或圓形如一晶圓，並可被例如以切割、冲壓或蝕刻來成型。在一實施例中，該導電材料片102係由一裸金屬譬如銅箔所形成，且係約為0.5mm厚。但是，本發明並不被金屬片102的特定材料、尺寸或厚度所限制。
一光微影材料104會被塗敷於該導電片102之一第一或頂部表面上，並被固化。一光罩，未示出，會被覆設在該光微影材料上。如在該領域中所習知，該光微影材料104可包含一阻抗塗層或一乾膜疊層。
請參閱第4圖，該光微影材料104和該導電片102會被曝光及顯影，或以一習知方式處理而在該導電片102的頂面上形成一預定圖案。嗣該導電片102會被蝕刻。一種習知的蝕刻方法係使用一酸浴，其中該等無疊層或塗層的區域會被蝕刻。該預定的圖案包含多數個凹穴106等，其會切穿該光微影材料104並伸入導電片102中。
請參閱第5圖，該等凹穴106會被鍍以一導電金屬108來形成外部電互接物，於後將會瞭解。該導電金屬108可為一金屬例如金、或一例如由鈀和鎳組成的合金。於本發明之一實施例中，在一初步的金電鍍之後又會施以Ni/Cu電鍍，俾有助於如下所述的後續電路建立。
第6圖示出該具有被鍍凹穴106的導電片102，其中該光 微影材料104已被剝除。該光微影材料104可被以人力或藉機器除去。
第7圖示出一絕緣膜110已被塗敷於該導電片102和被鍍的凹穴106上。該絕緣膜110可包含一焊罩材料，其係疊覆在該導電片102和被鍍的凹穴106上，然後被熱固化。在固化之後，通道等會被形成於該絕緣膜中且在該等被鍍的凹穴106邊緣處。
第8圖示出該等通道112已被形成於該絕緣膜110中。該等通道112可被使用一雷射來形成，如該技術中所習知。在本發明之一實施例中，該等通道112會延伸穿過該絕緣膜110而靠近於該等被鍍凹穴106的邊緣。在該等通道112形成之後，該等通道112會被鍍以一導電金屬。例如，該等通道可被電鍍金。在本發明之一實施例中，該等通道112會被先鍍以銅，然後再鍍以一Ni/Cu合金。第8圖亦示出一焊劑阻抗膜114已被敷設在該絕緣膜110和被鍍的通道112上。該焊劑阻抗膜114可被覆設在該絕緣膜110上，然後該等通道112會切穿該絕緣膜110和焊劑阻抗膜114。
嗣如第9圖所示，該焊劑阻抗膜114會被處置，即使用一阻罩和光顯像來曝光、顯影及熱固化，如該領域中所習知，以形成開放區域116等。該等開放區域116係被形成於通道112上方，並被定寸成可承接形成於一半導體晶粒背面的凸塊(見第11圖)。一鍍覆製程嗣會進行於該等開放區域116上而以一基底金屬譬如金來鍍覆該等開放區域116。若係使用Ni/Cu鍍覆，則一焊劑覆層亦可在該等鍍覆製程之後 被敷設於該等開放區域上。
第10圖示出一覆晶晶粒118正被附接於現已構建的導電片102上，而使該晶粒118底面的凸塊120等對準並承納於一各自的開放區域116中。該等凸塊120係藉由被鍍的通道112等電連接於該等被鍍的凹穴106。該IC晶粒118可為處理器，譬如數位訊號處理器(DSPs)，微控制器，特殊功能電路比如記憶位址產生器，或可執行任何其它類型之功能的電路等。該等IC晶粒118並不限制於一特別的技術比如CMOS，或由任何特定的晶圓技術所衍生。且，本發明能包容各種不同的晶粒尺寸，如熟習該技術者所瞭解。一典型範例係為一種具有大約6mm×6mm尺寸的快閃記憶裝置。
第11圖示出該導電片102在一包封製程完成後具有二覆晶晶粒118附接其上。即是，包封或成型製程會被進行以形成一塑膠材料122包圍該等晶粒118。包封該等晶粒118的塑膠材料122可包含泛知的商用市售成型材料，比如塑膠或環氧樹脂。當然，兩個以上的晶粒亦可被附接於一所構建的導電片上，而示出的兩個僅為舉例說明。
現請參閱第12圖，該導電片102會被去除(例如背銅去除。該導電片102可藉在一溶液中蝕刻而被除去，該溶液會溶化掉該片導電金屬102來暴露該等凹穴106的鍍覆表面108，其因而會形成端子。在本發明之一實施例中，由該等鍍覆凹穴所形成的端子係為c5凸塊。
最後，一切割製程會被進行來形成個別的封裝式裝置124等。切割可藉鋸切或雷射切割來完成，如該領域中所習 知。本發明能包容各種不同的封裝體尺寸，乃可為精習該技術者所瞭解。
由以上論述顯然可知，本發明係提供使用一覆晶晶粒構成的凸塊晶粒載體型封裝體。本發明可容許封裝體具有周邊的部份陣列和全凸塊陣列佈局。一全陣列可藉重設定該等線路和構積附加的料層來形成。C5凸塊係在該製程的初始被構設，並形成該基材之一整體部份。故，不須有額外的C5焊球附接在該總成背端。因該凸塊式C5焊球係為該整體封裝結構的一部份，故該焊球掉落的問題將會清除。該等凸塊上的絕緣膜110會提供應力釋除，其會在將該封裝的裝置124附接於一印刷電路板之後減少熱循環時直接作用於接點上的應力。此應力釋除可在經由該等C5凸塊電測試時提供機械應力和應變的吸收。
本發明之較佳實施例的描述已被呈現作為舉例和說明，但並非欲予排它地或將本發明限制於所揭的形式。精習於該技術者將可瞭解，各種變化亦可被完成於上述實施例而不超出其廣義的發明概念。因此，應請瞭解本發明並不受限於所揭的特定實施例，而涵蓋各種包含於所附申請專利範圍所界定之本發明的精神和範圍內之修正變化。
10，20‧‧‧封裝的裝置
12，22‧‧‧晶粒
14，26，120‧‧‧凸塊
16‧‧‧導線
18，32，122‧‧‧塑膠材料
24‧‧‧基材
28‧‧‧填充材料
30‧‧‧焊球
102‧‧‧導電材料
104‧‧‧光微影材料
106‧‧‧凹穴
116‧‧‧開放區域
118‧‧‧覆晶晶粒
108‧‧‧導電金屬
110‧‧‧絕緣膜
112‧‧‧通道
114‧‧‧焊劑阻抗膜
124‧‧‧被封裝的裝置
第1圖係為一傳統的凸塊晶片載體型封裝體之放大截面圖；第2圖係為一傳統的覆晶球柵陣列型封裝體之放大截 面圖；及第3-12圖係示出依據本發明一實施例之形成覆晶凸塊載體型封裝裝置的方法之各放大截面圖。
108‧‧‧導電金屬
110‧‧‧絕緣膜
112‧‧‧通道
114‧‧‧焊劑阻抗膜
124‧‧‧被封裝的裝置

Claims (14)

  1. 一種封裝半導體積體電路的方法，包含下列步驟：提供一片金屬箔；在該片金屬箔之一第一表面中形成多數凹穴；以一導電金屬鍍覆該等凹穴；在該金屬箔的第一表面和該等經鍍覆凹穴上形成一絕緣膜；在該絕緣膜中形成多數通道，其中該等通道會接觸該等經鍍覆凹穴之個別一者；以一導電金屬鍍覆該等通道；形成一焊劑阻抗膜於該等絕緣膜和經鍍覆通道上；加工該焊劑阻抗膜，以在該等通道上方形成曝露區域；以一導電金屬鍍覆該等通道上方的該等曝露區域；將一設有凸塊的半導體晶粒附接於該金屬箔的該第一表面，其中該等晶粒凸塊會接觸經鍍覆曝露區域之個別一者，藉以將該晶粒電連接於該等經鍍覆凹穴；及除去該片金屬箔以使該等經鍍覆凹穴的外表面曝露，藉以使該等經鍍覆凹穴外表面形成通至該半導體晶粒的電互接物。
  2. 如申請專利範圍第1項之封裝半導體積體電路的方法，其中該片金屬箔是由銅所構成。
  3. 如申請專利範圍第1項之封裝半導體積體電路的方法，其中在該金屬箔片的該第一表面中形成多數凹穴的步 驟包含：在該金屬箔片的該第一表面上形成一塗層；罩蔽該塗層；及加工該被罩蔽的塗層來形成該等凹穴。
  4. 如申請專利範圍第3項之封裝半導體積體電路的方法，其中在該金屬箔片的該第一表面上形成一塗層的步驟，包含在該箔片之該第一表面上形成一阻抗塗層及疊合一乾膜中之一者。
  5. 如申請專利範圍第4項之封裝半導體積體電路的方法，其中加工該被罩蔽的塗層來形成該等凹穴的步驟，包含蝕刻該箔片的該第一表面。
  6. 如申請專利範圍第1項之封裝半導體積體電路的方法，更包含在該絕緣膜形成於該金屬箔第一表面上之前，除去形成於該金屬箔第一表面上的該塗層之步驟。
  7. 如申請專利範圍第1項之封裝半導體積體電路的方法，其中用以鍍覆該等凹穴的該導電金屬包含金。
  8. 如申請專利範圍第1項之封裝半導體積體電路的方法，其中該絕緣膜包含一焊劑罩。
  9. 如申請專利範圍第8項之封裝半導體積體電路的方法，其中該等通道係以一雷射形成於該焊劑罩中。
  10. 如申請專利範圍第1項之封裝半導體積體電路的方法，其中該等通道係以金鍍覆。
  11. 如申請專利範圍第1項之封裝半導體積體電路的方法，更包含包封該半導體晶粒和該金屬箔之該第一表面的步 驟。
  12. 一種依據申請專利範圍第1項之方法所形成之經封裝的裝置。
  13. 一種形成多數個半導體封裝體的方法，該方法包含下列步驟：提供一片金屬箔；在該片金屬箔之一第一表面中形成多數凹穴；以一導電金屬鍍覆該等凹穴；在該金屬箔的該第一表面和該等經鍍覆凹穴上形成一絕緣膜；在該絕緣膜中形成多數通道，其中該等通道會接觸該等經鍍覆凹穴之個別一者；以一導電金屬鍍覆該等通道；形成一焊劑阻抗膜於該等絕緣膜和經鍍覆通道上；加工該焊劑阻抗膜，以在該等通道上方形成曝露區域；以一導電金屬鍍覆該等通道上方的該等曝露區域；將多數個設有凸塊的半導體晶粒附接於該金屬箔的該第一表面，其中該等晶粒凸塊會接觸經鍍覆曝露區域之個別一者；包封該等半導體晶粒和該金屬箔的該第一表面；除去該片金屬箔，以使該等經鍍覆凹穴的外表面曝露，藉以使該等經鍍覆凹穴外表面形成通至該等半導體晶粒的電互接物；及 進行一切割操作，來分開相鄰之各晶粒，藉以形成個別的半導體封裝體。
  14. 一種依據申請專利範圍第13項之方法所形成之經封裝的半導體電路。
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