CN101383301A - 形成倒装芯片突起载体式封装的方法 - Google Patents

形成倒装芯片突起载体式封装的方法 Download PDF

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CN101383301A
CN101383301A CNA2008100989691A CN200810098969A CN101383301A CN 101383301 A CN101383301 A CN 101383301A CN A2008100989691 A CNA2008100989691 A CN A2008100989691A CN 200810098969 A CN200810098969 A CN 200810098969A CN 101383301 A CN101383301 A CN 101383301A
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hole
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cavities
integrated circuit
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CN101383301B (zh
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卢威耀
叶兴强
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NXP USA Inc
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Abstract

通过提供金属箔片并在片的第一表面中形成腔来形成倒装芯片突起载体式封装。用导电金属镀覆腔以形成外部互连。在金属箔的第一表面和镀覆腔上形成绝缘膜，然后在绝缘膜中形成通孔。通孔接触相应的镀覆腔。然后镀覆通孔，并在绝缘膜和镀覆通孔上形成焊接阻挡膜。处理焊接阻挡膜以在通孔上形成暴露区域，然后用导电金属镀覆该暴露区域。将突起的半导体管芯附装到金属箔的第一表面，其中管芯突起接触相应的镀覆暴露区域，其将管芯电连接到镀覆腔。最后，移除金属箔片使得露出镀覆腔的外表面。如上所述，镀覆腔的外表面形成管芯和印刷电路板之间的电互连。

Description

形成倒装芯片突起载体式封装的方法
技术领域
本发明涉及集成电路(IC)的封装，更具体地涉及形成倒装芯片的突起载体式封装的方法。
背景技术
现代的消费电子装置如蜂窝电话、数字相机和数字音乐播放器正在驱动对于更小集成电路的需求。于是，半导体制造和封装公司正不断缩小封装电子器件的占用面积，并同时增强电路的功能性。减小封装尺寸的一种方法是使用突起管芯并将该管芯面朝下地电连接到衬底或载体。这因为与导线接合技术相比芯片是面朝下或倒装的而称为倒装芯片组件，在导线接合技术中芯片是面朝上的并且导线连接在芯片顶部上的接合垫与芯片底部所附装到的载体之间。尽管倒装芯片技术并不是新的，但其正变得越来越受欢迎。
图1示出一种封装器件10，其中半导体管芯12利用导线16电连接到柱突起14。导线16从管芯12的顶部延伸到柱突起14。塑性材料18覆盖导线和管芯12的顶部以进行保护。图2示出一种封装器件20，其中半导体管芯22利用突起26电连接到载体或衬底24。填充材料28布置在管芯22和载体24之间。焊珠30附装到载体24的相反侧以提供对其它电子器件的电连接。用虚线示出的塑性材料32绕管芯32形成以完成封装20。
封装过程由于如载体、管芯、焊珠和成型化合物(mold compound)的材料的不同成分而可能非常复杂。经常会遇到由过热和紧公差导致的问题。例如，焊珠30有时会脱落或与载体24分离。有利的是提供一种制造可靠的倒装芯片封装器件。
附图说明
在结合附图阅读时将更好地理解下面对本发明优选实施例的详细说明。本发明通过示例示出而不受附图限制，附图中类似的标号指示类似的元件。应该理解附图并不按比例绘制并且为了便于理解而进行了简化。
图1是传统突起芯片载体式封装的放大剖视图；
图2是传统倒装芯片球栅阵列式封装的放大剖视图；以及
图3-12是示出根据本发明一个实施例形成倒装芯片突起载体式封装器件的方法的放大剖视图。
具体实施方式
下面结合附图进行的详细说明是对本发明目前的优选实施例的说明，而非表示可以实现本发明的唯一形式。应该理解到相同或等同的功能可以由包括在本发明的精神和范围内的不同实施例实现。在附图中，类似的标号一直用于指示类似的元件。
本发明提供了一种形成半导体封装的方法，其包括提供金属箔片以及在片的第一表面中形成多个腔的步骤。用导电金属镀覆腔。在金属箔的第一表面和镀覆腔上形成绝缘膜，然后在绝缘膜中切出通孔。通孔接触相应的镀覆腔。接着用导电金属镀覆通孔。在绝缘膜和镀覆通孔上形成焊接阻挡膜，并处理焊接阻挡膜以在通孔上形成暴露区域。然后用导电金属镀覆该暴露区域。将突起的倒装芯片管芯附装到金属箔的第一表面。管芯突起接触相应的镀覆暴露区域，其将管芯电连接到镀覆腔。移除金属箔片，露出镀覆腔的外表面，从而镀覆腔的外表面形成与印刷电路板或外部载体的电互连。
现在将在下面参照图3-12描述一种形成多个倒装芯片突起载体式封装100的方法。
现在参照图3，提供了一条或一片导电材料102。导电材料片102可以是方形、矩形或类似于晶片的圆形，并可以通过例如切割、压印或刻蚀而成形。在一个实施例中，导电材料片102由诸如铜箔的普通金属形成并厚约0.5mm。但是，本发明并不受金属片102的具体材料、尺寸或厚度的限制。
光刻材料104涂覆到导电片102的第一或顶表面并固化。将未示出的光掩模布置在光刻材料上方。如现有技术已知的，光刻材料104可以包括阻挡涂层或干膜叠层。
参照图4，光刻材料104和导电片102被露出并以已知方式显影或者另外处理，以在导电片102的顶表面上形成预定图案。然后刻蚀导电片102。一种已知的刻蚀方法是使用酸浴，在其中刻蚀非叠层或涂覆区域。预定图案包括穿过光刻材料104切入导电片102中的多个腔106。
参照图5，用导电金属108镀覆腔106以形成外部电互连，这将在后面变得清楚。导电材料108可以是诸如金的金属或者由例如钯和镍构成的合金。在本发明的一个实施例中，在初始的金镀层之后涂覆Ni/Cu镀层以有助于下面描述的接着的迹线构建。
图6示出其中光刻材料104已经剥离的带镀覆腔106的导电片102。光刻材料104可以手动或通过机器移除。
图7示出已经涂覆到导电片102和镀覆腔106的绝缘膜110。绝缘膜110可以包括焊接掩模材料，其层叠在导电片102和镀覆腔106上方，然后热固化。在固化后，在镀覆腔106的边缘处在绝缘膜中形成通孔。
图8示出已经在绝缘膜110中形成的通孔112。通孔112可以使用激光器形成，这在现有技术中已知。在本发明的一个实施例中，通孔112靠近镀覆腔106的边缘延伸通过绝缘膜110。在形成通孔112之后，用导电金属镀覆通孔112。例如，可以用金电镀通孔112。在本发明的一个实施例中，通孔112首先用铜镀，然后再用Ni/Cu合金镀。图8还示出已经涂覆到绝缘膜110和镀覆通孔112上的焊接阻挡膜114。焊接阻挡膜114可以形成在绝缘膜110上，然后穿过绝缘膜110和焊接阻挡膜114两者切出通孔112。
接着，如图9所示，如现有技术中已知的，处理焊接阻挡膜114，即使用掩模和光成像来曝光、显影和热固化，以形成敞开区域116。敞开区域116形成在通孔112上，并且尺寸形成为接收形成在半导体管芯(图11)背面上的突起。然后在敞开区域116上执行镀覆工艺以用诸如金的基体金属镀覆敞开区域116。如果使用Ni/Cu镀覆，则还可以在镀覆工艺之后将焊接覆层涂覆到敞开区域。
图10示出附装到现在构建的导电片102的倒装芯片管芯118，使得管芯118的底部上的突起120与相应的敞开区域116对齐并接纳在其中。突起120通过镀覆通孔112电连接到镀覆腔106。IC管芯118可以是诸如数字信号处理器(DSP)的处理器、微控制器、诸如存储器地址产生器的专用功能电路、或者执行任何其它类型功能的电路。IC管芯118并不限于诸如CMOS的具体技术，而可以从任何具体晶片技术得到。另外，本发明可以容许本领域技术人员所理解的各种管芯尺寸。一个典型示例是具有约6mm乘6mm的尺寸的闪存器件。
图11示出在执行了封闭工艺之后其上附装有两个倒装芯片管芯118的导电片102。就是说，执行封闭或成型以绕管芯118形成塑性材料122。封闭管芯118的塑性材料122可以包括公知的商业可获得成型材料，例如塑料或环氧树脂。当然，可以将多于两个的管芯附装到所构建的导电片，示出两个仅仅是为了进行说明。
现在参照图12，移除导电片102(例如背面铜移除)。导电片102可以通过在以下方案中完成的刻蚀来移除，该方案溶解导电金属片102以露出腔106的镀覆表面108，所述腔由此形成端子。在本发明的一个实施例中，由镀覆腔形成的端子是C5突起。
最后，执行切片工艺以形成单独的封装器件124。如现有技术中已知的，可以通过划割单片化(saw singulation)或激光切割来进行切片。本发明可以容许本领域技术人员所理解的各种封装尺寸。
从以上讨论很清楚，本发明提供了使用倒装芯片管芯构造的突起芯片载体式封装。本发明允许具有周边、部分阵列和全突起阵列布局的封装。全阵列可以通过将迹线重布线并构建附加层而形成。C5突起在工艺开始时构建并形成衬底的集成部分。于是，不需要在组件背端附装附加的C5焊珠。由于突起的C5焊珠是整个封装结构的一部分，所以消除了焊珠掉落的问题。突起上的绝缘膜110提供了应力减小部，该应力减小部在将封装器件124附装到印刷电路板之后的热循环期间减小接头上的直接应力冲击。该应力减小部在经由C5突起的电子测试期间提供机械应力和应变吸收。
对本发明优选实施例的描述是为了说明和描述而给出的，而并非穷尽或将本发明限制到所公开的形式。本领域技术人员将认识到可以对上述实施例进行改变，而不偏离其广泛的发明概念。因此，应该理解本发明并不限于所公开的具体实施例，而覆盖在由所附权利要求限定的本发明的精神和范围内的修改。

Claims (14)

1.一种封装半导体集成电路的方法，包括:
提供金属箔片；
在所述金属箔片的第一表面中形成多个腔；
用导电金属镀覆所述腔；
在金属箔的第一表面和镀覆腔上形成绝缘膜；
在所述绝缘膜中形成多个通孔，其中所述通孔接触相应的所述镀覆腔；
用导电金属镀覆所述通孔；
在所述绝缘膜和镀覆通孔上形成焊接阻挡膜；
处理所述焊接阻挡膜以在所述通孔上形成暴露区域；
用导电金属镀覆所述通孔上的暴露区域；
将突起的半导体管芯附装到金属箔的第一表面，其中管芯突起接触相应的镀覆暴露区域，由此将所述管芯电连接到镀覆腔；以及
移除所述金属箔片使得露出镀覆腔的外表面，由此所述镀覆腔的外表面形成与半导体管芯的电互连。
2.根据权利要求1所述的封装半导体集成电路的方法，其中所述金属箔片由铜构成。
3.根据权利要求1所述的封装半导体集成电路的方法，其中在所述金属箔片的第一表面中形成多个腔的步骤包括:
在所述金属箔片的第一表面上形成涂层；
掩模所述涂层；以及
处理所掩模的涂层以形成所述腔。
4.根据权利要求3所述的封装半导体集成电路的方法，其中在所述金属箔片的第一表面上形成涂层的步骤包括在箔片的第一表面上形成阻挡涂层和在箔片的第一表面上层叠干膜这两者中之一。
5.根据权利要求4所述的封装半导体集成电路的方法，其中处理所掩模的涂层以形成所述腔的步骤包括刻蚀箔片的第一表面。
6.根据权利要求1所述的封装半导体集成电路的方法，还包括在金属箔的第一表面上形成所述绝缘膜之前移除在金属箔的第一表面上形成的涂层的步骤。
7.根据权利要求1所述的封装半导体集成电路的方法，其中用于镀覆所述腔的导电材料包括金。
8.根据权利要求1所述的封装半导体集成电路的方法，其中所述绝缘膜包括焊接掩模。
9.根据权利要求8所述的封装半导体集成电路的方法，其中利用激光在所述焊接掩模中形成通孔。
10.根据权利要求1所述的封装半导体集成电路的方法，其中所述通孔用金镀覆。
11.根据权利要求1所述的封装半导体集成电路的方法，还包括封闭半导体管芯、金属箔的第一表面的步骤。
12.根据权利要求1所述的方法形成的封装器件。
13.一种形成多个半导体封装的方法，所述方法包括:
提供金属箔片；
在所述金属箔片的第一表面中形成多个腔；
用导电金属镀覆所述腔；
在金属箔的第一表面和镀覆腔上形成绝缘膜；
在所述绝缘膜中形成多个通孔，其中所述通孔接触相应的所述镀覆腔；
用导电金属镀覆所述通孔；
在所述绝缘膜和镀覆通孔上形成焊接阻挡膜；
处理所述焊接阻挡膜以在所述通孔上形成暴露区域；
用导电金属镀覆所述通孔上的暴露区域；
将多个突起的半导体管芯附装到金属箔的第一表面，其中管芯突起接触相应的镀覆暴露区域；
封闭半导体管芯和金属箔的第一表面；
移除金属箔片使得露出镀覆腔的外表面，由此所述镀覆腔的外表面形成与半导体管芯的电互连；以及
执行单片化操作以分离相邻的管芯，由此形成单独的半导体封装。
14.根据权利要求13所述的方法形成的封装半导体电路。
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