CN1658387A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1658387A
CN1658387A CN2005100093666A CN200510009366A CN1658387A CN 1658387 A CN1658387 A CN 1658387A CN 2005100093666 A CN2005100093666 A CN 2005100093666A CN 200510009366 A CN200510009366 A CN 200510009366A CN 1658387 A CN1658387 A CN 1658387A
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China
Prior art keywords
semiconductor substrate
insulating barrier
pad electrode
hole
semiconductor device
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CN2005100093666A
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CN100382304C (zh
Inventor
龟山工次郎
铃木彰
冈山芳央
梅本光雄
高桥健司
寺尾博
星野雅孝
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Sanyo Electric Co Ltd
Fujitsu Semiconductor Ltd
Kioxia Corp
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Toshiba Corp
Fujitsu Ltd
NEC Corp
Sanyo Electric Co Ltd
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Publication of CN1658387A publication Critical patent/CN1658387A/zh
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Publication of CN100382304C publication Critical patent/CN100382304C/zh
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Abstract

一种半导体装置及其制造方法，提高可靠性。本发明的半导体装置包括：支承板(5)，其粘接在所述半导体衬底(1)的表面上，使其覆盖介由氧化硅膜或氮化硅膜等构成的绝缘层(2)形成在半导体衬底(1)上的焊盘电极(3)；通孔(8)，其从所述半导体衬底(1)的背面到达所述焊盘电极(3)的表面，其中，靠近所述焊盘电极表面的部分的开口直径大于靠近所述半导体衬底(1)背面的部分的开口直径。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及在半导体衬底上形成通孔的技术。
背景技术
近年来，作为三维安装技术，或新的封装技术，CSP(芯片尺寸封装)正在受到人们的注目。所谓CSP是具有与半导体芯片的外形尺寸大致相同外形尺寸的小型封装件。
目前，作为CSP之一种，可知有BGA型半导体装置。该BGA型半导体装置中，在封装件的一主面上格子状排列多个由焊锡等金属部件构成的球状导电端子，使其与搭载于封装件其它面上的半导体芯片电连接。
而且，在将该BGA型半导体装置装入电子设备内时，通过在印刷线路板上的配线图案上安装各导电端子，将半导体芯片和搭载在印刷线路板上的外部电路电连接。
这种BGA型半导体装置与侧部具有突出的引脚的SOP(Small OutinePackage)或QFP(Quad Flat Packagae)等其它CSP型半导体装置相比，具有可设置多个导电端子并可小型化的优点。该BGA型半导体装置具有作为例如搭载于手机上的数码相机的图像传感器芯片的用途。
图9是现有BGA型半导体装置的概略结构图，图9(A)是该BGA型半导体装置表面侧的立体图。图9(B)是该BGA型半导体装置背面侧的立体图。
该BGA型半导体装置101中，在第一及第二玻璃衬底102、103之间介由环氧树脂105a、105b密封有半导体芯片104。在第二玻璃衬底103的一主面上，即BGA型半导体装置101的背面上格子状配置多个导电端子106。该导电端子106介由第二配线110与半导体芯片104连接。在多个第二配线110上分别连接从半导体芯片104内部引出的铝配线，将各导电端子106和半导体芯片104电连接。
参照图10进一步详细说明该BGA型半导体装置101的剖面结构。图10是沿切割线分割成一各各芯片的BGA型半导体装置101的剖面图。
在配置于半导体芯片104表面上的绝缘层108上设有第一配线层107。该半导体芯片104利用树脂层105a与第一玻璃衬底102粘接。另外，该半导体芯片104的背面利用树脂层105b与第二玻璃衬底103粘接。
而且，第一配线107的一端与第二配线110连接。该第二配线110从第一配线107的一端延伸到第二玻璃衬底103的表面。在延伸到第二玻璃衬底103上的第二配线110上形成有球状的导电端子106。
上述技术记载于例如以下的专利文献1中。
专利文献1：特表2002-512436号公报
但是，在上述半导体装置101中，由于第一配线107和第二配线110的接触面积非常小，故可能在该接触部分产生断线。另外，在第二配线110的分步敷层中也有问题。因此，本发明提供一种半导体装置及其制造方法，以提高可靠性。
发明内容
本发明的第一方面提供一种半导体装置，其包括：支承体，其粘接在所述半导体衬底的表面上，覆盖介由绝缘层形成于半导体衬底上的焊盘电极；通孔，其从所述半导体衬底的背面到达所述焊盘电极的表面而形成，其中，靠近所述焊盘电极表面的部分的开口直径大于靠近所述半导体衬底背面的部分的开口直径。
本发明的第二方面在第一方面的基础上提供一种半导体装置，在所述通孔的侧壁形成绝缘层或金属层。
本发明的第三方面提供一种半导体装置的制造方法，其包括：将支承体粘接在所述半导体衬底的表面，使其覆盖介由绝缘层形成于半导体衬底上的焊盘电极的工序；形成通孔，使其从所述半导体衬底的背面到达所述焊盘电极表面的工序，其中，形成所述通孔的工序包括：相对于所述半导体衬底直至不露出所述绝缘层的位置形成第一开口的工序；相对于所述半导体衬底形成具有比所述第一开口的开口直径大的开口直径的第二开口，直至露出所述绝缘层的位置。
本发明的第四方面在第三方面的基础上提供一种半导体装置的制造方法，其具有蚀刻从所述开口露出的所述绝缘层，形成使所述焊盘电极露出的通孔的工序。
本发明的第五方面在第三、第四方面的基础上提供一种半导体装置的制造方法，其具有在所述通孔的侧壁形成绝缘层的工序和在所述绝缘层上形成金属层的工序。
根据本发明，由于介由通孔形成从半导体芯片的焊盘电极直至其导电端子的配线，故可防止所述配线的断线或分布敷层的劣化。由此，可得到可靠性高的半导体装置。
根据本发明，在具有从半导体衬底背面达到焊盘电极表面这样形成的通孔的半导体装置中，通过形成靠近所述焊盘电极表面的部分的开口直径比靠近所述半导体衬底背面的部分的开口直径大的通孔，所述通孔侧壁形成的绝缘层或金属层粘附在该开口直径变大的部分，形成不易从半导体衬底剥离的结构，提高焊盘电极和金属层的电及机械的接合性。
另外，通过扩大形成在焊盘电极表面上的通孔的开口直径，即使其后填充金属层，也可以缓和应力。
附图说明
图1是本发明实施例的半导体装置制造方法的剖面图；
图2是本发明实施例的半导体装置制造方法的剖面图；
图3是本发明实施例的半导体装置制造方法的剖面图；
图4是本发明实施例的半导体装置制造方法的剖面图；
图5是本发明实施例的半导体装置制造方法的剖面图；
图6是本发明实施例的半导体装置制造方法的剖面图；
图7是本发明实施例的半导体装置制造方法的剖面图；
图8是现有半导体装置的剖面图；
图9(A)、(B)是现有半导体装置的立体图；
图10是现有半导体装置的剖面图。
符号说明
1  半导体衬底
2  绝缘层
3  焊盘电极
7  第一开口
8  通孔
9、9A  绝缘层
10  阻挡膜
11  籽晶层
12  再配线层
13  球状端子
具体实施方式
其次，参照图1～图8说明本发明的半导体装置及其制造方法。图1～图8是可应用于图像传感器芯片的半导体装置及其制造方法的剖面图。
首先，如图1所示，在半导体衬底1的表面介由例如氧化硅膜或氮化硅膜等绝缘层2形成由铝层或铝合金层构成的焊盘电极3。然后，在包括焊盘电极3的半导体衬底1上介由由环氧树脂层构成粘接剂4粘接例如由玻璃构成的支承板5。另外，也可以在半导体衬底1上粘接带状保护材料以取代支承板5，也可以使用两面粘接带等作为支承材料。
其次，如图2所示，在对应焊盘电极3的半导体衬底1的背面形成具有开口部的抗蚀剂层6，并以该抗蚀剂层为掩模对半导体衬底1进行干蚀刻，形成从半导体衬底1的背面到达焊盘电极3上的绝缘层2的第一开口7。在该蚀刻工序中，使用至少含有SF6、O2或C4F8等的蚀刻气体蚀刻由Si构成的半导体衬底1。此时，当在绝缘层2上进行半导体衬底1的超量蚀刻时，形成桶状的横向扩大的第一开口7，其靠近焊盘电极3的部分的开口直径大于靠近半导体衬底1背面的部分的开口直径。
然后，如图3所示，以所述抗蚀剂层6为掩模，蚀刻除去所述焊盘电极3上的绝缘层2，形成使焊盘电极3露出的通孔8。该绝缘层2的蚀刻工序使用例如在CHF3、CF4等CF系气体中添加了氩气等稀释气体的蚀刻气体进行。此时，即使所述第一开口7的底部大，也可以使所述抗蚀剂层6或开口7的上部侧壁形成掩模，绝缘层2用的蚀刻气体难于向横向扩散，所以，所述焊盘电极3上的绝缘层2的开口直径K3形成为与通孔8上部的开口直径大致相同的开口直径。另外，也可以是不以所述抗蚀剂层6为掩模的蚀刻工序，在这种情况下，是在除去抗蚀剂层6后，以半导体衬底1为掩模，除去焊盘电极3上的绝缘层2。
以下，如图4所示，在包括通孔8内的半导体衬底1的背面形成由氧化硅膜或氮化硅膜等构成的绝缘层9，如图5所示，在除去焊盘电极3上的绝缘层9，形成绝缘层9A后，如图6所示，在包括通孔8内的半导体衬底1的背面形成阻挡层10。该阻挡层10优选使用例如氮化钛(TiN)层，另外，只要是钛(Ti)、钽(Ta)等高熔点金属或其化合物即钨化钛(TiW)层、氮化钽(TaN)层等，则也可以由除氮化钛层之外的金属构成。
另外，在形成所述绝缘层9A的工序中，也可以在包括所述通孔8内的半导体衬底1上形成绝缘层9后，在所述半导体衬底1上形成抗蚀剂层(未图示)，然后，以该抗蚀剂层为掩模，除去所述焊盘电极3上的绝缘层9，另外，也可以是不以所述抗蚀剂层为掩模的蚀刻工序。
另外，在不以该抗蚀剂层为掩模进行蚀刻时，利用了绝缘层9向通孔8上的被覆性。即，在图4中，为了方便图示，将在通孔8上形成的绝缘层9的膜厚均一化，但实际上形成的绝缘层9的膜厚具有通孔8底部的绝缘层9不如形成在半导体衬底1上的绝缘层9的膜厚厚的被覆性，举例如下，半导体衬底1上的绝缘层9的膜厚有时会达到通孔8底部的绝缘层9的膜厚的两倍。因此，通过利用该特性，即使不在半导体衬底1上形成抗蚀剂层，也可以在完全除去半导体衬底1上的绝缘层9之前完全除去焊盘电极3上的绝缘层9。
此时，优选使用在通孔8上形成的绝缘层9的蚀刻特性。即，具有与在所述半导体衬底1上形成的绝缘层9的蚀刻速率相比，在通孔8底部形成的绝缘层9的蚀刻速率低这种特性，举例如下，甚至有时半导体衬底1上的绝缘层9的蚀刻速率比通孔8底部的绝缘层9的蚀刻速率高1.5倍。因此，通过使用所述的绝缘层9的被覆性和绝缘层9的蚀刻特性两方面，提高制造工序的可靠性。
如图7所示，在阻挡层10上形成镀敷用籽晶层11(例如Cu层)，并在该籽晶层11上进行镀敷处理，形成例如由铜(Cu)构成的再配线层12。其结果是，再配线层12与焊盘电极3电连接，且介由通孔8向半导体衬底1的背面延伸。另外，该再配线层12可以构图，也可以不构图。进而在再配线层12上形成保护层(未图示)，并在保护层的规定位置设置开口，形成与再配线层12接触的球状端子13。
在此，所述阻挡层10或籽晶层11的形成方法可使用MOCVD法，但这种情况下存在成本升高的问题。因此，通过使用比MOCVD法成本低的长时间慢速喷溅法(ロングスロ一スパッタ法)等指向性喷溅法，与通常的喷溅法相比可使被覆性提高。通过使用该指向性喷溅法，即使对例如倾斜角度小于90度或长宽比为三以上的通孔也具有良好的被覆性，可形成所述阻挡层10或籽晶层11。
然后，虽未图示，但切断半导体衬底及层积在该半导体衬底上的上述各层，分离成一各各半导体芯片。这样，形成焊盘电极3和球状端子13电连接的BGA型半导体装置。
这样，在本发明中，利用在开口底部向横向的蚀刻形成的凹槽形状，形成在所述通孔8侧壁的绝缘层9A或阻挡层10、籽晶层11、再配线层12就在该开口直径大的部分粘附，形成难以从半导体衬底1剥离的结构。也就是由铝或铝合金层构成的焊盘电极3和由Cu构成的籽晶层11、再配线层12等的接合性提高。
通过扩大形成在焊盘电极3表面上的通孔8的开口直径，即使之后填充籽晶层11、再配线层12等，也可以使应力缓和，提高可靠性。
另外，如图8所示，当通孔侧壁为平直型，或形成正锥形或底部形成褶状时，在通孔的侧壁形成绝缘层9A，在蚀刻除去通孔底部的绝缘层时，存在被覆于通孔底部倾斜部分的绝缘层被蚀刻除去(图8的A部分)、该部分的绝缘性降低的情况，但使用本发明的通孔形状，不存在这种蚀刻消除，可抑制短路缺陷。
根据本发明，由于介由通孔形成从半导体芯片的焊盘电极直至其导电端子的配线，故可防止所述配线的断线或分布敷层时的劣化。由此，可得到可靠性高的BGA型半导体装置。
另外，在本实施例中，再配线层12是利用镀敷处理形成的，但本发明不限于此，例如也可以不形成镀敷用籽晶层11，利用除镀敷处理之外的方法形成再配线层12。例如，也可以喷溅形成由铝或其合金构成的层。
本实施例中说明了适用于形成有球状端子13的半导体装置的情况，但本发明不限于此，例如只要是形成有贯通半导体衬底的通孔的半导体装置，则也可以适用于不形成球状端子的半导体装置，例如也可以适用于LGA(Land Grid Array)型半导体装置。

Claims (9)

1、一种半导体装置，其包括：支承体，其粘接在所述半导体衬底的表面上，覆盖介由绝缘层形成于半导体衬底上的焊盘电极；通孔，其从所述半导体衬底的背面到达所述焊盘电极的表面而形成，其特征在于，靠近所述焊盘电极表面的部分的开口直径大于靠近所述半导体衬底背面的部分的开口直径。
2、如权利要求1所述的半导体装置，其特征在于，在所述通孔的侧壁形成有绝缘层或金属层。
3、一种半导体装置的制造方法，其包括：将支承体粘接在所述半导体衬底的表面，使其覆盖介由绝缘层形成于半导体衬底上的焊盘电极的工序；形成通孔，使其从所述半导体衬底的背面到达所述焊盘电极表面的工序，其特征在于，形成所述通孔的工序包括：相对于所述半导体衬底直至不露出所述绝缘层的位置形成第一开口的工序；相对于所述半导体衬底形成具有比所述第一开口的开口直径大的开口直径的第二开口，直至露出所述绝缘层的位置。
4、如权利要求3所述的半导体装置的制造方法，其特征在于，形成所述通孔的工序包括蚀刻从所述第二开口露出的所述绝缘层，从而使所述焊盘电极露出的工序。
5、如权利要求3、4的任意一项所述的半导体装置的制造方法，具有在所述通孔的侧壁形成绝缘层的工序和在所述绝缘层上形成金属层的工序。
6、如权利要求5所述的半导体装置的制造方法，其特征在于，在所述通孔的侧壁形成绝缘层的工序是如下工序，在包括通孔的半导体衬底上形成绝缘层后，以形成于所述半导体衬底上的抗蚀剂层为掩模，除去所述焊盘电极上的绝缘层。
7、如权利要求6所述的半导体装置的制造方法，其特征在于，除去所述焊盘电极上的绝缘层的工序是不使用以所述抗蚀剂层为掩模的蚀刻工序。
8、如权利要求5所述的半导体装置的制造方法，其特征在于，包括形成连接于所述金属层上的球状端子的工序。
9、如权利要求3、4、5、6、7、8任一项所述的半导体装置的制造方法，其特征在于，包括将所述半导体衬底分割成多个半导体芯片的工序。
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