US20070045120A1 - Methods and apparatus for filling features in microfeature workpieces - Google Patents

Methods and apparatus for filling features in microfeature workpieces Download PDF

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Publication number
US20070045120A1
US20070045120A1 US11217891 US21789105A US2007045120A1 US 20070045120 A1 US20070045120 A1 US 20070045120A1 US 11217891 US11217891 US 11217891 US 21789105 A US21789105 A US 21789105A US 2007045120 A1 US2007045120 A1 US 2007045120A1
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Prior art keywords
plating
workpiece
layer
species
features
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Abandoned
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US11217891
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Chandra Tiwari
Whonchee Lee
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Micron Technology Inc
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Micron Technology Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/008Current insulating devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/07Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process being removed electrolytically
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material

Abstract

Methods and apparatus for filling features on microfeature workpieces. One embodiment of a method for filling features on a microfeature workpiece comprises contacting a surface of the microfeature workpiece with a plating solution having a plating species and an accelerator, and electrochemically depositing the plating species onto the workpiece until the plating species at least substantially fills first depressions on the workpiece. The electrochemical species forms a plated layer on the workpiece, and this method further includes changing the concentration of the accelerator on a surface of the plated layer at locations aligned with the first depressions. The method continues by electroplating more of the plating species onto the workpiece after changing the concentration of the accelerator on the plated layer to further deposit the plating species into a second depression on the microfeature workpiece that is larger than the first depression.

Description

    TECHNICAL FIELD
  • [0001]
    The present invention is directed toward methods and apparatus for filling features in microfeature workpieces. For example, many embodiments of such methods and apparatus fill different features that have different critical dimensions in a manner that improves the ability to subsequently process the workpiece.
  • BACKGROUND
  • [0002]
    Microelectronic devices, such as semiconductor devices, imagers, and displays, are generally fabricated on and/or in microelectronic workpieces using several different types of machines (“tools”). Many such processing machines have a single processing station that performs one or more procedures on the workpieces. Other processing machines have a plurality of processing stations that perform a series of different procedures on individual workpieces or batches of workpieces. In a typical fabrication process, one or more layers of conductive materials are formed on the workpieces during deposition stages. The workpieces are then typically subject to etching and/or polishing procedures (i.e., planarization) to remove a portion of the deposited conductive layers for forming electrically isolated contacts and/or conductive lines.
  • [0003]
    Tools that plate metals or other materials on the workpieces are becoming an increasingly useful type of tool. Electroplating and electroless plating techniques can be used to deposit copper, solder, permalloy, gold, silver, platinum, electrophoretic resist, and other materials onto workpieces for forming blanket layers or patterned layers. A typical copper plating process involves depositing a copper seed layer onto the surface of the workpiece using chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating processes, or other suitable methods. After forming the seed layer, a blanket layer or patterned layer of copper is plated onto the workpiece by applying an appropriate electrical potential between the seed layer and an anode in the presence of an electroprocessing solution. The workpiece is then cleaned, etched, and/or annealed in subsequent procedures before transferring the workpiece to another processing machine.
  • [0004]
    Electroplating tools can have a single-wafer processing station that includes a container for receiving a flow of electroplating solution from a fluid inlet at a lower portion of the container. The processing station can include an anode, a plate-type diffuser having a plurality of apertures, and a workpiece holder for carrying a workpiece. The workpiece holder can include a plurality of electrical contacts for providing electrical current to a seed layer on the surface of the workpiece. When the seed layer is biased with a negative potential relative to the anode, it acts as a cathode. In operation, the electroplating fluid flows around the anode, through the apertures in the diffuser, and against the plating surface of the workpiece. The electroplating solution is an electrolyte that conducts electrical current between the anode and the cathodic seed layer on the surface of the workpiece. Therefore, ions in the electroplating solution plate onto the workpiece.
  • [0005]
    The plating machines used in fabricating microelectronic devices must meet many specific performance criteria. For example, many plating processes must be able to form small contacts in vias or trenches that are less than 0.5 μm wide, and often less than 0.1 μm wide. A combination of organic additives such as “accelerators,” “suppressors,” and “levelers” are often added to the electroplating solution to promote bottom-up plating in the trenches. Accelerators, more specifically, cause higher plating rates in the bottom of a trench than along the sides of the trench to avoid pinching off the opening and forming voids in the trench.
  • [0006]
    One drawback of conventional plating processes is that the finished layer may have bumps or other raised features on the plated layer directly over the trenches. These bumps can make it more difficult to planarize the workpiece because more time is required to remove the excess material plated over the trenches, and the additional height of the bumps may adversely affect the final surface of the workpiece. Moreover, the bumps also cause more consumables to be used in the planarizing process. The use of accelerators, therefore, may adversely affect the throughput, product quality, and operating costs of subsequent planarizing processes.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIGS. 1A-1E are schematic side cross-sectional views illustrating stages of filling first and second features on a workpiece.
  • [0008]
    FIG. 2 is a flow chart illustrating a method in accordance with an embodiment of the invention.
  • [0009]
    FIGS. 3A-3D are schematic side cross-sectional views illustrating stages of filling features on microfeature workpieces in accordance with an embodiment of the invention.
  • [0010]
    FIG. 4 is a schematic side cross-sectional view of a stage of a method in accordance with another embodiment of the invention.
  • [0011]
    FIG. 5 is a schematic side cross-sectional view illustrating a plating machine for filling features on microfeature workpieces in accordance with an embodiment of the invention.
  • DETAILED DESCRIPTION
  • [0000]
    A. Overview
  • [0012]
    The present invention is directed toward methods and apparatus for filling features on microfeature workpieces. One aspect related to the invention is that plating processes tend to form bumps directly above trenches or other small depressions in the workpiece. Referring to FIG. 1A, microfeature devices are often formed on a workpiece 10 that has a plurality of first features 12 with a first size and at least one second feature 14 with a second size larger than the first size. The first features 12 can be trenches for forming damascene lines, vias for forming plugs or interconnects in the workpiece 10, or other depressions in the workpiece 10. The first features 12 are typically formed in the array regions of the workpiece 10 and have relatively small critical dimensions. The second feature 14 can be a trench, void, alignment mark, or another depression on the workpiece 10 that has a significantly larger opening or dimension than the first features 12. The second feature 14 can be located in the array region with the first features 12, but in many applications the second feature 14 is located in a peripheral region of a die. The first features 12 and the second feature 14, therefore, are not necessarily adjacent to each other as shown in the figures.
  • [0013]
    FIGS. 1B-1E illustrate the problems of plating processes that are resolved by several embodiments of the methods and apparatus in accordance with the invention. Referring to FIG. 1B, a typical plating process initially deposits a conformal layer 16 onto the workpiece 10 such that the conformal layer 16 lines the first features 12 and the second feature 14. FIG. 1C illustrates a subsequent stage of the plating process in which additional material has been plated onto the workpiece 10 so that the layer 16 fills the first features 12 but does not completely fill the second feature 14. Although the plating process could terminate at the stage illustrated in FIG. 1C, it is difficult to planarize the workpiece 10 at this point because planarizing pads tend to “dish” in the region of the second feature 14. As such, many plating processes continue to deposit additional material until the second feature 14 is completely filled.
  • [0014]
    FIGS. 1D and 1E illustrate subsequent stages in which the second feature 14 is filled with the material. FIG. 1D illustrates a subsequent stage in which bumps 17 or other projections grow directly above the first features 12 as additional material is deposited onto the workpiece 10. As more material is deposited onto the workpiece 10 to fill the second feature 14, the bumps 17 continue to grow. Referring to FIG. 1E, for example, the bumps 17 tend to grow at an accelerated rate until the layer 16 completely fills the second feature 14.
  • [0015]
    Several embodiments of methods and apparatus for filling features on microfeature workpieces in accordance with the invention at least mitigate the size of projections aligned with trenches or other types of depressions on a workpiece. The inventors discovered that non-uniform accumulations of accelerators on the plated surface typically cause more material to be deposited in direct alignment with the first features 12 than on other areas of the workpiece 10. Referring to FIG. 1B, the surface area of the portion of the layer 16 within the first features 12 is significantly larger than the area of the opening at the top of the first features 12. As the material continually deposits onto the workpiece 10, the surface area of the deposited layer 16 within the first features 12 continually decreases until it is flat or at least substantially flat as shown by the areas 18 in FIG. 1C. The inventors believe that this causes higher concentrations of the accelerator to accumulate over the first features 12 compared to other areas on the workpiece 10. The higher concentration of the accelerator over the first features 12 accordingly promotes faster deposition rates at these areas compared to other areas across the workpiece 10. As explained in more detail below, several embodiments of the methods and apparatus for filling features on microfeature workpieces eliminate or at least mitigate this problem to produce workpieces 10 that are better suited for planarization or other processes after the features have been filled.
  • [0016]
    One embodiment of a method for filling features on microfeature workpieces in accordance with the invention comprises contacting a surface of a microfeature workpiece with a plating solution that includes a plating species and an accelerator for enhancing deposition of the plating species in depressions on the workpiece. This method continues by filling first depressions on the workpiece via electrochemically depositing the plating species onto the workpiece to form a first portion of a plated layer that at least substantially fills the first depressions on the workpiece. The embodiment of this method further includes reducing a concentration of the accelerator on a surface of the plated layer after the plated layer at least substantially fills the first depressions, and then electroplating more of the plating species onto the workpiece after reducing the concentration of the accelerator on the surface of the plated layer.
  • [0017]
    Another embodiment of a method for filling features on microfeature workpieces is directed toward workpieces having first features with a first dimension and second features with a second dimension greater than the first dimension. In this embodiment, the method comprises contacting a surface of a microfeature workpiece with a plating solution having a plating species and an accelerator, and electrochemically depositing the plating species onto the workpiece to form a layer that at least substantially occupies the first features of the workpiece. This method further includes removing accumulations of the accelerator from a surface of the layer, and subsequently electroplating more of the plating species onto the workpiece after removing the accumulations of the accelerator to bulk plate the plating species into the second features.
  • [0018]
    Another embodiment of a method for filling features on a microfeature workpiece comprises contacting a surface of the microfeature workpiece with a plating solution having a plating species and an accelerator, and electrochemically depositing the plating species onto the workpiece until the plating species at least substantially fills first depressions on the workpiece. The electrochemical species forms a plated layer on the workpiece, and this method further includes changing the concentration of the accelerator on a surface of the plated layer at locations aligned with the first depressions. The method continues by electroplating more of the plating species onto the workpiece after changing the concentration of the accelerator on the plated layer to further deposit the plating species into a second depression on the microfeature workpiece that is larger than the first depression.
  • [0019]
    Still another embodiment of a method for filling features on microfeature workpieces in accordance with the invention includes contacting a surface of the microfeature workpieces with a plating solution having a plating species and an accelerator, and electrochemically depositing the plating species onto the workpiece until the plating species fills first depressions on the workpiece to form a plated layer on the workpiece. In this embodiment, the method further includes electrochemically removing (a) accumulations of the accelerator from a surface of the plated layer and (b) a portion of the plated layer to produce a restored surface on the plated layer. This method can further include electroplating more of the plating species onto the restored surface of the plated layer to increase the thickness of the plated layer.
  • [0020]
    Another aspect of the invention is directed toward systems for filling features on microfeature workpieces having first features with a first size and a second feature with a second size greater than the first size. One embodiment of such a system comprises a workpiece holder having electrical contacts configured to contact a surface of the workpiece, a plating vessel configured to contain a plating solution, a counter electrode in the plating vessel, and a power source coupled to the electrical contacts and the counter electrode to establish an electrical field through the plating solution in the plating vessel for electrochemically processing the workpiece. The system can further include a controller coupled to the power source. The controller can include a computer-operable medium that contains instructions which cause the power source to (a) electrochemically deposit a plating species in the plating solution onto the workpiece until the plating species at least substantially fills the first features, (b) change the concentration of the accelerator on a surface of a plated layer at locations aligned with the first features, and (c) electroplate more of the plating species onto the workpiece after changing the concentration of the accelerator on the plated layer.
  • [0021]
    FIGS. 2A-5 illustrate several methods and apparatus for filling features on microfeature workpieces in accordance with embodiments of the invention. Several specific details of the invention are set forth in the following description and in FIGS. 2A-5 to provide a thorough understanding of certain embodiments of the invention. One skilled in the art, however, will understand that the present invention may have additional embodiments, or that other embodiments of the invention may be practiced without several of the specific features explained in the following description. The term “microfeature workpiece” is used throughout to include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, and other features are fabricated. For example, microfeature workpieces can be semiconductor wafers, glass substrates, dielectric substrates, or many other types of substrates. Microfeature workpieces generally have at least several features with critical dimensions less than or equal to 1 μm, and in many applications the critical dimensions of the smaller features on microfeature workpieces are less than 0.25 μm or even less than 0.1 μm. Furthermore, the terms “planarization” and “planarizing” mean forming a planar surface, forming a smooth surface (e.g., “polishing”), or otherwise removing materials from workpieces. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from other items in reference to a list of at least two items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or types of other features and components are not precluded.
  • [0000]
    B. Embodiments of Methods for Filling Features on Microfeature Workpieces
  • [0022]
    FIG. 2 is a flow chart illustrating a method 200 for filling features on microfeature workpieces in accordance with an embodiment of the invention. The method 200 includes a preliminary stage 210 in which a surface of a microfeature workpiece is contacted with a plating solution that includes a plating species and an accelerator for enhancing deposition of the plating species into depressions or other features on the workpiece. The workpiece can be similar to the workpiece 10 shown in FIG. 1A, and thus the workpiece can include first depressions having a first size and a second depression having a second size greater than the first size. The method 200 continues with a first plating stage 220 that includes at least partially filling the first depressions on the workpiece with the plating species by electrochemically depositing the plating species onto the workpiece to form a plated layer. The electrochemical process can be an electroless procedure and/or an electroplating procedure that deposits the plating species onto the workpiece. The first plating stage 220 generally plates the plating species onto the workpiece until the plated layer completely fills, or at least substantially fills, the first depressions.
  • [0023]
    The method 200 further includes a reconditioning stage 230 that includes changing the concentration of the accelerator or other additive on a surface of the plated layer after the first plating stage 220. As explained in more detail below, the reconditioning stage 230 can be accomplished by removing the accelerator from the plated layer or otherwise changing the concentration of the accelerator on the surface of the plated layer. The method 200 further includes a second plating stage 240 that comprises electroplating more of the plating species onto the workpiece after the reconditioning stage 230. The second plating stage 240 can comprise further filling the second depressions on the workpiece with additional material. FIGS. 3A-3E illustrate various embodiments of the stages 210-240 in further detail.
  • [0024]
    FIG. 3A illustrates the workpiece 10 being processed in accordance with an embodiment of the preliminary stage 210 of the method 200 illustrated in FIG. 2. At this stage, the workpiece 10 is placed in contact with a plating solution 310 that includes the plating species for plating a layer onto the workpiece and an accelerator for promoting deposition of the plating species in the closed ends 13 of the first features 12. The plating solution 310 can also include levelers, brighteners, suppressors, and/or other additives for controlling the deposition of the plating species. The plating species are generally metal ions, suitable electrophoretic photoresist materials, or other materials that can be plated onto the workpiece 10 using electroless plating and/or electroplating processes. In the embodiment illustrated in FIG. 3A, the workpiece 10 is coupled to a power supply 320 to define a working electrode, and a counter electrode 330 is also coupled to the power supply 320. When electroplating metals onto the workpiece 10, the workpiece 10 is a cathode biased at a negative potential and the counter electrode 330 is an anode biased at a positive potential to plate metal ions onto the workpiece 10. When electroplating electrophoretic photoresist materials, the workpiece 10 is typically an anode biased at a positive potential and the counter electrode 330 is typically a cathode biased at a negative potential to plate negatively charged electrophoretic resist molecules onto the workpiece 10. In either situation, the bias that plates the plating species onto the workpiece 10 is a forward bias or forward potential, and the bias that de-plates the plating species from the workpiece 10 is a reverse bias or reverse potential.
  • [0025]
    FIG. 3B illustrates an embodiment of the first plating stage 220 of the method 200 illustrated in FIG. 2. In this particular embodiment, the plating species has been electroplated onto the workpiece 10 to form the layer 16 and partially fill the first features 12. The layer 16 is a conformal layer that follows the topography of the workpiece 10 at this point in the method 200. The accelerator in the plating solution 310 causes the plating rate to be higher in the closed ends 13 of the first features 12 than at an exterior 19 of the workpiece 10. The first features 12 accordingly fill in a “bottom-up” manner to prevent producing voids within the first features 12. The first features 12 also fill up faster than the second feature 14 even when the depth of the first features 12 is the same as the second feature 14. The first plating stage 220 can use a continuous forward plating process in which the workpiece is a cathode and the counter electrode 330 is an anode. The first plating stage 220 can also use a pulsed plating process including only forward biased pulses and/or a combination of forward- and reverse-biased pulses.
  • [0026]
    FIG. 3C illustrates the workpiece 10 at the end of the first plating stage 220 and during the reconditioning stage 230 of the method 200 illustrated in FIG. 2. At the end of the first plating stage 220, the layer 16 at least substantially fills the first features 12, but the layer 16 does not need to substantially fill the second feature 14. In the particular embodiment illustrated in FIG. 3C, the plated layer 16 completely fills the first features 12, but not the second feature 14. The first plating stage 220 is terminated to form a surface 26 a on the layer 16. As explained above, there is typically a non-uniform distribution of the accelerator on the surface 26 a. The areas 18 in direct alignment with the first features 12, for example, can have a higher concentration of the accelerator than other areas of the surface 26 a. The reconditioning stage 230 is then executed to reduce or otherwise change the concentration of the accelerator on the layer 16. One particular embodiment of the reconditioning stage 230 includes removing the accumulations of the accelerator from the layer 16 by de-plating a portion of the layer 16. For example, when the layer 16 is formed by an electroplating process in which the workpiece 10 is a cathode as shown in FIG. 3B, the accelerator can be removed from the layer 16 by applying a reverse bias so that the workpiece 10 is an anode and the counter electrode 330 is a cathode. This removes additives that have accumulated on the surface 26 a and some of the layer 16 to form a restored or reconditioned surface 26 b on the layer 16. It is expected that the reconditioned surface 26 b is substantially free of any accelerators such that the distribution of the accelerator should be substantially constant across the layer 16 after the reconditioning stage 230.
  • [0027]
    In one embodiment of the reconditioning stage 230 of the method 200, the reverse bias is applied to the workpiece 10 for a period of time sufficient to de-plate approximately 1-100 angstroms of the layer 16. Several embodiments can de-plate more or less than this amount, such as removing only 2-5 angstroms of the layer 16 using a reverse bias for a short period of time (e.g., 100 milliseconds) or even up to 100 angstroms of material by applying the reverse bias for a longer period of time (e.g., 1-3 seconds). The reverse bias for changing the concentration of the accelerator on the layer 16 can be achieved by modifying typical reverse pulsed plating processes such that the reverse bias is applied for a significantly longer period of time (e.g., 4-10 times longer than a typical reverse pulse) and reducing the amp-minutes from approximately 7 amp-minutes to approximately 0.001 amp-minute.
  • [0028]
    FIG. 3D illustrates an embodiment of the second plating stage 240 of the method 200 illustrated in FIG. 2 in accordance with the invention. The second plating stage 240 includes bulk plating additional material from the plating solution 310 to the layer 16 until a finished surface 26 c is formed at a desired thickness. In the embodiment shown in FIG. 3D, the plating species is bulk plated onto the workpiece 10 by applying a forward bias between the workpiece 10 and the counter electrode 330. The bulk plating process can continue until the layer 16 at least approximately fills the second feature 14 to mitigate dishing over the second feature 14 during subsequent chemical-mechanical planarization of the workpiece 10.
  • [0029]
    As illustrated in FIG. 3D, the finished surface 26 c does not have bumps or projections directly aligned with the first features 12. This result is achieved because the reconditioning stage cleans the surface of the layer 16 so that the distributions of the accelerators, suppressors, and/or levelers is more uniform. The concentrations of these additives are expected to be at least substantially the same in the array areas and the periphery areas, and thus the plating rate in the second plating stage 240 is expected to be substantially the same across the workpiece 10. As a result, the second plating stage 240 should not form bumps or projections in alignment with the first features 12.
  • [0030]
    FIG. 4 is a schematic side cross-sectional view of the workpiece 10 illustrating another embodiment of the first plating stage 220 and reconditioning stage 230 of the method 200 illustrated in FIG. 2. In this embodiment, the first plating stage 220 includes terminating the electrochemical deposition of the plating species before the layer 16 completely fills the first features 12. At this point, the reconditioning stage 230 (FIG. 2) can be executed by reducing or otherwise changing the concentration of the accelerator and other additives that have adsorbed onto the surface of the workpiece 10. The reconditioning stage 230 of this embodiment can include de-plating a portion of the layer 16 in situ as described above with reference to FIG. 3C. After the concentration of the accelerator and/or other additives has been changed to recondition the surface of the layer 16, the second plating stage 240 can commence to increase the thickness of the layer 16 as described above with reference to FIG. 3D. Referring to both FIGS. 3C and 4, filling the first depressions to form a plated layer of material that at least substantially fills the first features 12 includes either completely filling the first features 12 (FIG. 3C) or nearly filling the first features 12 (FIG. 4) before removing the accelerator and/or other additives from the surface of the plated layer.
  • [0031]
    FIG. 5 is a schematic side cross-sectional view of a system 500 for filling features on microfeature workpieces in accordance with an embodiment of the invention. In this embodiment, the system 500 includes a workpiece holder 510 having electrical contacts configured to contact a surface of the workpiece 10, a plating vessel 520 having an inlet 522 through which a plating solution 524 can flow into the vessel 520, and a counter electrode 530. The system 500 optionally can include a flow distributor 540 having a plurality of openings 542 for conditioning the flow of the plating solution 524 upstream from the workpiece 10. The system 500 can further include a power supply 550 operatively coupled to the workpiece holder 510 and the counter electrode 530. As explained above, the power supply 550 establishes an electrical field in the plating vessel 520 for electrochemically processing the workpiece 10 by plating and/or de-plating the plating species to/from the workpiece 10.
  • [0032]
    The system 500 further includes a controller 560 coupled to the power supply 550. The controller 560 includes a computer operable medium that contains instructions to effectuate any of the methods for filling features on microfeature workpieces set forth above. The computer operable medium of the controller 560, for example, can contain instructions that cause the power supply 550 to (a) electrochemically deposit the plating species onto the workpiece 10 until the plating species at least substantially fills first features on the workpiece, (b) change the concentration of the accelerator and/or another additive on a surface of a plated layer of the plating species aligned with the first features, and (c) electroplate more of the plating species onto the workpiece after changing the concentration of the accelerator and/or other additives on the surface of the plated layer. In another embodiment, the computer operable medium can contain instructions that cause the power source to (a) electrochemically deposit the plating species onto the workpiece to form a plated layer that fills first depressions on the workpiece, (b) electrochemically remove accumulations of the accelerator and a portion of the plated layer to produce a reconditioned surface on the plated layer, and (c) electroplate more of the plating species onto the reconditioned surface of the plated layer.
  • [0033]
    From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims (31)

  1. 1. A method of filling features on microfeature workpieces, comprising:
    contacting a surface of a microfeature workpiece with a plating solution that includes a plating species and an accelerator for enhancing deposition of the plating species in depressions on the workpiece;
    filling first depressions on the workpiece with the plating species by electrochemically depositing the plating species onto the workpiece to form a plated layer that at least substantially fills the first depressions on the workpiece;
    reducing a concentration of the accelerator accumulated on a surface of the plated layer after the plated layer at least substantially fills the first depressions; and
    electroplating more of the plating species onto the workpiece after reducing the concentration of the accelerator on the surface of the plated layer.
  2. 2. The method of claim 1 wherein the first depressions have a first width and the workpiece further comprises a second depression having a second width larger than the first width, and wherein filling the first depressions comprises completely filling the first depressions with the plating species without completely filling the second depression with the plating species before reducing the concentration of the accelerator on the surface of the plated layer.
  3. 3. The method of claim 1 wherein:
    the first depressions have a first width and the workpiece further comprises a second depression having a second width larger than the first width;
    filling the first depressions comprises electroplating the plating species onto the workpiece using a forward electrical bias until the plating species completely fills the first depressions without completely filling the second depression; and
    reducing the concentration of the accelerator comprises reversing the electrical bias to de-plate the plating species from the workpiece.
  4. 4. The method of claim 3 wherein de-plating the plating species from the workpiece comprises removing approximately 3 Å to 100 Å of the plated layer, and electroplating more of the plating species comprises filling the second depression with the plating species after de-plating.
  5. 5. The method of claim 1 wherein:
    the first depressions have a first width and the workpiece further comprises a second depression having a second width larger than the first width;
    filling the first depressions comprises electroplating the plating species onto the workpiece using a forward electrical bias until the plating species completely fills the first depressions without completely filling the second depression with the plating species; and
    reducing the concentration of the accelerator comprises de-plating a portion of the plated layer from the workpiece.
  6. 6. The method of claim 5 wherein electroplating more of the plated species onto the workpiece comprises filling the second depression with the plating species after de-plating a portion of the plated layer from the workpiece.
  7. 7. The method of claim 5 wherein the plating species comprises copper, and wherein electrochemically depositing the plating species onto the workpiece comprises electrolessly plating copper into the first depressions.
  8. 8. The method of claim 5 wherein the plating species comprises copper, and wherein electrochemically depositing the plating species onto the workpiece comprises electroplating the copper into the first depressions.
  9. 9. A method of filling features on microfeature workpieces having first features with a first dimension and second features with a second dimension greater than the first dimension, comprising:
    contacting a surface of a microfeature workpiece with a plating solution having a plating species and an accelerator;
    electrochemically depositing the plating species onto the workpiece to form a plated layer that at least substantially occupies the first features of the workpiece;
    removing accumulations of the accelerator from a surface of the plated layer; and
    electroplating more of the plating species onto the workpiece after removing the accumulations of the accelerator to bulk plate the plating species into the second features.
  10. 10. The method of claim 9 wherein electrochemically depositing the plating species onto the workpiece to form a plated layer comprises completely filling the first features with the plating species without completely filling the second features before removing the accumulations of the accelerator from the surface of the plated layer.
  11. 11. The method of claim 10 wherein removing the accumulations of the accelerator from the surface of the plated layer comprises de-plating material from the plated layer.
  12. 12. The method of claim 9 wherein removing the accumulations of the accelerator from the surface of the plated layer comprises de-plating material from the plated layer.
  13. 13. The method of claim 12 wherein de-plating material from the plated layer comprises removing approximately 3 Å to approximately 100 Å of the plated layer.
  14. 14. The method of claim 9 wherein electrochemically depositing the plating species comprises electrolessly plating copper into the first features.
  15. 15. The method of claim 9 wherein electrochemically depositing the plating species onto the workpiece to form a plated layer comprises electroplating copper into the first features.
  16. 16. A method of filling features on microfeature workpieces having first depressions with a first dimension and a second depression with a second dimension greater than the first dimension, comprising:
    contacting a surface of a microfeature workpiece with a plating solution having a plating species and an accelerator;
    electrochemically depositing the plating species onto the workpiece until the plating species at least partially fills the first depressions;
    changing a concentration of the accelerator on a surface of a plated layer at locations aligned with the first depressions; and
    electroplating more of the plating species onto the workpiece after changing the concentration of the accelerator on the surface of the plated layer.
  17. 17. The method of claim 16 wherein electrochemically depositing the plating species onto the workpiece comprises completely filling the first depressions with the plating species without completely filling the second depression.
  18. 18. The method of claim 16 wherein electrochemically depositing the plating species onto the workpiece comprises filling the first depressions by electroplating the plating species onto the workpiece using a forward electrical bias.
  19. 19. The method of claim 18 wherein changing a concentration of the accelerator on the surface of the plated layer comprises applying a reverse electrical bias to the workpiece.
  20. 20. The method of claim 18 wherein changing a concentration of the accelerator on the surface of the plated layer comprises applying a reverse electrical bias to the workpiece to de-plate a portion of the plating layer.
  21. 21. The method of claim 16 wherein changing a concentration of the accelerator on the surface of the plated layer comprises de-plating a portion of the plated layer.
  22. 22. The method of claim 21 wherein de-plating a portion of the plating layer comprises removing approximately 3 Å to 100 Å of the plated layer.
  23. 23. The method of claim 16 wherein electrochemically depositing the plating species onto the workpiece comprises electrolessly plating copper into the first depressions.
  24. 24. The method of claim 16 wherein electrochemically depositing the plating species onto the workpiece comprises electroplating copper into the first depressions.
  25. 25. A method of filling features on microfeature workpieces having first depressions with a first dimension and a second depression with a second dimension greater than the first dimension, comprising:
    contacting a surface of a microfeature workpiece with a plating solution having a plating species and an accelerator;
    electrochemically depositing the plating species onto the workpiece until the plating species fills the first depressions to form a plated layer on the workpiece;
    electrochemically removing (a) accumulations of the accelerator from a surface of the plated layer and (b) a portion of the plated layer to produce a reconditioned surface on the plated layer; and
    electroplating more of the plating species onto the restored surface of the plated layer to increase the thickness of the plated layer.
  26. 26. The method of claim 25 wherein electrochemically depositing the plating species under the workpiece comprises electrolessly plating copper into the first depressions.
  27. 27. The method of claim 25 wherein electrochemically depositing the plating species under the workpiece comprises electroplating copper into the first depressions.
  28. 28. The method of claim 25 wherein electrochemically removing the accumulations of the accelerator from the surface of the plated layer and a portion of the plated layer to produce a reconditioned surface comprises de-plating material from the plated layer.
  29. 29. The method of claim 28 wherein de-plating material from the plated layer comprises applying a reverse electrical bias to the workpiece.
  30. 30. A system for filling features on microfeature workpieces having first features with a first size and a second feature with a second size greater than the first size, comprising:
    a workpiece holder having electrical contacts configured to contact a surface of the workpiece;
    a plating vessel configured to contain a plating solution having a plating species and an accelerator;
    a counter electrode in the plating vessel;
    a power source coupled to the electrical contacts and the counter electrode to establish an electrical field through the plating solution in the plating vessel for electrochemically processing the workpiece; and
    a controller coupled to the power source, wherein the controller includes a computer operable medium that contains instructions which cause the power source to (a) electrochemically deposit the plating species onto the workpiece until the plating species at least substantially fills the first features, (b) change the concentration of the accelerator on a surface of a plated layer of the plating species at locations aligned with the first features, and (c) electroplate more of the plating species onto the workpiece after changing the concentration of the accelerator on the surface of the plated layer.
  31. 31. A system for filling features on microfeature workpieces having first depressions with a first size and a second depression with a second size greater than the first size, comprising:
    a workpiece holder having electrical contacts configured to contact a surface of the workpiece;
    a plating vessel configured to contain a plating solution having a plating species and an accelerator;
    a counter electrode in the plating reactor;
    a power source coupled to the electrical contacts and the counter electrode to establish an electrical field in the plating vessel that electrochemically processes the workpiece; and
    a controller coupled to the power source, wherein the controller includes a computer operable medium that contains instructions which cause the power source to (a) electrochemically deposit the plating species onto the workpiece to form a plated layer that fills the first depressions, (b) electrochemically remove accumulations of the accelerator from a surface of the plated layer and a portion of the plated layer to produce a restored surface on the plated layer, and (c) electroplate more of the plating species onto the restored surface of the plated layer.
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060042952A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US20060216862A1 (en) * 2003-11-13 2006-09-28 Micron Technology, Inc. Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7683458B2 (en) 2004-09-02 2010-03-23 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7830018B2 (en) 2007-08-31 2010-11-09 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US7829976B2 (en) 2004-06-29 2010-11-09 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7915736B2 (en) 2005-09-01 2011-03-29 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US8536485B2 (en) 2004-05-05 2013-09-17 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US8795482B1 (en) * 2002-07-29 2014-08-05 Novellus Systems, Inc. Selective electrochemical accelerator removal
US9214391B2 (en) 2004-12-30 2015-12-15 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433304B1 (en) *
US2821959A (en) * 1956-03-29 1958-02-04 Bell Telephone Labor Inc Mass soldering of electrical assemblies
US3006318A (en) * 1958-03-26 1961-10-31 Western Electric Co Apparatus for applying solder coatings to surfaces
US3345134A (en) * 1962-04-21 1967-10-03 Knapsack Ag Process and apparatus for the manufacture of titanium nitride
US3865298A (en) * 1973-08-14 1975-02-11 Atomic Energy Commission Solder leveling
US3902036A (en) * 1974-05-02 1975-08-26 Western Electric Co Control system using multiplexed laser beams
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4368106A (en) * 1980-10-27 1983-01-11 General Electric Company Implantation of electrical feed-through conductors
US4534100A (en) * 1982-06-28 1985-08-13 The United States Of America As Represented By The Secretary Of The Air Force Electrical method of making conductive paths in silicon
US4581301A (en) * 1984-04-10 1986-04-08 Michaelson Henry W Additive adhesive based process for the manufacture of printed circuit boards
US4608480A (en) * 1983-06-15 1986-08-26 S.N.E.C.M.A. Process and apparatus for laser drilling
US4614427A (en) * 1983-05-20 1986-09-30 Hitachi, Ltd. Automatic contaminants detection apparatus
US4627971A (en) * 1985-04-22 1986-12-09 Alza Corporation Osmotic device with self-sealing passageway
US4660063A (en) * 1985-03-18 1987-04-21 General Electric Company Immersion type ISFET
US4756765A (en) * 1982-01-26 1988-07-12 Avco Research Laboratory, Inc. Laser removal of poor thermally-conductive materials
US4768291A (en) * 1987-03-12 1988-09-06 Monarch Technologies Corporation Apparatus for dry processing a semiconductor wafer
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
US4907127A (en) * 1988-03-21 1990-03-06 Lee John K C Printed circuit board construction and method for producing printed circuit end products
US4959705A (en) * 1988-10-17 1990-09-25 Ford Microelectronics, Inc. Three metal personalization of application specific monolithic microwave integrated circuit
US4964212A (en) * 1988-09-29 1990-10-23 Commissariat A L'energie Atomique Process for producing electrical connections through a substrate
US4984597A (en) * 1984-05-21 1991-01-15 Cfm Technologies Research Associates Apparatus for rinsing and drying surfaces
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5024966A (en) * 1988-12-21 1991-06-18 At&T Bell Laboratories Method of forming a silicon-based semiconductor optical device mount
US5027184A (en) * 1981-03-02 1991-06-25 Rockwell International Corporation NPN type lateral transistor with minimal substrate operation interference
US5026964A (en) * 1986-02-28 1991-06-25 General Electric Company Optical breakthrough sensor for laser drill
US5037782A (en) * 1989-03-29 1991-08-06 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device including via holes
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5123902A (en) * 1988-09-13 1992-06-23 Carl-Zeiss-Stiftung Method and apparatus for performing surgery on tissue wherein a laser beam is applied to the tissue
US5144412A (en) * 1987-02-19 1992-09-01 Olin Corporation Process for manufacturing plastic pin grid arrays and the product produced thereby
US5145099A (en) * 1990-07-13 1992-09-08 Micron Technology, Inc. Method for combining die attach and lead bond in the assembly of a semiconductor package
US5158911A (en) * 1990-08-03 1992-10-27 Thomson Composants Microondes Method for interconnection between an integrated circuit and a support circuit, and integrated circuit adapted to this method
US5200366A (en) * 1990-04-27 1993-04-06 Hitachi, Ltd. Semiconductor device, its fabrication method and molding apparatus used therefor
US5219344A (en) * 1988-06-09 1993-06-15 Visx, Incorporated Methods and apparatus for laser sculpture of the cornea
US5233448A (en) * 1992-05-04 1993-08-03 Industrial Technology Research Institute Method of manufacturing a liquid crystal display panel including photoconductive electrostatic protection
US5237148A (en) * 1990-10-04 1993-08-17 Brother Kogyo Kabushiki Device for manufacturing a nozzle and its manufacturing method
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5294568A (en) * 1990-10-12 1994-03-15 Genus, Inc. Method of selective etching native oxide
US5304743A (en) * 1992-05-12 1994-04-19 Lsi Logic Corporation Multilayer IC semiconductor package
US5378313A (en) * 1993-12-22 1995-01-03 Pace; Benedict G. Hybrid circuits and a method of manufacture
US5378312A (en) * 1993-12-07 1995-01-03 International Business Machines Corporation Process for fabricating a semiconductor structure having sidewalls
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5402435A (en) * 1993-03-05 1995-03-28 Matsushita Electric Industrial Co., Ltd. Optical device
US5406630A (en) * 1992-05-04 1995-04-11 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
US5424573A (en) * 1992-03-04 1995-06-13 Hitachi, Ltd. Semiconductor package having optical interconnection access
US5438212A (en) * 1993-02-25 1995-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with heat dissipation structure
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5464960A (en) * 1993-01-12 1995-11-07 Iatrotech, Inc. Laser calibration device
US5481483A (en) * 1992-11-23 1996-01-02 Ford Motor Company Non-contact method of obtaining dimensional information about an object for comparing similar objects
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
US5496755A (en) * 1989-11-29 1996-03-05 Texas Instruments Incorporated Integrated circuit and method
US5515167A (en) * 1994-09-13 1996-05-07 Hughes Aircraft Company Transparent optical chuck incorporating optical monitoring
US5518956A (en) * 1993-09-02 1996-05-21 General Electric Company Method of isolating vertical shorts in an electronic array using laser ablation
US5550403A (en) * 1994-06-02 1996-08-27 Lsi Logic Corporation Improved laminate package for an integrated circuit and integrated circuit having such a package
US5585308A (en) * 1993-12-23 1996-12-17 Sgs-Thomson Microelectronics, Inc. Method for improved pre-metal planarization
US5585675A (en) * 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5614743A (en) * 1994-07-26 1997-03-25 Kabushiki Kaisha Toshiba Microwave integrated circuit (MIC) having a reactance element formed on a groove
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5624437A (en) * 1995-03-28 1997-04-29 Freeman; Jerre M. High resolution, high speed, programmable laser beam modulating apparatus for microsurgery
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5654221A (en) * 1994-10-17 1997-08-05 International Business Machines Corporation Method for forming semiconductor chip and electronic module with integrated surface interconnects/components
US5734555A (en) * 1994-03-30 1998-03-31 Intel Corporation Shared socket multi-chip module and/or piggyback pin grid array package
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6107186A (en) * 1999-01-27 2000-08-22 Advanced Micro Devices, Inc. High planarity high-density in-laid metallization patterns by damascene-CMP processing
US6137163A (en) * 1997-09-12 2000-10-24 Hyundai Electronics Industries Co., Ltd. Semiconductor substrate and stackable semiconductor package and fabrication method thereof
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US6297155B1 (en) * 1999-05-03 2001-10-02 Motorola Inc. Method for forming a copper layer over a semiconductor wafer
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6388208B1 (en) * 1999-06-11 2002-05-14 Teradyne, Inc. Multi-connection via with electrically isolated segments
US6433304B2 (en) * 1999-12-22 2002-08-13 Honda Giken Kogyo Kabushiki Kaisha Perforating machining method with laser beam
US6432821B1 (en) * 2000-12-18 2002-08-13 Intel Corporation Method of copper electroplating
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6448106B1 (en) * 1999-11-09 2002-09-10 Fujitsu Limited Modules with pins and methods for making modules with pins
US6455425B1 (en) * 2000-01-18 2002-09-24 Advanced Micro Devices, Inc. Selective deposition process for passivating top interface of damascene-type Cu interconnect lines
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
US6736953B1 (en) * 2001-09-28 2004-05-18 Lsi Logic Corporation High frequency electrochemical deposition
US6750144B2 (en) * 2002-02-15 2004-06-15 Faraday Technology Marketing Group, Llc Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes
US20040188260A1 (en) * 2003-03-31 2004-09-30 Matthias Bonkabeta Method of plating a semiconductor structure
US20040265562A1 (en) * 2003-01-30 2004-12-30 Uzoh Cyprian E Method of electroplating copper layers with flat topography
US6847109B2 (en) * 2002-09-25 2005-01-25 Samsung Electronics Co., Ltd. Area array semiconductor package and 3-dimensional stack thereof
US20050189637A1 (en) * 2004-02-17 2005-09-01 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6939343B2 (en) * 2003-02-28 2005-09-06 Nidex Co., Ltd. Ophthalmic laser surgical apparatus
US20060195729A1 (en) * 2001-12-05 2006-08-31 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
US7111149B2 (en) * 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US7279776B2 (en) * 2004-05-25 2007-10-09 Canon Kabushiki Kaisha Method of manufacturing semiconductor device and semiconductor device
US7378726B2 (en) * 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
US7408265B2 (en) * 2002-08-15 2008-08-05 Micron Technology, Inc. Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates
US7449098B1 (en) * 1999-10-05 2008-11-11 Novellus Systems, Inc. Method for planar electroplating
US20080299759A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method to form a via
US20080299762A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method for forming interconnects for 3-D applications
US20080318361A1 (en) * 2007-06-20 2008-12-25 Kwon Whan Han Method for manufacturing semiconductor package
US20090091962A1 (en) * 2007-10-04 2009-04-09 Samsung Electronics Co., Ltd. Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory
US20090127668A1 (en) * 2007-11-21 2009-05-21 Samsung Electronics Co., Ltd. Stacked semiconductor device and method of forming serial path thereof
US20090146312A1 (en) * 2007-12-06 2009-06-11 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20090283898A1 (en) * 2008-05-15 2009-11-19 Janzen Jeffery W Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
US20090315154A1 (en) * 2008-06-19 2009-12-24 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20090321947A1 (en) * 2008-06-27 2009-12-31 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods

Patent Citations (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433304B1 (en) *
US2821959A (en) * 1956-03-29 1958-02-04 Bell Telephone Labor Inc Mass soldering of electrical assemblies
US3006318A (en) * 1958-03-26 1961-10-31 Western Electric Co Apparatus for applying solder coatings to surfaces
US3345134A (en) * 1962-04-21 1967-10-03 Knapsack Ag Process and apparatus for the manufacture of titanium nitride
US3865298A (en) * 1973-08-14 1975-02-11 Atomic Energy Commission Solder leveling
US3902036A (en) * 1974-05-02 1975-08-26 Western Electric Co Control system using multiplexed laser beams
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4368106A (en) * 1980-10-27 1983-01-11 General Electric Company Implantation of electrical feed-through conductors
US5027184A (en) * 1981-03-02 1991-06-25 Rockwell International Corporation NPN type lateral transistor with minimal substrate operation interference
US4756765A (en) * 1982-01-26 1988-07-12 Avco Research Laboratory, Inc. Laser removal of poor thermally-conductive materials
US4534100A (en) * 1982-06-28 1985-08-13 The United States Of America As Represented By The Secretary Of The Air Force Electrical method of making conductive paths in silicon
US4614427A (en) * 1983-05-20 1986-09-30 Hitachi, Ltd. Automatic contaminants detection apparatus
US4608480A (en) * 1983-06-15 1986-08-26 S.N.E.C.M.A. Process and apparatus for laser drilling
US4581301A (en) * 1984-04-10 1986-04-08 Michaelson Henry W Additive adhesive based process for the manufacture of printed circuit boards
US4984597B1 (en) * 1984-05-21 1999-10-26 Cfmt Inc Apparatus for rinsing and drying surfaces
US4984597A (en) * 1984-05-21 1991-01-15 Cfm Technologies Research Associates Apparatus for rinsing and drying surfaces
US4660063A (en) * 1985-03-18 1987-04-21 General Electric Company Immersion type ISFET
US4627971A (en) * 1985-04-22 1986-12-09 Alza Corporation Osmotic device with self-sealing passageway
US5026964A (en) * 1986-02-28 1991-06-25 General Electric Company Optical breakthrough sensor for laser drill
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
US5144412A (en) * 1987-02-19 1992-09-01 Olin Corporation Process for manufacturing plastic pin grid arrays and the product produced thereby
US4768291A (en) * 1987-03-12 1988-09-06 Monarch Technologies Corporation Apparatus for dry processing a semiconductor wafer
US4907127A (en) * 1988-03-21 1990-03-06 Lee John K C Printed circuit board construction and method for producing printed circuit end products
US5219344A (en) * 1988-06-09 1993-06-15 Visx, Incorporated Methods and apparatus for laser sculpture of the cornea
US5123902A (en) * 1988-09-13 1992-06-23 Carl-Zeiss-Stiftung Method and apparatus for performing surgery on tissue wherein a laser beam is applied to the tissue
US4964212A (en) * 1988-09-29 1990-10-23 Commissariat A L'energie Atomique Process for producing electrical connections through a substrate
US4959705A (en) * 1988-10-17 1990-09-25 Ford Microelectronics, Inc. Three metal personalization of application specific monolithic microwave integrated circuit
US5024966A (en) * 1988-12-21 1991-06-18 At&T Bell Laboratories Method of forming a silicon-based semiconductor optical device mount
US5037782A (en) * 1989-03-29 1991-08-06 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device including via holes
US5496755A (en) * 1989-11-29 1996-03-05 Texas Instruments Incorporated Integrated circuit and method
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5200366A (en) * 1990-04-27 1993-04-06 Hitachi, Ltd. Semiconductor device, its fabrication method and molding apparatus used therefor
US5145099A (en) * 1990-07-13 1992-09-08 Micron Technology, Inc. Method for combining die attach and lead bond in the assembly of a semiconductor package
US5158911A (en) * 1990-08-03 1992-10-27 Thomson Composants Microondes Method for interconnection between an integrated circuit and a support circuit, and integrated circuit adapted to this method
US5237148A (en) * 1990-10-04 1993-08-17 Brother Kogyo Kabushiki Device for manufacturing a nozzle and its manufacturing method
US5294568A (en) * 1990-10-12 1994-03-15 Genus, Inc. Method of selective etching native oxide
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5424573A (en) * 1992-03-04 1995-06-13 Hitachi, Ltd. Semiconductor package having optical interconnection access
US5233448A (en) * 1992-05-04 1993-08-03 Industrial Technology Research Institute Method of manufacturing a liquid crystal display panel including photoconductive electrostatic protection
US5406630A (en) * 1992-05-04 1995-04-11 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
US5304743A (en) * 1992-05-12 1994-04-19 Lsi Logic Corporation Multilayer IC semiconductor package
US5481483A (en) * 1992-11-23 1996-01-02 Ford Motor Company Non-contact method of obtaining dimensional information about an object for comparing similar objects
US5464960A (en) * 1993-01-12 1995-11-07 Iatrotech, Inc. Laser calibration device
US5438212A (en) * 1993-02-25 1995-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with heat dissipation structure
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5402435A (en) * 1993-03-05 1995-03-28 Matsushita Electric Industrial Co., Ltd. Optical device
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5518956A (en) * 1993-09-02 1996-05-21 General Electric Company Method of isolating vertical shorts in an electronic array using laser ablation
US5378312A (en) * 1993-12-07 1995-01-03 International Business Machines Corporation Process for fabricating a semiconductor structure having sidewalls
US5378313A (en) * 1993-12-22 1995-01-03 Pace; Benedict G. Hybrid circuits and a method of manufacture
US5585308A (en) * 1993-12-23 1996-12-17 Sgs-Thomson Microelectronics, Inc. Method for improved pre-metal planarization
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5734555A (en) * 1994-03-30 1998-03-31 Intel Corporation Shared socket multi-chip module and/or piggyback pin grid array package
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US5585675A (en) * 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5550403A (en) * 1994-06-02 1996-08-27 Lsi Logic Corporation Improved laminate package for an integrated circuit and integrated circuit having such a package
US5614743A (en) * 1994-07-26 1997-03-25 Kabushiki Kaisha Toshiba Microwave integrated circuit (MIC) having a reactance element formed on a groove
US5515167A (en) * 1994-09-13 1996-05-07 Hughes Aircraft Company Transparent optical chuck incorporating optical monitoring
US5654221A (en) * 1994-10-17 1997-08-05 International Business Machines Corporation Method for forming semiconductor chip and electronic module with integrated surface interconnects/components
US5624437A (en) * 1995-03-28 1997-04-29 Freeman; Jerre M. High resolution, high speed, programmable laser beam modulating apparatus for microsurgery
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6137163A (en) * 1997-09-12 2000-10-24 Hyundai Electronics Industries Co., Ltd. Semiconductor substrate and stackable semiconductor package and fabrication method thereof
US6107186A (en) * 1999-01-27 2000-08-22 Advanced Micro Devices, Inc. High planarity high-density in-laid metallization patterns by damascene-CMP processing
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US6297155B1 (en) * 1999-05-03 2001-10-02 Motorola Inc. Method for forming a copper layer over a semiconductor wafer
US6388208B1 (en) * 1999-06-11 2002-05-14 Teradyne, Inc. Multi-connection via with electrically isolated segments
US7449098B1 (en) * 1999-10-05 2008-11-11 Novellus Systems, Inc. Method for planar electroplating
US6448106B1 (en) * 1999-11-09 2002-09-10 Fujitsu Limited Modules with pins and methods for making modules with pins
US6433304B2 (en) * 1999-12-22 2002-08-13 Honda Giken Kogyo Kabushiki Kaisha Perforating machining method with laser beam
US6455425B1 (en) * 2000-01-18 2002-09-24 Advanced Micro Devices, Inc. Selective deposition process for passivating top interface of damascene-type Cu interconnect lines
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
US6432821B1 (en) * 2000-12-18 2002-08-13 Intel Corporation Method of copper electroplating
US6736953B1 (en) * 2001-09-28 2004-05-18 Lsi Logic Corporation High frequency electrochemical deposition
US20060195729A1 (en) * 2001-12-05 2006-08-31 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
US6750144B2 (en) * 2002-02-15 2004-06-15 Faraday Technology Marketing Group, Llc Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes
US7408265B2 (en) * 2002-08-15 2008-08-05 Micron Technology, Inc. Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates
US6847109B2 (en) * 2002-09-25 2005-01-25 Samsung Electronics Co., Ltd. Area array semiconductor package and 3-dimensional stack thereof
US20040265562A1 (en) * 2003-01-30 2004-12-30 Uzoh Cyprian E Method of electroplating copper layers with flat topography
US6939343B2 (en) * 2003-02-28 2005-09-06 Nidex Co., Ltd. Ophthalmic laser surgical apparatus
US20040188260A1 (en) * 2003-03-31 2004-09-30 Matthias Bonkabeta Method of plating a semiconductor structure
US7111149B2 (en) * 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US20050189637A1 (en) * 2004-02-17 2005-09-01 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US7279776B2 (en) * 2004-05-25 2007-10-09 Canon Kabushiki Kaisha Method of manufacturing semiconductor device and semiconductor device
US7378726B2 (en) * 2005-12-28 2008-05-27 Intel Corporation Stacked packages with interconnecting pins
US20080299759A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method to form a via
US20080299762A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method for forming interconnects for 3-D applications
US20080318361A1 (en) * 2007-06-20 2008-12-25 Kwon Whan Han Method for manufacturing semiconductor package
US20090091962A1 (en) * 2007-10-04 2009-04-09 Samsung Electronics Co., Ltd. Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory
US20090127668A1 (en) * 2007-11-21 2009-05-21 Samsung Electronics Co., Ltd. Stacked semiconductor device and method of forming serial path thereof
US20090146312A1 (en) * 2007-12-06 2009-06-11 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20090283898A1 (en) * 2008-05-15 2009-11-19 Janzen Jeffery W Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
US20090315154A1 (en) * 2008-06-19 2009-12-24 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20090321947A1 (en) * 2008-06-27 2009-12-31 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8795482B1 (en) * 2002-07-29 2014-08-05 Novellus Systems, Inc. Selective electrochemical accelerator removal
US7759800B2 (en) 2003-11-13 2010-07-20 Micron Technology, Inc. Microelectronics devices, having vias, and packaged microelectronic devices having vias
US20060216862A1 (en) * 2003-11-13 2006-09-28 Micron Technology, Inc. Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US20060264041A1 (en) * 2003-11-13 2006-11-23 Micron Technology, Inc. Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US9653420B2 (en) 2003-11-13 2017-05-16 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US8748311B2 (en) 2003-12-10 2014-06-10 Micron Technology, Inc. Microelectronic devices and methods for filing vias in microelectronic devices
US9452492B2 (en) 2004-05-05 2016-09-27 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US8686313B2 (en) 2004-05-05 2014-04-01 Micron Technology, Inc. System and methods for forming apertures in microfeature workpieces
US8664562B2 (en) 2004-05-05 2014-03-04 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US8536485B2 (en) 2004-05-05 2013-09-17 Micron Technology, Inc. Systems and methods for forming apertures in microfeature workpieces
US7829976B2 (en) 2004-06-29 2010-11-09 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US20060042952A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US7956443B2 (en) 2004-09-02 2011-06-07 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7683458B2 (en) 2004-09-02 2010-03-23 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US8669179B2 (en) 2004-09-02 2014-03-11 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US8502353B2 (en) 2004-09-02 2013-08-06 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US9214391B2 (en) 2004-12-30 2015-12-15 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US9293367B2 (en) 2005-06-28 2016-03-22 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US8008192B2 (en) 2005-06-28 2011-08-30 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7915736B2 (en) 2005-09-01 2011-03-29 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US8610279B2 (en) 2006-08-28 2013-12-17 Micron Technologies, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7973411B2 (en) 2006-08-28 2011-07-05 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US9570350B2 (en) 2006-08-31 2017-02-14 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US9099539B2 (en) 2006-08-31 2015-08-04 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7830018B2 (en) 2007-08-31 2010-11-09 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US8536046B2 (en) 2007-08-31 2013-09-17 Micron Technology Partitioned through-layer via and associated systems and methods
US8367538B2 (en) 2007-08-31 2013-02-05 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US9281241B2 (en) 2007-12-06 2016-03-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8247907B2 (en) 2007-12-06 2012-08-21 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

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