CN1692495A - 半导体集成装置及其制造方法 - Google Patents

半导体集成装置及其制造方法 Download PDF

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Publication number
CN1692495A
CN1692495A CNA2003801002199A CN200380100219A CN1692495A CN 1692495 A CN1692495 A CN 1692495A CN A2003801002199 A CNA2003801002199 A CN A2003801002199A CN 200380100219 A CN200380100219 A CN 200380100219A CN 1692495 A CN1692495 A CN 1692495A
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Prior art keywords
integrated device
wiring
semiconductor integrated
semiconductor substrate
semiconductor
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铃木信广
今井宪次
北村勇也
山口惠一
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1692495A publication Critical patent/CN1692495A/zh
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Abstract

本发明提供一种半导体集成装置及其制造方法。该制造方法包含：在半导体基板形成集成电路元件的工序；形成内部布线的工序；在半导体基板的背面，沿着划线形成使内部布线的一部分露出的沟的工序；至少覆盖沟形成金属膜的工序；对金属膜构图，形成外部布线，并且在沟的底部除去金属膜的工序；覆盖外部布线和沟的底部形成保护膜的工序；沿着划线分割半导体芯片的工序。

Description

半导体集成装置及其制造方法
技术领域
本发明涉及在元件的侧面具有金属的外部布线的半导体集成装置及其制造方法。
背景技术
为了实现半导体集成装置的芯片尺寸的小型化，使用从元件侧面引出外部布线的芯片尺寸封装(CSP)。
图12A和12B表示使用芯片尺寸封装的半导体集成装置的外观图。通常，芯片尺寸封装的半导体集成装置的构造为：把半导体芯片10隔着环氧等的树脂层12由上部支撑基体14和下部支撑基体16夹入，从其侧面引出外部布线18，并将其连接在设置于元件背面上的球状端子20上。
具有这样构造的芯片尺寸封装的半导体集成装置如图13～图19所示，通过进行以下工序而制造：形成把半导体芯片10的两面隔着树脂层12由上部支撑基体14和下部支撑基体16夹入的层叠体的层叠体形成工序(S10)；从下部支撑基体16一侧，通过基于切片锯的切削，把沟(切口沟)24形成反V字型，使半导体芯片10的内部布线26的端部28露出的切削工序(S12)；在沟24的内部形成金属膜30的金属膜形成工序(S14)；对该金属膜30构图，形成连接内部布线26的端部28和缓冲部件32的外部布线18的构图工序(S16)；形成保护膜34的保护膜形成工序(S18)；形成球状端子20的端子形成工序(S20)；把沟24的底部作为切割线进行切断的切片工序(S22)。
通过所述以往技术制造的芯片尺寸封装的半导体集成装置如图20的端部放大图所示，位于元件侧面的外部布线18的端部36未被保护膜34覆盖，存在着易受来自元件外部的腐蚀的问题。
结果，外部布线18容易从元件侧面剥离，与内部布线26的接触电阻也增大，产生半导体集成装置的动作可靠性下降的问题。
此外，在切片工序(S22)后，为了用保护膜覆盖外部布线18的端部36，有必要对切断的各半导体集成装置另外进行保护膜的涂敷处理，所以造成生产效率的显著下降。
发明内容
本发明是鉴于所述技术问题而提出的，其目的在于：提供一种至少能够解决所述问题的一个，能防止位于元件侧面的外部布线的腐蚀的半导体集成装置及其制造方法。
用于解决所述问题的本发明是一种半导体集成装置的制造方法，其特征在于：包括：在由划线划分的半导体基板的各区域中形成集成电路元件的第一工序；跨邻接的集成电路元件的边界形成内部布线的第二工序；在所述半导体基板的背面，沿着所述划线形成使所述内部布线的一部分露出的沟的第三工序；覆盖所述半导体基板的背面和所述沟，形成金属膜的第四工序；对所述金属膜构图，形成外部布线，并且在所述沟的底部除去所述金属膜的第五工序；覆盖所述外部布线和所述沟的底部，形成保护膜的第六工序；沿着所述划线分割所述半导体基板的第七工序。
此外，用于解决所述课题的本发明的其他形态是一种半导体集成装置，其特征在于：包括：在半导体基板上形成了集成电路元件的半导体芯片；形成在所述半导体基板上，延迟到所述半导体基板的侧边的内部布线；绕过所述半导体芯片的侧面配置，与所述内部布线连接的外部布线；所述外部布线的端部有保护膜覆盖。
附图说明
图1是表示本发明实施例的集成电路元件的形成工序的图。
图2是表示本发明实施例的内部布线的形成工序的图。
图3是表示本发明实施例的层叠体的形成工序的图。
图4是表示本发明实施例的切削工序的图。
图5是表示本发明实施例的金属膜形成工序的图。
图6是表示本发明实施例的构图工序的图。
图7是表示本发明实施例的保护膜形成工序的图。
图8是表示本发明实施例的端子形成工序的图。
图9是表示本发明实施例的切片工序的图。
图10是表示本发明实施例的构图工序中的金属膜的除去的样子的图。
图11是本发明实施例的半导体集成装置的端部放大图。
图12A、图12B是表示芯片尺寸封装的半导体集成装置的外观的图。
图13是表示以往技术的层叠体形成工序的图。
图14是表示以往技术的切削工序的图。
图15是表示以往技术的金属膜形成工序的图。
图16是表示以往技术的构图工序的图。
图17是表示以往技术的保护膜形成工序的图。
图18是表示以往技术的端子形成工序的图。
图19是表示以往技术的切片工序的图。
图20是以往的半导体集成装置的端部放大图。
具体实施方式
本发明实施例的半导体集成装置的制造方法如图1～图9所示，基本上由集成电路元件形成工序(S30)、内部布线形成工序(S32)、层叠体形成工序(S34)、切削工序(S36)、金属膜形成工序(S38)；构图工序(S40)、保护膜形成工序(S42)、端子形成工序(S44)、切片工序(S46)构成。
工序S30的集成电路元件形成工序如图1所示，在由划线划分的半导体芯片10(晶片)的各区域形成集成电路元件。半导体芯片10可采用硅、砷化镓等一般的半导体材料，集成电路元件的形成通过众所周知的半导体工艺进行。
工序S32的内部布线形成工序如图2所示，在半导体芯片10的表面跨相邻的集成电路元件的边界，隔着氧化膜形成内部布线26。该内部布线26通过形成在氧化膜中的接触孔，与集成电路元件电连接。
此外，作为内部布线26的材料，可以把银、金、铜、铝、镍、钛、钽、钨等的一般在半导体器件中使用的材料作为主材料。当考虑电阻值或材料的加工性时，适合使用铝。此外，为了避免元件外部的腐蚀，更适合使用包含0.1原子％以上20原子％以下范围的铜的铝。
此外，为了降低与以后形成的外部布线的接触电阻，希望内部布线26的膜厚为1μm以上。而为了提高布线的加工精度，并且缩短成膜时间，希望为10μm以下。
在工序S34的层叠体形成工序中，如图3所示，在形成集成电路元件的半导体芯片10的表面背面涂敷环氧结合剂等的树脂层12，由上部支撑基体14和下部支撑基体16夹着形成层叠体。
这时，从背面一侧用机械研磨、化学研磨等磨半导体芯片10，使半导体芯片10的厚度变薄，从背面一侧沿着划线蚀刻半导体芯片10，加工成使层叠内部布线26的氧化膜的表面露出。
上部支撑基体14和下部支撑基体16可从玻璃、塑料、金属或陶瓷等的在半导体器件的封装中所使用的材料中适当选择使用。例如，当在硅基板上形成固态摄像元件时，作为上部支撑基体，适合使用透明的玻璃和塑料。
接着，在下部支撑基体16的表面上在以后的工序中形成球状端子20的位置形成缓冲部件32。该缓冲部件32起到缓和球状端子20所受的应力的垫子的作用。作为缓冲部件32，适合使用具有柔性，并且可被进行构图的材料，适合使用感光性环氧树脂。
在工序S36的切削工序中，如图4所示，从下部支撑基体16到达上部支撑基体14，通过切片锯等，形成倒V字型沟(切口沟)24。结果，使内部布线26的端部28在沟24的内表面露出。
在工序S38的金属成膜工序中，如图5所示，在形成沟24的下部支撑基体16一侧形成金属膜30。该金属膜30也形成在沟24的底面和侧面，通过在下述构图工序中进行形状加工，形成把内部布线26向外部引出的外部布线18。
作为金属膜30的材料，可把银、金、铜、铝、镍、钛、钽、钨等的一般在半导体器件中使用的材料作为主材料。当考虑电阻值和材料的加工性时，适合使用铝。此外，为了避免来自元件外部的腐蚀，更适合使用包含0.1原子％以上20原子％以下范围的铜的铝。
在工序S40的构图工序中，如图6所示，把金属膜30构图为规定的布线图案，进行外部布线18的形状加工。在构图中，可使用现有的光刻技术、蚀刻技术。
在工序S40中，与构图同时，除去在沟24的底面形成的金属膜30。即，如图10所示，覆盖沟24的底部以外形成抗蚀图形38，以该抗蚀图形38为掩模进行蚀刻，除去沟24的底面的金属膜30。
在工序S42的保护膜形成工序中，如图7所示，覆盖下部支撑基体16一侧的缓冲部件32以外的区域形成保护膜34。作为保护膜34，由于适合使用可进行构图的材料，所以可使用与缓冲部件32相同的感光性环氧树脂。
在工序S44的端子形成工序中，如图8所示，在下部支撑基体16的缓冲部件32上形成球状端子20作为外部端子。球状端子20例如由焊锡材料构成，可使用现有技术形成。
在工序S46的切片工序中，如图9所示，把沟24的底部作为切割线，使用切片锯切断层叠体，分割为各半导体集成装置。
这时，选择使用切片锯，使切断宽度比工序S30中的金属膜30的除去宽度还窄。由此，外部布线18的端部36位于比分割后的半导体集成装置的侧面还靠内侧，外部布线18的端部36由保护膜34覆盖。此外，当无法选择使切断宽度比金属膜30的除去宽度还窄的切片锯时，在工序S30中，预先除去宽度宽的金属膜30。
如上所述，根据本实施例的半导体集成装置的制造方法，如图11的端部放大图那样，在装置侧面具有外部布线18的芯片尺寸封装的半导体集成装置中，成为装置侧面外部布线18的端部36由保护膜34完全覆盖的构造。
因此，来自装置外部的腐蚀难以进行，能防止外部布线18的剥离或与内部布线26的接触电阻的恶化。结果，能提高半导体集成装置的可靠性。
此外，对于各半导体集成装置，没必要另外进行涂敷保护膜的处理，不会使生产率下降。
此外，在本实施例中，以球格阵列(BGA)型芯片尺寸封装为例进行说明，但只要是在元件侧面具有外部布线的半导体集成装置，通过同样制造，也能取得同样的构造，能取得同样的效果。
根据本发明，对于在元件侧面具有外部布线的半导体集成装置，可提供一种无需增加制造工序，避免布线腐蚀的半导体集成装置及其制造方法。

Claims (7)

1.一种半导体集成装置的制造方法，其特征在于：包括：
在由划线划分的半导体基板的各区域中形成集成电路元件的第一工序；
跨邻接的集成电路元件的边界形成内部布线的第二工序；
在所述半导体基板的背面，沿着所述划线形成使所述内部布线的一部分露出的沟的第三工序；
覆盖所述半导体基板的背面和所述沟，形成金属膜的第四工序；
对所述金属膜构图，形成外部布线，并且在所述沟的底部除去所述金属膜的第五工序；
覆盖所述外部布线和所述沟的底部，形成保护膜的第六工序；
沿着所述划线分割所述半导体基板的第七工序。
2.根据权利要求1所述的半导体集成装置的制造方法，其特征在于：
在所述第七工序中，以比所述沟的底部还窄的切断宽度分割所述半导体基板。
3.根据权利要求1所述的半导体集成装置的制造方法，其特征在于：
在所述第五工序中，所述沟的底部上的所述金属膜的除去宽度比在所述第六工序中的分割时的切断宽度宽。
4.一种半导体集成装置，其特征在于：包括：
在半导体基板上形成有集成电路元件的半导体芯片；
形成在所述半导体基板上，延伸到所述半导体基板的侧边的内部布线；
绕过所述半导体芯片的侧面配置，与所述内部布线连接的外部布线，
所述外部布线的端部由保护膜覆盖。
5.根据权利要求4所述的半导体集成装置，其特征在于：
所述外部布线的端部位于比半导体集成装置的侧面更靠内侧。
6.根据权利要求4所述的半导体集成装置，其特征在于：
所述外部布线由添加了铜的铝构成。
7.根据权利要求4所述的半导体集成装置，其特征在于：
所述内部布线由添加了铜的铝构成。
CNA2003801002199A 2002-11-12 2003-11-12 半导体集成装置及其制造方法 Pending CN1692495A (zh)

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