CN1445845A - 芯片比例封装及其制造方法 - Google Patents

芯片比例封装及其制造方法 Download PDF

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CN1445845A
CN1445845A CN03101447A CN03101447A CN1445845A CN 1445845 A CN1445845 A CN 1445845A CN 03101447 A CN03101447 A CN 03101447A CN 03101447 A CN03101447 A CN 03101447A CN 1445845 A CN1445845 A CN 1445845A
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chip scale
scale packages
chip
conductive layer
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尹畯皓
崔龙七
裴锡洙
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Samsung Electro Mechanics Co Ltd
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Abstract

公开了一种芯片比例封装和制造该芯片比例封装的方法。芯片比例封装包括在其一个表面上具有多个端子的芯片的上表面上形成的绝缘层，在绝缘层上形成的并按指定距离使彼此分开以便连接到多个端子的每一个上的多个导电层；以及在多个导电层的每个上表面上形成的多个电极面。在整个封装尺寸上小型化芯片比例封装。另外，制造芯片比例封装的方法不需要引线接合步骤或通孔形成步骤，从而简化芯片比例封装的制造过程并提高芯片比例封装的可靠性。

Description

芯片比例封装及其制造方法
技术领域
本发明涉及芯片比例封装，以及更具体地说涉及小型化芯片比例封装，包括在其一个表面上具有多个端子的芯片类型器件，以及制造该芯片比例封装的方法。
背景技术
通常，封装如晶体管的半导体器件，然后将这些封装的器件安装在印刷电路板上。结构上，该封装容易将半导体器件的端子连接到印刷电路板的相应信号图案上并用来保护半导体器件免受外应力，从而提高封装的可靠性。
为满足近来半导体产品小型化的趋势，也已经小型化了半导体芯片封装，因此，已经引入芯片比例封装(也称为“芯片尺寸封装”)。
图1是常规芯片比例封装的示意性剖视图。图1的芯片比例封装10的结构采用陶瓷衬底1并且是具有两个端子的二极管封装。
参考图1，在陶瓷衬底1上形成两个通孔，即第一通孔2a和第二通孔2b。用导电材料填充第一和第二通孔2a和2b以便将衬底1的上表面电连接到衬底1的下表面。然后，分别在第一和第二通孔2a和2b的上表面上形成第一和第二上导电焊盘3a和3b。分别在第一和第二通孔2a和2b的下表面上形成第一和第二下导电焊盘4a和4b。将第二上导电焊盘3b直接连接到形成在二极管5的下表面上的端子，即，印刷电路板上的二极管5的安装面，以及将第一上导电焊盘3a通过导线7连接到形成在二极管5的上表面上的另一端子。在包括二极管5的陶瓷衬底1的上表面形成使用常规树脂的模塑件9以便保护二极管5免受外应力。从而完成制造封装10。
图2是常规芯片比例封装组件的剖视图，其中将芯片比例封装安装在印刷电路板上。
如图2所示，通过回流焊接将制造的二极管封装10安装在印刷电路板20上。即，通过在印刷电路板20的相应信号图案上排列封装10的下导电焊盘4a和4b，然后用焊料15将下导电焊盘4a和4b连接到印刷电路板20的信号图案上，将二极管封装10安装在印刷电路板20上。
如图1和2所示，由于芯片通常具有在其两个相对面的每一个上的端子，这些端子必须通过导线内连。然而，这些导线需要芯片上表面上的很大空间，从而增加了封装的整个高度。另外，由于必须在陶瓷衬底上形成与二极管的端子数量相应的至少两个通孔，另外要求与通孔的总直径一样大的区域。因此，为了不使在通孔的上表面和下表面上形成的导电焊盘相互连接，必须用最小间隔使导电焊盘彼此分开。因此，衬底具有大尺寸以便满足上述条件，而且衬底的尺寸在小型化封装方面强加了限制。
上述二极管具有两个端子，分别形成在上表面和下表面上。然而，在其一个表面上具有多个端子的集成电路(IC)芯片进一步需要导线接合步骤或采用适当的引线框以便使端子相互内连。即，诸如IC芯片的器件具有多个端子，从而招致在小型化包括该器件的组件方面的困难并且使制造该封装的过程变得复杂。
另外，上述封装采用的衬底是引线框、印刷电路板或陶瓷衬底。这些衬底价格很高，从而增加了封装的生产成本。因此，常规封装的制造过程要求引线接合步骤以及模塑步骤以及芯片焊接(die-bonding)步骤，从而变得更加复杂。
因此，要求一种能小型化封装的尺寸以及简化其制造过程的封装技术。
发明概述
因此，鉴于上述问题提出了本发明，并且本发明的一个目的是通过在除端子区域外的芯片的上表面上形成绝缘层以及通过在绝缘层上形成导电层，并且在导电层上形成电极面，以便连接到印刷电路板的相应连接焊盘上来提供小型化和更容易制造的芯片比例封装，从而提高封装的可靠性。
本发明的另一目的是根据芯片比例封装的结构，提供具有创新安装方法的芯片封装组件。
本发明的另一目的是提供制造芯片比例封装的方法。
根据本发明的一个方面，通过提供包括在其一个表面上具有多个端子、在除多个端子区域外的芯片的表面上形成的绝缘层、在绝缘层上形成的并通过指定距离彼此分开以便连接到多个端子的每一个的多个导电层以及在多个导电层的每个上表面上形成的多个电极面的芯片的芯片比例封装来实现上述和其他目的。
根据本发明的另一方面，提供包括芯片比例封装和印刷电路板的芯片比例封装组件。芯片比例封装包括在其一个表面上具有多个端子、在除多个端子区域外的芯片的表面上形成的绝缘层、在绝缘层上形成的并通过指定距离彼此分开以便连接到多个端子的每一个的多个导电层以及在多个导电层的每个上表面上形成的多个电极面的芯片。印刷电路板包括多个用于连接到芯片比例封装的每个电极面的多个连接焊盘，以及连接到每个连接焊盘的电路图案。
根据本发明的另一方面，提供制造芯片比例封装的方法，包括步骤：准备包括多个芯片的晶片，每个芯片包括在其一个表面上的多个端子；在除用于形成端子的区域外的晶片的上表面上形成绝缘层；在绝缘层的上表面上形成导电层以便连接到多个端子；在导电层的上表面上形成电极面；将在绝缘层上形成的上导电层划分成两个多个部分以便连接到多个端子的每一个；以及将晶片切成多个封装单元。
附图说明
通过下述结合附图的详细说明将更容易理解本发明的上述和其他目的、特征和其他优点，其中：
图1是常规芯片比例封装的示意性剖视图；
图2是常规芯片比例封装组件的剖视图，其中将芯片比例封装安装在印刷电路板上；
图3a和3b是根据本发明的优选实施例的芯片比例封装的透视图和剖视图；
图4是芯片比例封装组件的透视图，其中根据本发明的优选实施例将芯片比例封装安装在印刷电路板上；以及
图5a至5f是根据本发明的优选实施例，描述制造芯片比例封装的方法的每个步骤。
具体实施方式
现在，参考附图来详细地描述本发明的优选实施例。
图3a和3b是根据本发明的优选实施例的芯片比例封装的透视图和剖视图。
参考图3a，芯片比例封装30包括在其一个表面上具有四个端子(未示出)的芯片35。芯片比例封装30进一步包括在芯片35上形成的绝缘层37、在绝缘层33的上表面上形成的并连接到四个端子的每一个的四个导电层31a、31b、31c和31d，以及在导电层31a、31b、31c或31d的每个上表面上形成的四个电极面33a、33b、33c或33d。在图3a中未示出，在本发明的优选实施例的芯片35的上表面上形成有四个端子。然而，并不限定芯片的端子的数量。即，可不同地改变芯片端子的数量。上述芯片35可以是在其一个表面上具有多个端子的常规集成电路芯片。
图3b更详细地描述本发明的芯片比例封装30的结构。参考图3a和3b，芯片35具有四个端子A、B、C和D。在除用于四个端子A、B、C和D的区域外的芯片35的上表面上形成绝缘层37。通常，如图3b所示，通过用在芯片35的上表面上的多个窗口覆盖掩膜图案36和通过掩膜图案36的窗口将金属材料附着在芯片35的外露端子区域上来形成端子区域。因此，在掩膜图案36上形成绝缘层37。
在绝缘层37的上表面上形成四个导电层，即第一、第二、第三和第四导电层31a、31b、31c和31d。将第一、第二、第三和第四导电层31a、31b、31c和31d连接到芯片35的上表面的四个端子A、B、C和D的每一个上。按指定距离使第一、第二、第三和第四导电层31a、31b、31c和31d彼此分开。优选地，第一、第二、第三和第四导电层31a、31b、31c和31d是用铜(Cu)制成的金属层，但不并局限于此。为将第一、第二、第三和第四导电层31a、31b、31c和31d连接到四个端子A、B、C和D的每一个上，优选地，用电镀方法填充绝缘层的空腔。然而，更优选地，用电镀法形成薄的电镀层以及在电镀层上堆叠至少一层铜层，从而具有指定的厚度。
在第一、第二、第三和第四导电层31a、31b、31c和31d的每个上表面上形成第一、第二、第三和第四电极面33a、33b、33c和33d。第一、第二、第三和第四电极面33a、33b、33c和33d用来电或机械连接到印刷电路板的相应的连接焊盘上。因此，优选地，第一、第二、第三和第四电极面33a、33b、33c和33d是具有良好的电导性的包括金(Au)的金属层以便接下来在第一、第二、第三和第四电极面33a、33b、33c和33d和印刷电路板的相应连接焊盘间进行焊接。
将第一、第二、第三和第四电极面33a、33b、33c和33d是印刷电路板上的安装表面。即，将上述芯片比例封装30旋转180度以及将旋转后的芯片比例封装30随后安装在印刷电路板上以便将第一、第二、第三和第四电极面33a、33b、33c和33d连接到印刷电路板的相应连接焊盘上。
可通过自然氧化在第一、第二、第三和第四导电层31a、31b、31c和31d的外露表面上形成氧化层。在这里，外露表面是第一、第二、第三和第四导电层31a、31b、31c和31d的侧面(在某些情况下，外露表面可以是第一、第二、第三和第四导电层31a、31b、31c和31d的未形成电极面的部分上表面。)这些氧化层是用作保护第一、第二、第三和第四导电层31a、31b、31c和31d免受氧化，从而确保第一、第二、第三和第四导电层31a、31b、31c和31d的可靠性的层。然而，为防止第一、第二、第三和第四导电层31a、31b、31c和31d严重氧化，可在除具有第一、第二、第三和第四电极面33a、33b、33c和33d的表面外的第一、第二、第三和第四导电层31a、31b、31c和31d上形成钝化层39。
优选地，钝化层39是通过涂上绝缘树脂形成的绝缘薄膜。如果必要的话，可在芯片35的外露侧面上形成钝化层39。
图4是芯片封装组件50的透视图，其中根据本发明的优选实施例，将芯片比例封装40安装在印刷电路板51上。
如图4所示，芯片封装组件50包括芯片比例封装40和用于安装芯片比例封装40的印刷电路板51。如图3a和3b所示，在芯片比例封装40中，在芯片45的上表面上形成绝缘层47。在绝缘层47的上表面上形成四个导电层，即第一、第二、第三导电层41a、41b和41c(未示出第四导电层)。将第一、第二、第三导电层41a、41b和41c(未示出第四导电层)连接到每个端子上。在第一、第二、第三导电层41a、41b和41c(未示出第四导电层)的每个上表面上形成四个电极面，即第一、第二、第三电极面43a、43b和43c(未示出第四电极面)。
通过将第一、第二、第三电极面43a、43b和43c(未示出第四电极面)布置在印刷电路板的相应连接焊盘53a、53b和53c(未示出其余一个)以及通过在第一、第二、第三电极面43a、43b和43c(未示出第四电极面)和连接焊盘53a、53b和53c(未示出其余一个)间执行焊接来将芯片比例封装40安装在印刷电路板51上，从而完成图4的芯片封装装置50的制造。
经具有第一、第二、第三电极面43a、43b和43c(未示出第四电极面)的第一、第二、第三导电层41a、41b和41c(未示出第四导电层)，将在印刷电路板51上形成的指定电路(未示出)电连接到芯片45的每个端子上。
另外，本发明提供了一种制造上述芯片比例封装的方法。图5a至5f是根据本发明的优选实施例，描述制造芯片比例封装的方法的每个步骤的透视图。
首先，如图5a所示，准备包括多个芯片的晶片101。在这里，用晶片101的上表面的虚线划分每个芯片。在晶片101的上表面上形成端子111。在除用于形成端子111外的晶片101的上表面上形成绝缘层117。如上所述，晶片101的每个芯片包括在其上表面上的四个端子。图5a部分表示晶片101。然而，对本领域的技术人员来说具有多个芯片和预定直径的晶片105的整个结构是显而易见的。
如图5b所示，在晶片101的绝缘层117的上表面上形成导电层121。在这里，在绝缘层117的上表面上形成导电层121以便将导电层121连接到外露的四个端子111上。因此，优选地，通过电镀方法形成导电层121。然而，如上所述，最优选地，通过形成电镀层以便填充没有绝缘层117的区域，然后通过将至少一层铜层堆叠在电镀层上来形成导电层121。导电层121可用铜(Cu)制成。
然后，如图5C所示，在导电层121的上表面上形成电极面123。电极面123是用具有良好电导性的包括金(Au)的金属制成的相当薄的层以便随后进行焊接。通过电镀法很容易形成电极面123。在形成电极面123后，沿图5C的线X1-X1′、X2-X2′、Y1-Y1′和Y2-Y2′去除部分导电层121，从而将具有电极面123的导电层121划分为多个部分。
因此，如图5d所示，将具有电极面123的导电层121划分成分别连接到每个相应端子的多个导电单元121′。导电单元121′充当连接到每个相应端子的端子部分。通过切割步骤很容易执行将导电层121划分成多个导电单元121′，其中控制刀片的切割深度。将切割深度设置为大于导电层121的厚度，但不到达芯片。在这里，在导电层121下的绝缘层117用来防止芯片受划分导电层121的损坏。
然后，如图5d所示，通过沿线A-A′和B-B′切割晶片101，将晶片101切成多个封装单元，从而获得如图5e所示的多个芯片比例封装130。通过控制切割深度，可同时完成划分导电层121的步骤和将晶片101切成多个封装130的步骤。
如图5f所示，可另外在除电极面123′外的导电层121′的外露表面上形成钝化层139。钝化层139用通过在导电层121′涂上绝缘树脂形成的绝缘薄膜制成。钝化层139用来防止导电层121′氧化，从而提高芯片比例封装140的可靠性。如果必要的话，根据芯片比例封装140的工作条件可省略钝化层139。
根据本发明，通过处理其具有多个端子的一个表面的一系列步骤来制造小型化芯片比例封装。另外，在本发明的范围和精神内可对本发明的芯片比例封装进行各种改变。即，尽管本发明的上述优选实施例公开了在其一个表面上具有四个端子的芯片，如果在芯片的一个表面上形成端子，可大大地改变或改进芯片端子的数量和排列。
如从上面的描述所看到的，本发明提供一种通过在芯片的一个表面上形成导电层以便连接到芯片的表面的每个端子上以及通过在导电层的上表面上形成电极面来小型化和更容易制造芯片比例封装，从而提高封装的可靠性。另外，本发明提供一种用于制造芯片比例封装的方法，其中省略常规的导线接合步骤或通孔形成步骤，从而简化制造过程和降低制造成本。
尽管为了说明目的公开了本发明的优选实施例，本领域的普通技术人员将意识到在不脱离由所附的权利要求书公开的本发明的范围和精神的情况下，可能做出各种改变、添加和代替。

Claims (26)

1.一种芯片比例封装，包括：
芯片，在其一个表面上具有多个端子；
绝缘层，形成在除用于多个端子区域外的芯片的表面上；
多个导电层，形成在绝缘层上并按指定距离将彼此分开以便连接到多个端子的每一个上；以及
多个电极面，形成在多个导电层的每个上表面上。
2.如权利要求1所述的芯片比例封装，其中以大致相同的厚度形成多个导电层，而且每个导电层具有平的上表面。
3.如权利要求1所述的芯片比例封装，进一步包括钝化层，每个形成在除具有电极面的上表面外的导电层的外露表面上。
4.如权利要求2所述的芯片比例封装，其中所述钝化层是用通过涂上绝缘树脂形成的绝缘薄膜制成。
5.如权利要求1所述的芯片比例封装，其中导电层是包括铜(Cu)的金属层。
6.如权利要求1所述的芯片比例封装，其中电极面是包括金(Au)的金属层。
7.如权利要求1所述的芯片比例封装，其中每个导电层包括用电镀层制成的第一层以及用堆叠在第一层上的至少一层铜层制成的第二层。
8.如权利要求1所述的芯片比例封装，其中芯片是在其一个表面上具有多个端子的集成电路芯片。
9.一种芯片比例封装组件，包括：
芯片比例封装，包括：
芯片，在其一个表面上具有多个端子；
绝缘层，形成在除用于多个端子区域外的芯片的表面上；
多个导电层，形成在绝缘层上并按指定距离将彼此分开以便连接到多个端子的每一个上；以及
多个电极面，形成在多个导电层的每个上表面上；以及
印刷电路板，包括：
多个连接焊盘，用于连接到芯片比例封装的每个电极面上；以及
电路图案，连接到每个连接焊盘上。
10.如权利要求9所述的芯片比例封装组件，其中以大致相同的厚度形成多个导电层，而且每个导电层具有平的上表面。
11.如权利要求9所述的芯片比例封装组件，进一步包括钝化层，每个形成在除具有电极面的上表面外的导电层的外露表面上。
12.如权利要求9所述的芯片比例封装组件，其中所述钝化层是用通过涂上绝缘树脂形成的绝缘薄膜制成。
13.如权利要求9所述的芯片比例封装组件，其中导电层是包括铜(Cu)的金属层。
14.如权利要求9所述的芯片比例封装组件，其中电极面是包括金(Au)的金属层。
15.如权利要求9所述的芯片比例封装组件，其中每个导电层包括用电镀层制成的第一层以及用堆叠在第一层上的至少一层铜层制成的第二层。
16.如权利要求9所述的芯片比例封装组件，其中芯片是在其一个表面上具有多个端子的集成电路芯片。
17.一种制造芯片比例封装的方法，所述方法包括步骤：
准备包括多个芯片的晶片，每个芯片包括在其一个表面上的多个端子；
在除用于形成端子的区域外的晶片的上表面上形成绝缘层；
在绝缘层的上表面上形成导电层以便连接到多个端子上；
在导电层的上表面上形成电极面；
将在绝缘层上形成的上导电层划分为两个多个部分以便连接到多个端子的每一个上；以及
将晶片切成多个封装单元。
18.如权利要求17所述的制造芯片比例封装的方法，进一步包括形成钝化层的步骤，每个钝化层形成在除具有电极面的上表面外的导电层的外露表面上。
19.如权利要求18所述的制造芯片比例封装的方法，其中所述钝化层是用通过涂上绝缘树脂形成的绝缘薄膜制成。
20.如权利要求17所述的制造芯片比例封装的方法，其中通过控制切割深度，同时执行将导电层划分为多个部分的步骤以及将晶片切成封装单元的步骤。
21.如权利要求17所述的制造芯片比例封装的方法，其中用电镀方法形成导电层。
22.如权利要求17所述的制造芯片比例封装的方法，其中导电层是包括铜(Cu)的金属层。
23.如权利要求17所述的制造芯片比例封装的方法，其中电极面是包括金(Au)的金属层。
24.如权利要求17所述的制造芯片比例封装的方法，其中通过使用电镀方法形成金属层以及通过在金属层上堆叠至少一层铜层来形成每个导电层。
25.如权利要求17所述的制造芯片比例封装的方法，其中用电镀方法形成电极面。
26.如权利要求17所述的制造芯片比例封装的方法，其中芯片是在其一个表面上具有多个端子的集成电路芯片。
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