CN101047167A - 具有贯通孔连接的半导体封装堆体 - Google Patents

具有贯通孔连接的半导体封装堆体 Download PDF

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CN101047167A
CN101047167A CNA2006101100271A CN200610110027A CN101047167A CN 101047167 A CN101047167 A CN 101047167A CN A2006101100271 A CNA2006101100271 A CN A2006101100271A CN 200610110027 A CN200610110027 A CN 200610110027A CN 101047167 A CN101047167 A CN 101047167A
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hole
encapsulation
substrate
package stack
package
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CN100541785C (zh
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郑永熙
李讃瑄
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SK Hynix Inc
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Abstract

本发明的封装堆体包括有至少两个堆叠在一起的封装，每一个封装具有一基板、设置在该基板上的电路图案、固定到该基板的半导体芯片和多个形成在侧面上的贯通孔。多个电连接构件固定到该贯通孔以彼此电连接封装。该贯通孔垂直设置在封装的侧面或端面。锡球固定到最下层封装的基板下表面。

Description

具有贯通孔连接的半导体封装堆体
技术领域
本发明涉及半导体封装，特别是使用贯通孔连接的半导体封装堆体。
背景技术
由于半导体集成电路封装技术的快速进步因此也要求体积更小以及可靠度更高的封装技术。随着芯片尺寸封装技术的快速进步，有些半导体封装的尺寸已经缩到与一般半导体芯片的大小差不多。因此改善半导体封装工艺效率与确保封装后机机械和电学可靠度是一样重要的。
随着，小型化和高性能化的要求，有人提出堆叠技术的概念。所谓″堆叠″一般是指将至少两个半导体芯片或封装垂直重叠。例如将两个256MDRAM堆叠形成一个512M DRAM。堆叠的封装可以通过每单位安装面积的增加的整体存储能力而提供更高安装密度。
图1是堆叠的传统FBGA(细间距球栅阵列)型封装的横截面图。在图1中，两个FBGA型封装10、20使用两个印刷电路板(PCB)22、24堆叠。两个封装10、20通过在下封装10周围插入在PCB 22、24之间连接壁26彼此电连接。
每个封装10(或20，下面分别在括号中示出)包括基板2(或12)；固定到基板2(或12)的半导体芯片1(或11)；一组电极端子3(或13)，设置在相应基板2(或12)上，电连接到各个半导体芯片1(或11)的一组焊盘1a(或11a)，例如一组键合线4(或14)；密封剂5(或15)，用于将基板2(或12)的上表面密封在包括键合线4(或14)的半导体芯片1(或11)上；和固定到各个基板2(或12)的下表面的一组锡球6(或16)。
封装10、20分别通过锡球6、16机械固定到对应的PCB 22、24并与PCB 22、24的各个电路图案23，25电连接。
为了使下层PCB 22可以安装在外部电路特别是主板上，下层PCB 22的下表面上具有另外的锡球28。
然而，根据这种传统封装堆体，在封装堆体之间至少需要两个PCB 22、24和连接壁26来进行电连接，因此会增加制造成本和缺陷率。
此外，传统封装堆体的基本结构是将两个封装叠在一起，因此会限制其小型化。
而且，连接PCB 22、24的连接壁例如26也需要空间，因此不容易缩小整体尺寸和封装面积。
附图说明
本发明的目的、特征和优点通过结合附图和后面的叙述将更明白清楚：
图1是传统封装堆体的横截面图；
图2和3分别是根据本发明实施例封装堆体的横截面和透视图；和
图4是根据本发明另一实施例的封装堆体透视图。
发明内容
因此，为了解决上述和其它习知技术所发生的问题，本发明的目的是提供一种可以降低制造成本和缺陷率的封装堆体。
本发明的另一目的是提供一种适合小型化的封装堆体。
本发明的另一目的是提供一种不需要额外空间，可以缩小整体尺寸和封装面积的封装堆体。
为了达成上述目的，本发明的封装堆体具有至少两个彼此堆叠的封装，每个封装具有：基板、设置在该基板上的电路图案、固定到该基板的半导体芯片和形成在侧面上的多个贯通孔；固定到该贯通孔以彼此电连接封装的多个电连接构件，该贯通孔垂直设置在封装的侧面上；以及固定到最下层封装基板下表面的锡球。
每个封装包括：具有电路图案的基板；固定到基板并电连接到基板的半导体芯片；密封包括半导体芯片的基板的上表面的密封剂；以及在包括基板的密封剂侧面上形成的多个贯通孔。
半导体芯片通过键合线或锡凸块与基板电连接。
贯通孔具有电镀表面，特别是电镀铜的表面
电连接构件为导电引线。
电连接构件通过焊锡固定到贯通孔。
基板上通过贯通孔暴露，使得电路图案电连接到导电引线。
封装堆体具有2-4个彼此堆叠的封装。
具体实施方式
接下来，本发明的优选实施例将参考相关图示加以说明。在接下来的说明和图示中，将使用相同的参考数字来表示相同或是类似的组件，并省略相同或类似组件的重复说明。
根据本发明实施例，当FBGA型封装彼此迭层在一起时，在每个封装的侧面会形成电镀贯通孔，而导电引线则设置在各个电镀贯通孔中以便在封装堆体间进行电连接。
由于本发明在进行封装迭层时，不需要增加额外的空间。因此可以缩小封装堆体的整体尺寸和厚度，达到目前半导体技术对于体积上的要求。此外，相较于习知技术，本发明在进行封装堆体时，既不使用基板也不使用连接壁，因此可以降低制造成本和缺陷率。
本发明实施例的封装堆体将参考图2-3的横截面图和透视图说明如下。图中，与图1中相同的参考数字表示相同的组件。
参考图2-3，封装堆体具有彼此迭在一起的FBGA型封装10、20和多个电连接构件，例如导电引线50以便电连接堆叠的封装10、20。
每个FBGA型封装10(或分别在括号中示出的20)分别包括：具有电路图案3(或13)的基板2(或12)；固定在各个基板2、12上并与基板电连接的半导体芯片1(或11)；和密封剂5(或15)，密封具有半导体芯片1和11的基板2、12上表面。特别是在包括基板2和12的密封剂5和15的侧面上形成多个贯通孔40(参考图3)。
半导体芯片1和11通过键合线4和14分别电连接到基板2和12，如果是覆晶键合模式时则使用锡凸块。
设置由包括基板2和12的密封剂5和15(参考第2图)的侧面形成的贯通孔40，以暴露基板2和12的电路图案3和13。因此，基板2和12的电路图案3和13优选设置在基板2和12侧面，因此可以如图2所示通过贯通孔40暴露出。
贯通孔40具有镀有高导电性的金属层例如铜层42的表面，在电镀层42上施加有焊锡44让导电引线50容易固定。
根据本发明实施例封装堆体的最下层封装10下表面上具有固定到其下表面的锡球30，以便可以安装在外部电路特别是主板上。
根据本发明实施例封装堆体的工艺说明如下。
首先以晶片水平制造多个FBGA型封装。然后多个贯通孔通过习知技术形成在晶片的切割线附近的以晶片水平制造的封装的侧面预定区域上。
形成贯通孔后，所得结构被依次进行沉积种子金属层的工艺、形成光敏层图案的工艺、电镀工艺、和去除感光层图形和下面种子金属层的工艺，使得每个贯通孔具有电镀有铜层的表面。
在每个贯通孔具有电镀铜层的表面后，沿着切割线将以晶片水平制造的封装切割成分离的封装。然后，具有电镀表面的贯通孔会暴露在外面。
将通过上述分离工艺获得的至少两个封装，堆叠在一起，让形成在侧面的贯通孔垂直排列。
然后，焊锡施加在已经垂直排列的封装的贯通孔内。导电引线通过使用焊锡固定在贯通孔内，该焊锡随后被湿润(wetting)使得贯通孔表面上的铜层与导电引线连结以达到封装堆体之间的电连接。
接着将锡球固定在最下层封装的下表面，完成本发明的封装堆体。
如上述，根据本发明实施例的封装堆体具有堆叠的封装，其在它们的侧面具有电镀贯通孔，和设置在垂直设置的封装的各个贯通孔内的导电引线，达到封装堆体之间的电连接。因此不需要额外的空间来进行封装堆体之间电连接。此外，贯通孔和导电引线可以取代传统PCB和连接壁。
因此，本发明的封装堆体相较于习知技术可以大幅缩小整体尺寸和厚度，因此实现了小型化。此外，省略昂贵的PCB和连接壁降低了制造成本和缺陷率。
虽然本实施例以两个FBGA型的封装堆体来进行说明，实际上可以根据需要使用更多个封装来进行堆叠。例如，可以使用四个彼此堆叠的FBGA型封装构成封装堆体，如图4所示。
如上所述，当制造根据本发明实施例的封装堆体时，贯通孔形成在封装的侧面，且导电引线设置在堆叠的封装的贯通孔内，以在堆叠封装之间电连接。因此，不需要额外的空间来在堆叠封装之间电连接，且可以省略昂贵的电连接部件。这实现了小型化并减少了制造成本和缺陷率。
本发明上述最佳实施例仅作为解释目的，任何熟悉此项技术的人员将理解，可以进行各种改进、附加或替换，而不脱离所附权利要求所限定的本发明的精神和范畴。

Claims (9)

1.一种封装堆体，具有至少两个堆叠在一起的封装，每个封装包括：
基板，其上具有电路图案；
半导体芯片，固定并电连接到所述基板，和
多个贯通孔，形成在封装侧面的预定部分上，
其中一个封装的每个贯通孔与另一堆叠的封装的相应贯通孔对准，以在两个堆叠的封装的侧面上形成连续的贯通孔；
多个电连接构件，每个固定到两个堆叠封装侧面上的每个连续贯通孔，以彼此电连接两个封装，每个连续的贯通孔垂直设置在堆叠封装侧面的预定部分上；以及
固定到最下层封装的基板下表面的锡球。
2.如权利要求1所述的封装堆体，其中每个封装还包括：
密封剂，密封包括半导体芯片的基板的上表面，
其中密封剂在所述侧面成形以提供所述贯通孔。
3.如权利要求2所述的封装堆体，其中所述半导体芯片通过多个键合线或锡凸块电连接到基板，其中所述多个键合线或锡凸块连接到形成在基板上的相应电极端子，且其中电极端子的一部分设置在相应于连续贯通孔的基板侧面的预定区域。
4.如权利要求3所述的封装堆体，其中每个连续的贯通孔表面具有接触电极端子的电镀表面。
5.如权利要求4所述的封装堆体，其中的贯通孔具有镀铜的表面。
6.如权利要求1所述的封装堆体，其中的电连接构件为导电引线。
7.如权利要求1所述的封装堆体，其中电连接构件通过焊锡固定到贯通孔。
8.如权利要求1所述的封装堆体，其中基板由贯通孔暴露出来使得电路图案电连接到导电引线。
9.如权利要求1所述的封装堆体，其中2至4个封装堆叠在一起。
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