JP4979320B2 - 半導体ウェハおよびその製造方法、ならびに半導体装置の製造方法 - Google Patents
半導体ウェハおよびその製造方法、ならびに半導体装置の製造方法 Download PDFInfo
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- JP4979320B2 JP4979320B2 JP2006265873A JP2006265873A JP4979320B2 JP 4979320 B2 JP4979320 B2 JP 4979320B2 JP 2006265873 A JP2006265873 A JP 2006265873A JP 2006265873 A JP2006265873 A JP 2006265873A JP 4979320 B2 JP4979320 B2 JP 4979320B2
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Description
本発明は、LSIの製造初期段階において、貫通電極を形成する位置に筒状(円筒状等)のトレンチをドライエッチングにより形成する工程と、CVD法により形成したトレンチ部分を絶縁材料(SiO2等)で充填すると同時に、基板(Si基板等)表面を絶縁する工程と、トランジスタのゲート電極部を形成するPoly−Si膜を形成するのと同時に、トレンチ部表面にもPoly−Si膜を形成する工程と、その上部に外部接続電極と電気的に接続するための柱状配線ビアが形成する工程からなる。
図1は、本発明の実施の形態1である半導体ウェハの要部を示す平面図(a)と、そのA−A切断線による断面図(b)である。
図18,図19は、本発明の実施の形態2である半導体ウェハの要部を示す平面図(a)と、そのA−A切断線による断面図(b)である。
図20〜図26は、本発明の実施の形態3である半導体ウェハを用いた半導体装置の各製造工程を示す図(平面図、断面図)である。
図27は、前記実施の形態1〜3によるLSI製造プロセスと通常のLSI製造プロセスとを比較して示す図である。
図28,図29は、前記実施の形態1〜3により形成された、貫通電極並びに金のスタッドバンプを有するLSIチップやインターポーザチップを電気的に接続する方法を示す図である。
以上説明したように、前記実施の形態1〜3によれば、以下のような効果を得ることができる。
Claims (19)
- シリコンウェハの貫通電極を形成する位置に形成された筒状の溝トレンチと、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に埋め込まれた絶縁部材と、
前記絶縁部材の上面に形成された導電性膜と、
前記導電性膜の上面に形成された導電部材と、
前記導電性膜に前記導電部材を介して電気的に接続されて形成された外部接続電極とを有することを特徴とする半導体ウェハ。 - 請求項1記載の半導体ウェハにおいて、
前記導電性膜は、半導体製造プロセス中に形成された複数の導電性膜からなり、
前記導電部材は、前記半導体製造プロセス中の多層配線や層間絶縁膜の成膜過程において形成された多段の柱状配線ビアからなることを特徴とする半導体ウェハ。 - シリコンウェハの貫通電極を形成する位置に筒状の溝トレンチを形成する工程と、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に絶縁部材を埋め込む工程と、
前記絶縁部材の上面に導電性膜を形成する工程と、
前記導電性膜の上面に導電部材を形成する工程と、
前記導電性膜に前記導電部材を介して電気的に接続された外部接続電極を形成する工程とを有することを特徴とする半導体ウェハの製造方法。 - 請求項3記載の半導体ウェハの製造方法において、
前記導電性膜を形成する工程は、半導体製造プロセス中に複数の導電性膜を形成し、
前記導電部材を形成する工程は、前記半導体製造プロセス中の多層配線や層間絶縁膜の成膜過程において多段の柱状配線ビアを形成することを特徴とする半導体ウェハの製造方法。 - 請求項1記載の半導体ウェハを用いた半導体装置の製造方法であって、
前記半導体ウェハを裏面から薄型化して、前記溝トレンチの内部に埋め込まれた絶縁部材を露出させる工程と、
前記溝トレンチの内部および上面の絶縁部材をウェットエッチング処理により溶解させる工程と、
前記溝トレンチの内面側のシリコン片を脱落させて前記導電性膜に達するシリコン孔部を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法であって、
前記シリコン孔部の内面および前記半導体ウェハの裏面の全面に絶縁膜を成膜する工程と、
前記シリコン孔部の底辺部の前記絶縁膜を除去して、前記導電性膜を露出させる工程と、
前記シリコン孔部の内面および前記半導体ウェハの裏面の所定の領域に電解メッキのためのシード層、並びに電解メッキ膜を形成して、前記外部接続電極と電気的に接続された貫通電極を形成する工程とをさらに有することを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記絶縁部材を露出させる工程から前記シリコン孔部を形成する工程は、前記半導体ウェハを支持体に貼り付けた状態で実施し、製造終了後に前記半導体ウェハは前記支持体から分離されることを特徴とする半導体装置の製造方法。 - シリコンウェハの貫通電極を形成する位置に筒状の溝トレンチを形成する工程と、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に絶縁部材を埋め込む工程と、
前記絶縁部材の上面に導電性膜を形成する工程と、
前記導電性膜の上面に導電部材を形成する工程と、
前記導電性膜に前記導電部材を介して電気的に接続された外部接続電極を形成する工程と、
前記シリコンウェハを裏面から薄型化して、前記溝トレンチの内部に埋め込まれた絶縁部材を露出させる工程と、
前記溝トレンチの内部および上面の絶縁部材をウェットエッチング処理により溶解させる工程と、
前記溝トレンチの内面側のシリコン片を脱落させて前記導電性膜に達するシリコン孔部を形成する工程と、
前記シリコン孔部の内面および前記シリコンウェハの裏面に絶縁膜を成膜する工程と、
前記シリコン孔部の底辺部のみ前記絶縁膜を除去して、前記導電性膜を露出させる工程と、
前記シリコン孔部の内面および前記シリコンウェハの裏面の所定の領域に電解メッキのためのシード層、並びに電解メッキ膜を形成して、前記外部接続電極と電気的に接続された貫通電極を形成する工程とを有することを特徴とする半導体装置の製造方法。 - シリコンウェハの貫通電極を形成する位置に形成された筒状の溝トレンチと、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に埋め込まれた絶縁部材と、
前記絶縁部材の上面に形成された導電性膜と、
前記導電性膜の上面に形成された導電部材と、
前記導電性膜に前記導電部材を介して電気的に接続されて形成されたLSI内部のI/O配線、または電源配線、またはグランド配線とを有することを特徴とする半導体ウェハ。 - 請求項9記載の半導体ウェハにおいて、
前記導電性膜は、半導体製造プロセス中に形成された複数の導電性膜からなり、
前記導電部材は、前記半導体製造プロセス中の多層配線や層間絶縁膜の成膜過程において形成された多段の柱状配線ビアからなることを特徴とする半導体ウェハ。 - シリコンウェハの貫通電極を形成する位置に筒状の溝トレンチを形成する工程と、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に絶縁部材を埋め込む工程と、
前記絶縁部材の上面に導電性膜を形成する工程と、
前記導電性膜の上面に導電部材を形成する工程と、
前記導電性膜に前記導電部材を介して電気的に接続されたLSI内部のI/O配線、または電源配線、またはグランド配線を形成する工程とを有することを特徴とする半導体ウェハの製造方法。 - 請求項11記載の半導体ウェハの製造方法において、
前記導電性膜を形成する工程は、半導体製造プロセス中に複数の導電性膜を形成し、
前記導電部材を形成する工程は、前記半導体製造プロセス中の多層配線や層間絶縁膜の成膜過程において多段の柱状配線ビアを形成することを特徴とする半導体ウェハの製造方法。 - 請求項9記載の半導体ウェハを用いた半導体装置の製造方法であって、
前記半導体ウェハを裏面から薄型化して、前記溝トレンチの内部に埋め込まれた絶縁部材を露出させる工程と、
前記溝トレンチの内部および上面の絶縁部材をウェットエッチング処理により溶解させる工程と、
前記溝トレンチの内面側のシリコン片を脱落させて前記導電性膜に達するシリコン孔部を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法であって、
前記シリコン孔部の内面および前記半導体ウェハの裏面の全面に絶縁膜を成膜する工程と、
前記シリコン孔部の底辺部のみ前記絶縁膜を除去して、前記導電性膜を露出させる工程と、
前記シリコン孔部の内面および前記半導体ウェハの裏面の所定の領域に電解メッキのためのシード層、並びに電解メッキ膜を形成して、前記外部接続電極と電気的に接続された貫通電極を形成する工程とをさらに有することを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記絶縁部材を露出させる工程から前記シリコン孔部を形成する工程は、前記半導体ウェハを支持体に貼り付けた状態で実施し、製造終了後に前記半導体ウェハは前記支持体から分離されることを特徴とする半導体装置の製造方法。 - シリコンウェハの貫通電極を形成する位置に筒状の溝トレンチを形成する工程と、
前記溝トレンチの内部および前記溝トレンチで囲まれたシリコンウェハの上面に絶縁部材を埋め込む工程と、
前記絶縁部材の上面に導電性膜を形成する工程と、
前記導電性膜の上面に導電部材を形成する工程と、
前記導電性膜に前記導電部材を介して電気的に接続されたLSI内部のI/O配線、または電源配線、またはグランド配線を形成する工程と、
前記シリコンウェハを裏面から薄型化して、前記溝トレンチの内部に埋め込まれた絶縁部材を露出させる工程と、
前記溝トレンチの内部および上面の絶縁部材をウェットエッチング処理により溶解させる工程と、
前記溝トレンチの内面側のシリコン片を脱落させて前記導電性膜に達するシリコン孔部を形成する工程と、
前記シリコン孔部の内面および前記シリコンウェハの裏面の全面に絶縁膜を成膜する工程と、
前記シリコン孔部の底辺部のみ前記絶縁膜を除去して、前記導電性膜を露出させる工程と、
前記シリコン孔部の内面および前記シリコンウェハの裏面の所定の領域に電解メッキのためのシード層、並びに電解メッキ膜を形成して、前記外部接続電極と電気的に接続された貫通電極を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体ウェハにおいて、
前記外部接続電極上にウェハレベルで形成された金バンプをさらに有することを特徴とする半導体ウェハ。 - 請求項1記載の半導体ウェハにおいて、
前記シリコンウェハのスクライブエリア内に形成された溝トレンチと、
前記溝トレンチの内部および上面に埋め込まれた絶縁部材とをさらに有することを特徴とする半導体ウェハ。 - 請求項6記載の半導体装置の製造方法において、
前記貫通電極が形成された前記半導体ウェハを各チップサイズに個片化する工程と、
前記個片化した各チップの外部接続電極上に金バンプを形成する工程とを有し、
前記貫通電極を有する第1のチップ上に、前記金バンプを有する第2のチップを積層する際には、前記第2のチップの金バンプを前記第1のチップの貫通電極の内部に押し込み、機械的にかしめることによって、積層チップ間を電気的に接続することを特徴とする半導体装置の製造方法。
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US11/891,458 US20080079152A1 (en) | 2006-09-28 | 2007-08-10 | Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device |
US12/823,913 US7897509B2 (en) | 2006-09-28 | 2010-06-25 | Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device |
US13/030,098 US20110133336A1 (en) | 2006-09-28 | 2011-02-17 | Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device |
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FR2910705B1 (fr) * | 2006-12-20 | 2009-02-27 | E2V Semiconductors Soc Par Act | Structure de plots de connexion pour capteur d'image sur substrat aminci |
US7939942B2 (en) * | 2007-12-19 | 2011-05-10 | Infineon Technologies Ag | Semiconductor devices and methods of manufacturing thereof |
JP2009181981A (ja) | 2008-01-29 | 2009-08-13 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US7821107B2 (en) * | 2008-04-22 | 2010-10-26 | Micron Technology, Inc. | Die stacking with an annular via having a recessed socket |
JP5455538B2 (ja) * | 2008-10-21 | 2014-03-26 | キヤノン株式会社 | 半導体装置及びその製造方法 |
JP2010103300A (ja) * | 2008-10-23 | 2010-05-06 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US8697569B2 (en) * | 2010-07-23 | 2014-04-15 | Tessera, Inc. | Non-lithographic formation of three-dimensional conductive elements |
US20120193809A1 (en) * | 2011-02-01 | 2012-08-02 | Nanya Technology Corp. | Integrated circuit device and method for preparing the same |
JP5970696B2 (ja) * | 2012-03-27 | 2016-08-17 | セイコーエプソン株式会社 | 電子デバイスの製造方法、電子デバイス |
US9064933B2 (en) | 2012-12-21 | 2015-06-23 | Invensas Corporation | Methods and structure for carrier-less thin wafer handling |
KR102473664B1 (ko) | 2016-01-19 | 2022-12-02 | 삼성전자주식회사 | Tsv 구조체를 가진 다중 적층 소자 |
JP6412179B2 (ja) * | 2017-02-03 | 2018-10-24 | ファナック株式会社 | 加工機に対して移動ロボットが物品の搬入及び搬出を行う加工システム、及び機械制御装置 |
EP3364454B1 (en) * | 2017-02-15 | 2022-03-30 | ams AG | Semiconductor device |
CN108346639B (zh) * | 2017-09-30 | 2020-04-03 | 中芯集成电路(宁波)有限公司 | 一种晶圆级系统封装方法以及封装结构 |
CN110246801B (zh) * | 2018-03-07 | 2021-07-16 | 长鑫存储技术有限公司 | 连接结构及其制造方法、半导体器件 |
US10861821B2 (en) | 2018-05-03 | 2020-12-08 | Ningbo Semiconductor International Corporation | Packaging method and package structure of wafer-level system-in-package |
US10755956B2 (en) | 2019-01-25 | 2020-08-25 | Semiconductor Components Industries, Llc | Backside wafer alignment methods |
US20200266169A1 (en) | 2019-02-19 | 2020-08-20 | Tokyo Electron Limited | Replacement buried power rail in backside power delivery |
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JP4850392B2 (ja) * | 2004-02-17 | 2012-01-11 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100568452B1 (ko) * | 2004-09-23 | 2006-04-07 | 삼성전자주식회사 | 얼라인먼트 키를 갖는 반도체 소자의 제조방법 및 그에의하여 제조된 반도체 소자. |
JP2006108244A (ja) * | 2004-10-01 | 2006-04-20 | Sharp Corp | 半導体装置の製造方法 |
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US20080079152A1 (en) | 2008-04-03 |
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