CN1941340A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1941340A
CN1941340A CNA200610131718XA CN200610131718A CN1941340A CN 1941340 A CN1941340 A CN 1941340A CN A200610131718X A CNA200610131718X A CN A200610131718XA CN 200610131718 A CN200610131718 A CN 200610131718A CN 1941340 A CN1941340 A CN 1941340A
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pad electrode
semiconductor substrate
semiconductor device
electronic circuit
hole
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CN100466243C (zh
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森田佑一
石部真三
野间崇
大塚久夫
高尾幸弘
金森宽
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L2924/04941—TiN

Abstract

本发明涉及半导体装置及其制造方法，防止半导体装置的外部连接用的焊盘电极受到损伤。在半导体基板(1)上形成电子电路(30)、与电子电路(30)连接的第一焊盘电极(3)、与第一焊盘电极(3)连接的第二焊盘电极(4)。此外，形成覆盖第一焊盘电极(3)并且只在第二焊盘电极(4)上具有开口部的第一保护膜(5)。并且，形成通过贯通半导体基板(1)的通孔(8)连接在第一焊盘电极(3)的背面并从通孔(8)延伸到半导体基板(1)的背面的布线层(10)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，具体是涉及具有贯通半导体基板的通孔的半导体装置及其制造方法。
背景技术
近年来，作为新的封装技术，CSP(Chip Size Package)受到关注。所谓CSP是指具有与半导体芯片的外形尺寸大致相同的外形尺寸的小型封装。作为CSP的一种，BGA(Ball Grid Array)型的半导体装置为人们所知。
这种半导体装置具有通过贯通半导体基板的通孔与其表面的焊盘连接的布线层。在该半导体基板的背面格子状地配置有多个由焊料等的金属材料构成的球状的导电端子，这些导电端子通过布线层与所述焊盘电极连接。并且，在将该半导体装置组装到电子设备上时，将各导电端子连接在电路基板例如印刷基板上的布线图案上。
BGA型半导体装置与具有向侧部突出的引线脚的SOP(Small OutlinePackage)或QFP(Quad Flat Package)等的其它CSP型半导体装置相比，能够设置多个导电端子，并且具有能够使其尺寸小型化的优点。
图8及图9是表示BGA型的半导体装置的结构及制造方法的剖面图，特别表示了焊盘电极的周围。如图8所示，在半导体基板50的表面介由第一绝缘膜51形成焊盘电极52，在该焊盘电极52上形成具有开口部并覆盖第一绝缘膜51及焊盘电极52的端部的第一保护膜53。焊盘电极52与在半导体基板50上形成的未图示的电子电路连接，通过该焊盘电极52在所述电子电路与外部电路之间进行信号的交换。
经过半导体晶片加工，在半导体基板50上制成电子电路后，测试该电子电路是否正常工作。此时，通过设置在第一保护膜53上的开口部，测定针54与焊盘电极52的表面接触。在图8中，只表示了一个焊盘电极52，但实际上在半导体基板50上同样形成了多个焊盘电极52。测定针54与LSI测试器连接。并且，从LSI测试器通过测定针54、焊盘电极52向电子电路传送测试信号，LSI测试器100在逆向通路接收来自电子电路的响应信号，由此，能够进行电子电路的测试测定。
上述测试测定结束的半导体基板50被送往后面的工序，形成通孔、布线、球状的导电端子等。即，如图9所示，在半导体基板50的表面介由粘接用的树脂膜55粘贴用于支承半导体基板50的玻璃基板56。之后，形成贯通半导体基板50的通孔57，形成覆盖通孔57的侧壁及半导体基板50的背面的第二绝缘膜58，在其上形成通过通孔57与焊盘电极52的背面连接并延伸到半导体基板50的背面的布线层59。并且，形成覆盖半导体基板50的背面并在布线层59上具有开口部的第二保护膜60，形成通过该开口部与布线层59连接的球状的导电端子61。
专利文献1：特开2003-309221号公报
然而，存在这样的问题，即，在上述的BGA型半导体装置上，在电子电路测试时，由于测定针54的尖端部压触在焊盘电极52上，所以使焊盘电极52被损伤，由于该损伤使得水分容易侵入，而腐蚀焊盘电极52。
另外，由于在焊盘电极52上设置了第一保护膜53的开口部K，所以通孔57形成后焊盘电极52的上下方向的固定变得不稳定，受通孔57形成后的热处理的影响，在焊盘电极52的中央部产生弯曲，严重的情况产生龟裂等问题。列举热处理影响的具体例子，在用光敏抗蚀剂那样的有机膜形成第二绝缘膜58的情况下，为了使其固化而进行烘烤处理。此时，引起第二绝缘膜58收缩，对焊盘电极52产生向下方拉应力。由于该拉应力使得在焊盘电极52的中央部产生弯曲。
发明内容
本发明的半导体装置，其特征在于，具有：半导体基板；形成在所述半导体基板上的电子电路；第一焊盘电极，其形成在所述半导体基板上并与所述电子电路连接；第二焊盘电极，其形成在所述半导体基板上并与所述第一焊盘电极连接；保护膜，其覆盖所述第一焊盘电极并且只在所述第二焊盘电极上具有开口部；以及布线层，其通过贯通所述半导体基板的通孔与所述第一焊盘电极的背面连接并从所述通孔延伸到所述半导体基板的背面。
此外，本发明的半导体装置的制造方法，其特征在于，具有如下工序：准备半导体基板，在其表面形成电子电路、与该电子电路连接的第一焊盘电极以及与该第一焊盘电极连接的第二焊盘电极，并形成覆盖所述第一焊盘电极并且只在所述第二焊盘电极的表面具有开口部的保护膜；在与所述第一焊盘电极对应的位置形成贯通所述半导体基板的通孔的工序；以及形成布线层的工序，该布线层通过所述通孔与所述第一焊盘电极的背面连接并从所述通孔延伸到所述半导体基板的背面。
根据本发明，由于设置了与第一焊盘电极连接的第二焊盘电极，所以通过将第二焊盘电极作为电子电路测定用的焊盘使用，能够防止连接用的第一焊盘电极被损伤而腐蚀。另外，由于将第二焊盘电极作为电子电路测定用的焊盘使用，所以没有必要在第一焊盘电极上设置第一保护膜的开口部，因此，使第一焊盘电极被第一保护膜所覆盖而被稳定地固定。由此，消除了形成通孔后的热处理的影响，解决了第一焊盘电极的弯曲的问题。
附图说明
图1是本发明的实施例的半导体装置的整体平面图；
图2是图1的用虚线包围部分的放大图；
图3是沿着图2的X-X线的剖面图；
图4是表示本发明的实施例的半导体装置的制造方法的剖面图；
图5是表示本发明的实施例的半导体装置的制造方法的剖面图；
图6是表示本发明的实施例的半导体装置的制造方法的剖面图；
图7是表示本发明的实施例的半导体装置的制造方法的剖面图；
图8是表示现有例的半导体装置的制造方法的剖面图。
图9是表示现有例的半导体装置的制造方法的剖面图；
标记说明
1半导体基板；2第一绝缘膜；3第一焊盘电极；4第二焊盘电极；5第一保护膜；6树脂层；7支承体；8通孔；9第二绝缘膜；10布线层；11第二保护膜；12导电端子；20，21布线；30电子电路；50半导体基板；51第一绝缘膜；52焊盘电极；53第一保护膜；54测定针；55树脂膜；56玻璃基板；57通孔；58第二绝缘膜；59布线层；60第二保护膜；61导电端子；100 LSI测试器；K开口部。
具体实施方式
下面，对本发明的实施例参照附图进行说明。图1是晶片加工结束阶段的半导体装置的整体平面图，图2是图1的用虚线包围部分的放大图，图3是沿着图2的X-X线的剖面图。
如图1及图2所示，在由硅等构成的半导体基板1的表面形成电子电路30(半导体集成电路)、第一焊盘电极3、与第一焊盘电极3邻接配置并通过布线20连接的第二焊盘电极4。第一焊盘电极3是外部连接用的焊盘，通过布线21与电子电路30连接。即，通过第一焊盘电极3在电子电路30与外部电路之间进行信号的交换。第二焊盘电极4是电子电路30测定用的焊盘。电子电路30可以是例如CCD(Charge Coupled Device)、红外线传感器等的感光元件或者发光元件，也可以是除此之外的电子电路。
此外，如图3的剖面图所示，第一焊盘电极3及第二焊盘电极4在第一绝缘膜2上形成，该第一绝缘膜2以热氧化等形成在半导体基板1的表面。另外，第一焊盘电极3及第二焊盘电极4通过溅射例如铝(Al)形成，优选的是具有大约1μm的膜厚。第一绝缘膜2由例如氧化硅膜构成，优选的是具有大约0.8μm的膜厚。
此外，覆盖第一绝缘膜2及第一焊盘电极3并覆盖第二焊盘电极4的端部利用CVD法等形成具有使第二焊盘电极4的表面露出的开口部K的第一保护膜5。第一保护膜5是由例如氮化硅膜构成的钝化膜。
并且，通过第一保护膜5的开口部K使测定针54与第二焊盘电极4的表面接触而测试电子电路30是否正常工作。测定针54连接在LSI测试器100上。并且，通过测定针54、第二焊盘电极4、第一焊盘电极3将测试信号从LSI测试器100传送到电子电路30，LSI测试器100在逆向通路接收来自电子电路30的响应信号，由此，能够进行电子电路30的测试测定。此时，由于测定针54的尖端部压触在第二焊盘电极4上，所以虽然第二焊盘电极4被损伤，但第一焊盘电极3保持无损伤。因此，即使第二焊盘电极4由于损伤而腐蚀，而第一焊盘电极3也会不被腐蚀，所以能够毫无问题地发挥作为外部连接用端子的功能。
该测试测定后，如图4所示，在半导体基板1的表面根据需要形成支承体7。该支承体7介由树脂层6在半导体基板1的表面形成。这里，在电子电路30是感光元件或发光元件的情况下，支承体7由具有例如玻璃那样的透明或半透明性质的材料形成。在电子电路30不是感光元件或发光元件的情况下，支承体7可以由不具有透明或者半透明的性质的材料形成。另外，支承体7可以是带状的。该支承体7可以在后面的工序被除去。或者，支承体7可以不被除去而残留。
接着，如图5所示，从背面有选择地蚀刻半导体基板1(优选为干式蚀刻)，对半导体基板1进行蚀刻。当半导体基板1由硅构成时，作为干式蚀刻的蚀刻气体能够使用CHF3。由该蚀刻形成将与第一焊盘电极3对应位置的半导体基板1从该背面到该表面贯通的通孔8。在通孔8的底部露出第一绝缘膜2，在其下方第一焊盘电极3呈连接状态。并且，进而利用干式蚀刻或湿式蚀刻对在通孔8的底部露出的第一绝缘膜2进行蚀刻而使其变薄或完全除去。或者，第一绝缘膜2的蚀刻工序可以不在该阶段进行，而与后述的其它蚀刻工序同时进行。
接着，在包含通孔8的内部在内的半导体基板1的背面的整个面上形成第二绝缘膜9。其中，第二绝缘膜9是例如光敏抗蚀剂那样的有机膜。这种情况，在第二绝缘膜9形成后，进行用于使其固化的烘烤处理。此时，第二绝缘膜9收缩，虽然对第一焊盘电极3产生拉应力的影响，但由于第一保护膜5与第一焊盘电极3的表面紧密结合，所以拉应力由第一保护膜5消除，防止了第一焊盘电极3弯曲。之后，第二绝缘膜9通过曝光、显影而被图案形成，通孔8的底部的第二绝缘膜9被除去，露出第一焊盘电极3的背面。第二绝缘膜9残存在第一半导体基板1的背面及通孔8的侧壁。
另外，第二绝缘膜9由氧化硅膜(SiO2膜)或者氮化硅膜(SiN膜)形成，可以由例如等离子CVD法形成。这种情况，在第二绝缘膜9上形成无图示的抗蚀剂膜层，把该抗蚀剂膜层作为掩模，将通孔8的底部的第二绝缘膜9(第一绝缘膜2残存时也包括该膜)蚀刻除去。该蚀刻虽然优选是例如反应性离子蚀刻，但也可以是其它的蚀刻。利用上述蚀刻能够残存在通孔8的侧壁形成的第二绝缘膜9，同时除去该底部的第一绝缘膜2而露出第一焊盘电极3的背面。
接着，如图6所示，形成通过通孔8连接到第一焊盘电极3的背面并从通孔8延伸到半导体基板1的背面的布线层10。布线层10能够利用铝等金属溅射法和利用其后的有选择地蚀刻而形成。另外，布线层10也可以利用电解镀法形成。这种情况，在包含通孔8的半导体基板1的背面的第二绝缘膜9上形成籽晶层(シ一ド層)，在该籽晶层上利用电解镀法形成由铜构成的布线层10。镀膜厚调整成使布线层10完全或不完全埋入通孔8内那样的厚度。所述籽晶层例如将钨化钛(TiW)层、氮化钛(TiN)层或者氮化钽(TaN)层等金属层和铜(Cu)等金属层层叠构成。籽晶层例如由溅射法、CVD法、无电解镀法、或者其它成膜方法形成。另外，在通孔8的侧壁的第二绝缘膜9由氮化硅膜(SiN膜)形成的情况下，该氮化硅(SiN膜)成为对于铜扩散的阻挡层，所以，籽晶层可以具有由铜(Cu)构成的单层结构。
接着，如图7所示，在半导体基板1的背面上形成由例如焊剂抗蚀剂那样的抗蚀剂材料构成的第二保护膜11。在第二保护层11中的布线层10的一部分上设置开口部。并且，在从该开口部露出的布线层10上使用丝网印刷法形成由例如焊料等金属构成的球状的导电端子12，从而构成BGA型半导体装置。
另外，在本发明的半导体装置是LGA(Land Grid Array)型的情况下，没有必要在从第二保护层11局部露出的布线层10的一部分上形成导电端子12。

Claims (8)

1、一种半导体装置，其特征在于，具有：
半导体基板；
形成在所述半导体基板上的电子电路；
第一焊盘电极，其形成在所述半导体基板上并与所述电子电路连接；
第二焊盘电极，其形成在所述半导体基板上并与所述第一焊盘电极连接；
保护膜，其覆盖所述第一焊盘电极并且只在所述第二焊盘电极上具有开口部；以及
布线层，其通过贯通所述半导体基板的通孔与所述第一焊盘电极的背面连接，并从所述通孔延伸到所述半导体基板的背面。
2、如权利要求1所述的半导体装置，其特征在于，
在所述半导体基板上粘贴有支承体。
3、如权利要求1所述的半导体装置，其特征在于，
在所述支承体与所述半导体基板之间介入粘接层。
4、如权利要求1所述的半导体装置，其特征在于，
在所述布线层上形成有导电端子。
5、一种半导体装置的制造方法，其特征在于，具有如下工序：
准备半导体基板，在其表面形成电子电路、与该电子电路连接的第一焊盘电极以及与该第一焊盘电极连接的第二焊盘电极，并形成覆盖所述第一焊盘电极并且只在所述第二焊盘电极的表面具有开口部的保护膜；
在与所述第一焊盘电极对应的位置形成贯通所述半导体基板的通孔的工序；以及
形成布线层的工序，该布线层通过所述通孔与所述第一焊盘电极的背面连接并从所述通孔延伸到所述半导体基板的背面。
6、如权利要求5所述的半导体装置的制造方法，其特征在于，
具有使测定针通过所述开口部与所述第二焊盘电极接触而进行所述电子电路的测定的工序。
7、如权利要求5所述的半导体装置的制造方法，其特征在于，
具有在所述半导体基板上粘贴支承体的工序。
8、如权利要求5所述的半导体装置的制造方法，其特征在于，
具有在所述布线层上形成导电端子的工序。
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