CN101159252A - 焊盘结构及其形成方法 - Google Patents

焊盘结构及其形成方法 Download PDF

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CN101159252A
CN101159252A CNA2007101021715A CN200710102171A CN101159252A CN 101159252 A CN101159252 A CN 101159252A CN A2007101021715 A CNA2007101021715 A CN A2007101021715A CN 200710102171 A CN200710102171 A CN 200710102171A CN 101159252 A CN101159252 A CN 101159252A
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layer
metal
protective layer
pad
engaging zones
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CN100539099C (zh
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林亮臣
曹佩华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种焊盘结构及其形成方法，上述焊盘结构包括第一含金属层，形成于基板上以及第一保护层，形成于该第一含金属层上，该第一保护层具有第一开口，其露出部分第一含金属层。上述焊盘结构还包括焊盘层，形成于该第一保护层上，且覆盖该第一开口，该焊盘层包括探测区域以及接合区域，该探测区域用来接触探针，而该接合区域用来接合导线，其中该探测区域经由该第一开口与该第一含金属层接触，该接合区域位于部分的该第一保护层的上方。

Description

焊盘结构及其形成方法
技术领域
本发明涉及一种半导体结构以及半导体结构的形成方法，特别涉及焊盘结构及焊盘结构的形成方法。
背景技术
随着电子产品的发展，半导体的技术已广泛地应用于存储器、中央处理器(CPU)、液晶显示器(LCD)、发光二极管(LED)、激光二极管以及其他元件或者芯片组的制造。为了达成高集成度以及高速度的目的，半导体集成电路的尺寸必须不断地缩小。已提出各种的材料和技术来达成上述高集成度与高速度的目的，并且克服与此相关的制造阻碍。为了降低晶粒尺寸，可在下方形成有有源、功能性元件或电路的上方区域形成焊盘，而不限于晶粒的周边区域。
一般而言，在探测步骤时，上方形成有焊盘的芯片会进行电子测试。此探测步骤会使用探针碰触或接触焊盘以搜集连接于焊盘的元件或电路的电子特性。如果元件或电路的电子特性为先前定义可接受的值，则会通过接合导线将此芯片与其他的基板封装而结合，其他的基板例如为印刷电路板(PCB)。每一个接合导线连接于个别焊盘的上方。因此，在探测步骤以及连接步骤，焊盘分别被施以探测力与接合力。
假如焊盘的尺寸缩小，接合导线可能会连接于被探针所损伤的焊盘的区域上方。介于焊盘以及接合导线的接触面必须进行后续的测试，例如可靠度测试。此外，被施以探针测试与接合步骤的上述焊盘的同一区域可能无法承受此两者结合的力。因此，有人提出一种焊盘下方电路(circuit under pad；CUP)结构，其包括探测区域与接合区域，可以分别承受探测力与接合力，以解决上述的问题。
图1A为已知的CUP结构剖面图。在此图中，接触孔113、123与135以及金属层115、125与150依序地形成于基板100的上方。分别于基底100与金属层115之间、金属层115与125之间以及金属层125与150之间，依序地形成介电层110、120、130。保护层160形成于介电层130以及部分金属层150的上方。包含探测区域170b与连接区域170a的焊盘层170，形成于保护层160的上方，并且与金属层150接触。具有露出部分焊盘层170的开口(未标示)的保护层180形成于保护层160上方。
一般而言，金属层150以及125又称为顶部金属层Mtop以及第二顶部金属层Mtop-1。金属层115包含有源或功能性电路图案。如图1A所示，金属层150与125仅作为缓冲层，提供想要的机械强度以对抗探测力与接合力。由于缓冲层150与125，在焊盘层170下的金属层115的布线电路以及介电层120于探测与接合的步骤较不易受到影响而受到损伤。然而，在焊盘层170下方使用金属层125作为缓冲层会减少与金属层125位于同一层的电路图案126的布线面积。因此，晶粒面积的缩小会受到限制。
为了解决上述的问题，有人提出另一种如图1B所示的焊盘结构。在此图中，有源区域160延伸至介于探测区域170b与金属层150之间的区域。位于探测层170b下的保护层160作为探测步骤的缓冲层，但是位于连接区域170a下的金属层125仍然作为保护层。因此，有源或者功能性电路126能够被布线在探测区域170b下方，并且与图1A的结构比较下，有更多的布线区域可以使用。然而，由于保护层160为氧化层，与金属层相较之下较不具弹性，所以探测步骤可能会使位于探测区域下的保护层160龟裂。发生于保护层160中的龟裂175，会使得在此区域中的产品的可靠度降低。
由上述可知，需要一种改良的焊盘结构以及焊盘结构的形成方法。
发明内容
第一保护层，形成于该第一含金属层上，该第一保护层具有第一开口，其露出部分第一含金属层；以及焊盘层，形成于该第一保护层上，且覆盖该第一开口，该焊盘层包括探测区域以及接合区域，该探测区域用来接触探针，而该接合区域用来接合导线，其中该探测区域经由该第一开口与该第一含金属层接触，该接合区域位于部分的该第一保护层的上方。
根据本发明的焊盘结构，还包括第二含金属层，形成于所述第一含金属层下方并邻接于所述第一含金属层，其中所述第二含金属层包括电路图案，设于接合区域的下方。
根据本发明的焊盘结构，其中所述电路图案还设于所述探测区域的下方。
根据本发明的焊盘结构，还包括导电图案，穿过于所述第一保护层的中，用以连接所述接合区域及所述第一含金属层。
根据本发明的焊盘结构，其中所述导电图案密封位于所述接合区域下方的所述第一保护层。
根据本发明的焊盘结构，其中所述导电图案包括导电接触孔阵列。
根据本发明的焊盘结构，还包括第二保护层，形成于所述第一保护层上方，所述第二保护层包括第二开口，其露出所述探测区域以及所述接合区域。
根据本发明具体实施例的焊盘结构的形成方法，包括：形成第一含金属层于基板上；形成第一保护层于该第一含金属层上，该第一保护层具有第一开口，其露出部分第一含金属层；以及形成焊盘层于该第一保护层上，且覆盖该第一开口，该焊盘层包括探测区域以及接合区域，该探测区域用来以探针接触，而该接合区域用来接合导线，其中该探测区域经由该第一开口与该第一含金属层接触，该接合区域位于部分的该第一保护层的上方。
根据本发明的焊盘结构的形成方法，还包括形成至少一个导电图案，在所述第一保护层之中穿过，用以连接所述接合区域及所述第一含金属层。
根据本发明的焊盘结构的形成方法，还包括形成至少一个导电图案，密封位于所述接合区域下方的所述第一保护层。
根据本发明的焊盘结构的形成方法，还包括形成导电接触孔阵列，在所述第一保护层之中穿过，用以连接所述接合区域及所述第一含金属层。
根据本发明的焊盘结构的形成方法，还包括形成第二含金属层于所述第一含金属层下方并邻接于所述第一含金属层，其中所述第二含金属层包括电路图案，设于接合区域的下方。
根据本发明的焊盘结构的形成方法，其中所述电路图案还设于所述探测区域的下方。
根据本发明的焊盘结构的形成方法，还包括形成第二保护层于所述第一保护层上方，所述第二保护层包括第二开口，其露出所述探测区域以及所述接合区域。
根据本发明的焊盘结构的形成方法，还包括：利用测试探针与所述探测区域接触；以及利用导线接合于所述接合区域。
附图说明
图1A及图1B为已知的CUP结构剖面图。
图2A至图2D为形成焊盘结构的具体方法的剖面示意图。
图2E为显示在探测区域应用探针的剖面示意图。
图2F为显示接合导线接合于图2E所示的焊盘结构的剖面示意图。
图2G为图2D的焊盘结构的上视图。
图2H至图2K为具体的焊盘结构的剖面图。
其中，附图标记说明如下：
现有技术
100～基板；
110、120、130～介电层；
113、123、135～接触孔；
115、125、150～金属层；
170～焊盘层；
170a～接合区域；
170b～探测区域；
160、180～保护层；
126～电路图案；
175～龟裂。
本发明
200～基板；
200a～薄化的基板；
210、220、230～介电层；
213、215、223、225、235及250～导电结构；
260～第一保护层；
280～第二保护层；
281～接合导线；
270～焊盘层；
270a～接合区域；
270b～探测区域；
265、275～开口；
277～探针；
a～宽度；
b～间距；
285、290、225a、225b～导电结构。
具体实施方式
图2A至图2D为形成焊盘结构的具体方法的剖面示意图。上述焊盘结构通常又称为焊盘下方电路(circuit under pad；CUP)结构。
请参照图2A，形成多层结构(未标示)于基板200上方，此多层结构例如可包括介电层210、220及230以及导电结构213、215、223、235及250。基板200可以是硅基板、III-V族化合物基板、例如液晶显示器(LCD)、等离子显示器、电激发光灯管显示器或发光二极管(LED)基板等显示基板(统称为基板200)。
介电层210、220及230例如可包括氧化层、氮化层、氮氧化合物层、低介电常数材料层、超低介电常数材料层或其组合或类似的材料。介电层210、220及230可使用例如化学气相沉积(CVD)步骤或类似的方法形成。导电结构213、223及235例如可包括接触孔(contacts)、介层孔(vias)、镶嵌结构、双镶嵌结构或其组合或类似的物质。在一个实施例中，导电结构213、223及235可包括铝层、铜层、铝铜层、钛层、氮化钛层、钽层、氮化钽层、其组合或类似的物质。导电结构215、225、250可包括含金属导线、含金属图案、镶嵌结构、双镶嵌结构或其组合或类似的物质。在一个实施例中，导电结构215、225、250可包括铝层、铜层、铝铜层、钛层、氮化钛层、钽层、氮化钽层、其组合或类似的物质。导电结构213、215、223、225、235及250可利用例如化学气相沉积步骤、物理气相沉积(physical vapor deposition；PVD)步骤、电化学镀膜步骤、无电镀膜(electroless plating)步骤、其组合或类似的方法形成。导电结构215及225可包括布线电路图案，通过此布线电路图案，形成于基板200之中或上方而电性连接的元件及/或二极管(图未显示)会彼此连接。导电结构250可包括含金属层，通过此含金属层，焊盘层会电性连接于导电结构225及/或215，也就是布线电路图案。在一个实施例中，导电结构250可包括至少一个开口(图未显示)，此开口形成于介电层(图未显示)之中。可利用介层孔/接触孔工艺步骤、金属线工艺步骤、镶嵌工艺步骤、双镶嵌工艺步骤、其组合或类似的方法形成导电结构213、215、223、225、235及250于介电层之中。在一个实施例中，导电结构250可包括厚度约9000的铜层。
导电结构250那层通常又称为顶部金属层(以符号Mtop表示)，在一个实施例中，可形成至少一个额外的金属结构(图未显示)于顶部金属层上以作为导电结构250。此额外的金属结构(图未显示)用来连接形成于其他介电层的其他导电结构。导电结构225形成于导电结构250的下方并邻接于导电结构250。导电结构225通常又称为第二顶部金属层(以符号Mtop-1表示)。如图2A所示，导电结构250覆盖一部的导电结构225的布线电路图案。虽然图2A仅显示三层的导电结构，然而本发明不限于此。导电结构的层数是随着工艺技术而改变，在一个实施例中，大于或小于三层的导电结构也可以得到想要的电路。
请参照图2B，形成第一保护层260于导电结构250的上方，第一保护层260之中形成有开口265，其露出部分的导电结构250的表面(未标示)。第一保护层260可包括例如氧化层、氮化层、氮氧化物层、聚酰亚胺层、其组合或类似的物质。在一个实施例中，第一保护层260包括厚度约4000的氧化层，其利用CVD步骤形成。开口265可利用光刻步骤及蚀刻步骤形成。例如形成图案化的光刻胶层(图未显示)于起始的第一保护层(用以形成第一保护层260)的上方。此图案化光刻胶层具有对应于开口265的开口，接着经由蚀刻步骤去除一部分的起始的第一保护层以露出一部分的导电结构250并形成第一保护层260。上述蚀刻步骤之后，进行光刻胶去除步骤以去除图案化光刻胶层。
请参照图2C，形成焊盘层270于第一保护层260上方，此焊盘层覆盖开口265(如图2B所示)，焊盘层270可包括铝层、铜层、铝铜层、铝硅铜层、其组合或类似的物质。焊盘层270可利用例如化学气相沉积步骤、物理气相沉积步骤、电化学镀膜步骤、无电镀膜步骤、其组合或类似的方法形成，在一个实施例中，焊盘层270包括铝铜层，而厚度可以是大约12000。
焊盘层270可以通过沉积步骤、光刻步骤及蚀刻步骤形成。例如，形成薄膜(用来形成焊盘层270)于图2B所示的结构上方，然后形成光刻胶层(图未显示)于上述薄膜上方，再图案化此光刻胶层，其覆盖对应于焊盘层270的图案的区域。接着，进行蚀刻步骤以去除未被图案化光刻胶层覆盖的焊盘层270，而形成焊盘层270。进行蚀刻步骤之后，利用光刻胶去除步骤以去除图案化光刻胶层。
请再参照图2C，焊盘层270包括接合区域270a以及探测区域270b，上述接合区域270a的上方用来形成接合导线结构或覆晶接合(flip chip bonding)结构，而上述探测区域270b的上方用来施以于探针测试。如图2C所示，第一保护层260延伸于接合区域270a的下方，换言之，第一保护层260延伸于接合区域270a以及导电结构250之间的区域。在此叠层区域，第一保护层260的延伸区域覆盖部分导电结构225的布线电路图案，也就是Mtop-1层。
如参照图2D，形成第二保护层280于第一保护层260的上方，第二保护层280之中具有开口275，露出部分的焊盘层270的顶部表面(未标示)，也就是露出接合区域270a以及探测区域270b。第二保护层280可包括例如氧化层、氮化层、氮氧化物层、聚酰亚胺层、其组合或类似的物质。在一个实施例中，第一保护层280包括厚度约4000的氧化层及6000的氮化层，上述氧化层及氮化层可利用CVD步骤形成。图2G显示第二保护层280及开口275的上视图。在一个实施例中，开口275的宽度“a”以及开口275之间的间距“b”，也就是第二保护层280的宽度大约等于或小于50μm，在一个实施例中，间距“b”大约等于或小于6μm。
开口275可利用光刻步骤及蚀刻步骤形成。例如形成图案化的光刻胶层(图未显示)于起始的第二保护层(用以形成第二保护层280)的上方。此图案化光刻胶层具有对应于开口275的开口，接着经由蚀刻步骤去除一部分的起始的第二保护层以露出一部分的焊盘层270，也就是接合区域270a及探测区域270并形成第二保护层280。上述蚀刻步骤之后，进行光刻胶去除步骤以去除图案化光刻胶层。
图2E为显示在探测区域270b应用探针277的剖面示意图。形成焊盘结构后，进行电性测试，以搜集代表形成于元件基板200上方或基板200之中的二极管及/或电路的电子性能的信号。在电子测试的期间，探针277被指向及施加于探测区域270b，探针277会接触或穿透焊盘层270，或者甚至穿透导电结构250。由于焊盘层270及导电结构250是具有弹性的含金属层，所以探针277的穿透不会使焊盘层270及/或导电结构250龟裂。再者，由于焊盘层270及导电结构250的总厚度可承受由探针277施加的探测力及压力，而不会使材料层龟裂(例如直接形成于导电结构225，也就是Mtop-1层的布线电路图案下方的介电层230)。
图2F为显示接合导线281接合于图2E所示的焊盘结构的剖面示意图。进行探针电子测试之后，可利用基板薄化步骤薄化基板200，以形成薄化的基板200a，基板薄化步骤例如为研磨(grinding)步骤。进行基板200薄化步骤之后，进行薄化的基板200a的分割步骤(dicing step)以得到单独的晶粒。然后，如图2F所示，将导线281或覆晶焊接凸块接合于接合区域270a上方。如图2F所示，保护层260形成于接合区域270a以及导电结构250之间，接合区域270a、保护层260及/或导电结构250的结合机械应力可承受接合步骤中产生的接合力，使得接合步骤不会使介电层230及/或直接形成于接合区域270a下方的导电结构225(即Mtop-1层)的布线电路图案损伤或龟裂。
如上所述，由于探测步骤及接合步骤都不会影损伤导电结构225，也就是Mtop-1层的布线电路图案，所以不需要在导电结构225形成的那层形成于额外的含金属层，以作为形成缓冲层。因此，整个导电结构225可用来作为金属布线及电子连接于其他的布线电路图案，使得晶粒的尺寸可以理想地降低。
图2H显示另一具体焊盘结构的剖面示意图，在此图之中，形成至少导电结构285，其穿过第一保护层260，用来连接接合区域270a以及导电结构250。导电结构285可包括例如包括铝层、铜层、铝铜层其组合或类似的物质。导电结构285例如可包括至少一个接触孔/介层孔结构、导线结构、镶嵌结构、双镶嵌结构、沟槽结构或其组合或类似的物质。在一个实施例中，导电结构285结合焊盘层270与导电结构250，用来密封直接形成于接合区域270a下方的保护结构260a。导电结构285提供接合区域270a以及导电结构250之间额外的电性连接。
导电结构285可以使用与图2C所描述的焊盘层270相同的方式来形成。在一个实施例中，利用与形成焊盘层270相同的工艺步骤来形成导电结构285。在一个实施例中，可使用额外的薄膜沉积步骤、光刻步骤及/或蚀刻步骤来形成导电结构285。
图2I显示另一具体焊盘结构的剖面示意图，此焊盘结构包括导电结构290阵列，其穿过位于接合区域270a下方的第一保护层260。导电结构290可利用上述与形成导电结构285相同或相似的方法来形成。导电结构290提供接合区域270a以及导电结构250之间想要的电性连接。
图2J为具体的焊盘结构的剖面示意图，此焊盘结构之中没有直接形成于探测区域270b下方的导电结构225a，也就是Mtop-1层的布线电路图案。可利用如图2A所描述的导电结构225相同或相似的形成方法来形成导电结构225a。如图所示，导电结构225a的图案布线围绕在直接位于接合区域270a下方的区域，用来提供与其他形成于相同或不同层的导电结构的电性连接。因此，在此实施例中，即使焊盘层270以及导电结构250无法承受探测步骤所施加的力，也没有直接位于探测区域270b下方的导电结构225a的布线电路会受到损伤。
另一实施例中，导电结构225b形成于探测区域270b的下方，如图2K所示。在此实施例中，导电结构225b用来作为缓冲层，也就是非功能性电路，但是提供导电结构215以及250之间的电性连接，以更进一步地保护直接位于导电结构225b下方的导电结构215，也就是Mtop-2。导电结构225b可利用与形成导电结构225a相同的方法来形成。在一个实施例中，可利用如图2A所描述的导电结构225相同或相似的形成方法来形成导电结构225b。在一个实施例中，可使用额外的薄膜沉积步骤、光刻步骤及/或蚀刻步骤来形成导电结构225b。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许修改与变型，因此本发明的保护范围当视后附的权利要求所界定者为准。

Claims (15)

1.一种焊盘结构，包括：
第一含金属层，形成于基板上；
第一保护层，形成于所述第一含金属层上，所述第一保护层具有第一开口，其露出部分第一含金属层；以及
焊盘层，形成于所述第一保护层上，且覆盖所述第一开口，所述焊盘层包括探测区域以及接合区域，所述探测区域用来接触探针，而所述接合区域用来接合导线，其中所述探测区域经由所述第一开口与所述第一含金属层接触，所述接合区域位于部分的所述第一保护层的上方。
2.如权利要求1所述的焊盘结构，还包括第二含金属层，形成于所述第一含金属层下方并邻接于所述第一含金属层，其中所述第二含金属层包括电路图案，设于接合区域的下方。
3.如权利要求2所述的焊盘结构，其中所述电路图案还设于所述探测区域的下方。
4.如权利要求1所述的焊盘结构，还包括导电图案，穿过于所述第一保护层之中，用以连接所述接合区域及所述第一含金属层。
5.如权利要求4所述的焊盘结构，其中所述导电图案密封位于所述接合区域下方的所述第一保护层。
6.如权利要求4所述的焊盘结构，其中所述导电图案包括导电接触孔阵列。
7.如权利要求1所述的焊盘结构，还包括第二保护层，形成于所述第一保护层上方，所述第二保护层包括第二开口，其露出所述探测区域以及所述接合区域。
8.一种焊盘结构的形成方法，包括：
形成第一含金属层于基板上；
形成第一保护层于所述第一含金属层上，所述第一保护层具有第一开口，其露出部分第一含金属层；以及
形成焊盘层于所述第一保护层上，且覆盖所述第一开口，所述焊盘层包括探测区域以及接合区域，所述探测区域用来以探针接触，而所述接合区域用来接合导线，其中所述探测区域经由所述第一开口与所述第一含金属层接触，所述接合区域位于部分的所述第一保护层的上方。
9.如权利要求8所述的焊盘结构的形成方法，还包括形成至少一个导电图案，在所述第一保护层之中穿过，用以连接所述接合区域及所述第一含金属层。
10.如权利要求8所述的焊盘结构的形成方法，还包括形成至少一个导电图案，密封位于所述接合区域下方的所述第一保护层。
11.如权利要求8所述的焊盘结构的形成方法，还包括形成导电接触孔阵列，在所述第一保护层之中穿过，用以连接所述接合区域及所述第一含金属层。
12.如权利要求8所述的焊盘结构的形成方法，还包括形成第二含金属层于所述第一含金属层下方并邻接于所述第一含金属层，其中所述第二含金属层包括电路图案，设于接合区域的下方。
13.如权利要求12所述的焊盘结构的形成方法，其中所述电路图案还设于所述探测区域的下方。
14.如权利要求8所述的焊盘结构的形成方法，还包括形成第二保护层于所述第一保护层上方，所述第二保护层包括第二开口，其露出所述探测区域以及所述接合区域。
15.如权利要求8所述的焊盘结构的形成方法，还包括：
利用测试探针与所述探测区域接触；以及
利用导线接合于所述接合区域。
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