TWI335644B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TWI335644B
TWI335644B TW095133583A TW95133583A TWI335644B TW I335644 B TWI335644 B TW I335644B TW 095133583 A TW095133583 A TW 095133583A TW 95133583 A TW95133583 A TW 95133583A TW I335644 B TWI335644 B TW I335644B
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Taiwan
Prior art keywords
semiconductor substrate
electrode
pad electrode
semiconductor device
electronic circuit
Prior art date
Application number
TW095133583A
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English (en)
Other versions
TW200713529A (en
Inventor
Yuichi Morita
Shinzo Ishibe
Takashi Noma
Hisao Otsuka
Yukihiro Takao
Hiroshi Kanamori
Original Assignee
Sanyo Electric Co
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Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200713529A publication Critical patent/TW200713529A/zh
Application granted granted Critical
Publication of TWI335644B publication Critical patent/TWI335644B/zh

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

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1335644 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體裝置及其製造方法，尤其有 關一種具有貫穿半導體基板的通孔（Via hole)之半導體裝 置及其製造方法。 【先前技術】 近年來，CSP(Chip Size Package ;晶片尺寸封裝）作 為新型的封裝技術而受到矚目。所謂csp係意指具有與半 籲導體晶片的外形尺寸大致相同大小的外形尺寸之小型封裳 體。csp的-種，已知有BGA(Bal】Grid Array;球拇陣列） 型的半導體裝置。 這種半導體裝置係具有通過貫穿半導體基板的通孔， 而與半導體基板表面的塾電極連接之配線層。該半導體其 面係以格子狀方式配列有複數個由銲錫等金屬㈣ 二=:狀的導電端子’這些導電裙子係經由配線層而 ?:述塾電極連接。而且，將該半導體裝置組裝至電子機 态時，係將各導電端子連接至電 板上的配線圖案， I 土板，例如印刷電路基 BGA型的半導體裝置與具有突出 SOPCSmall Outline Packp^ · , t 丨町導線接腳之 F] f p , . g ，小外型封裝）或QFP(Quad FI at Package，四面平整封梦）望盆 相比，JL有β 、等，、他的CSP型半導體裝置 化之優點。 川子，且能將尺寸予以小型 第8圖及第 9圖係顯示BGA型的半導體 裝置的構造及 318581 5 製造方法，尤其係 -私坐道： 墊電極的周邊之圖。如第8ra所 不’於+導體基板50的表 如第8圖所 電㈣，並形成在該塾電二=絕緣膜51而形成塾 絕緣膜51及塾電極52的邊緣部之第/且覆盖第1 52係與形成於半導體基 保=53。塾電極 接，經由該墊電極52於一…未圖不的電子電路連 纪电径62於刖述電子電路 信號的授受。 罨路之間進仃 經過半導體的晶圓處理(wafer_ 板:0上製成電子電路後，進行該電子電路是否正 測:式。此時，測試探針54係通過設於第^保護膜 ㈠而與墊電極52的表面接觸。第8㈣雖僅顯示了一個 塾電極52,惟實際上係於半導體基板5{)上形成相同的多 數個墊電極52。測試探針54係連接於LSi(Large s⑽
Integrati〇n circuit，·大型積體電路）測試器（tester) 1 〇 〇。然後，藉由從L SI測試器！ 〇 〇將測試信號通過測試探 針54與墊電極52傳送至電子電路，再由Lsi測試器1〇〇 經由相反的路徑接收來自電子電路的回答信號，而能進行 電子電路的測試。 完成上述測試的半導體基板50係傳送至後段製程，以 $成通孔、配線以及球狀的導電端子等。亦即，如第9圖 所不’於半導體基板5〇的表面隔著接著用的樹脂膜55而 貼附用來支持半導體基板5〇之玻璃基板56。之後，形成： 通孔57’其貫穿半導體基板50;第2絕緣膜58，其覆蓋 通孔57的側壁及半導體基板50的背面；以及配線層59， 318581 6 1335644 其於第2絕緣膜58上通過通孔57而連接至墊電極52的背 面’且延伸於半導體基板5〇的背面 '然後，形成：第2 保瘦膜60，其覆蓋半導體基板5〇的背面，且於配線層μ 上具有開口部；以及球狀的導電端子6卜其通過前述開口 部而連接至配線層59。 專利文獻1 :日本特開第2003_309221號公報 【發明内容】 (發明所欲解決之課題） 然而，上述BGA型半導體裝置具有：在進行電子電路 的測試時，由於將測試探針54的前端部壓抵於墊電極52, 而損傷塾電極52’使得水分容㈣該損傷而浸人而腐钱塾 電極5 2之問題。 並且，由於在墊電極52上設置第丨保護膜53的開口 部κ’故產生：通孔57形成後，墊電極52上下方向的固 定變得不安定，受到通孔57形成後的熱處理之影響墊電 極52的中央部會產生翹曲’嚴重時更會產生龜裂等問題。 列舉熱處理之影響的具體例，則有：在藉由如同光阻 (Photoresist)之有機膜形成第2絕緣膜58時爲使其硬 化而施予供烤（baking)處理之例子。此時，第2絕緣膜Μ 會收縮，產生將墊電極52往下拉的應力。由於該拉應力， 導致墊電極52的中央部產生翹曲。 (解決課題的手段） 本發明的半導體裝置係具備有：半導體基板；電子 路’其形成於前述半導體基板上；第i塾電極，其與前述 318581 7 丄 W5644 電子=路連接；帛2墊電極，其與形成於前述半導體基板 上的前述第1墊電極連接；保護膜，其覆蓋前述第1墊電 極，並且僅於前述第2墊電極上具有開口部；以及配線層， 過貝穿則述半導體基板的通孔而連接至前述第1整電 極的背面，且從前述通孔延伸至前述半導體基板的背面。 •;此外，本發明的半導體裝置的製造方法，係具備有： 準備表面形成有電子電路、與該電 極：以及與該第，整電極連接的第2塾電極，== 盍前述第1墊電極，並且僅於前述第2塾電極的表面具有 開口部的保護膜之半導體基板，而在與前述第1塾電極對 應的位置幵y成貝穿則述半導體基板的通孔之步驟；以及形 成通過前述通孔而連接至前述第1墊電極的背面，且從前 述通孔延伸至前述半導體基板的背面之配線層之步驟。 (發明的效果） 依據本發明，由於設置有與第丨墊電極連接的第2墊 .電極，故藉由將第2墊電極用作為電子電路測試用的接 墊，即能防止連接用的第丨墊電極因受損傷而腐蝕。此外， 甴於將第2墊電極用作為電子電路測試用的接墊，故無須 於第1墊電極處設置第1保護膜的開口部，第卫塾電極係 甴第1保護膜覆蓋並安定地固定著。如此，即不會為形成 通孔後的熱處理所影響，而能解決第丨墊電極翹曲之問題。 【實施方式】 接著，參照圖式說明本發明的實施形態。第1圖係完 成晶圓處理的階段之半導體裝置全體的平面圖，第2圖係 318581 8 ^中虛線所包圍的部分之放大圖， 圖的X-X線的剖面圖。 ^第1圖及第2圖所示，於㈣所構成的半導體基板 W 成有·電子電路3G(半導體積體電路）、第1墊電 二以及配置成與第1墊電極3鄰接，並經由配線 墊電極3連接的第2墊電極4。第1塾電極^外 =連接用的接塾（_)，經由配線21而與電子電路別連 即’經由第1塾電極3而於電子電路⑽與外部電路 =行信號的授受。第2墊電極4係電子電路抑測試用 電子電路 30 為例如 CCD(ChargeC〇upledDevice; ^合凡件）和紅外線感測器等的受光元件、或者為發光 疋件，亦可為其他的電子電路。 此外，如第3圖的剖面圖所示，帛i墊電極3及第2 、極4係形成於藉由熱氧化等而形成於半導體基板】表 面之第1絕緣膜2上。此外，第i塾電極3 4係例如藉由進⑽⑹的濺鑛而形成，且較佳為具塾有^ β m的臈厚。第1絕緣膜2係例如由氧化石夕膜 oxide film)所構成，且較佳為具有約〇.8#瓜的膜厚。 严此外，藉由 CVD 法（Chemical Vapour Dep〇sition ;化 f氣相沉積法）形成覆蓋第1絕緣膜2及第1墊電極3’、覆 蓋第2塾電極4的端部，並具有使第2墊電極$的表面露 f的開口部反之第1保護膜5。第1保護膜5係為例如由 氣化珍膜所構成的純化（passivation)膜。 然後，使測試探針54通過第丨保護膜5的開口部1( 318581 9 1335644 :接觸第2塾電極4的表面，以測試電子電路⑽是否正常 動作。測試探針54係連接於LSI測試器1〇〇。然後，藉由 從LSI測試器100將測試信號通過測試探針54、第2墊電 :=第丨墊電極3而傳送至電子電路3〇，再由W測 “ 100、！由相反的路徑接收來自電子電路3〇的回應俨 ^而能進行電子電路3G的賴。此時，由於測試料 54的前端部壓抵在第2塾電極4,故第2塾電極4受到損 旦f 1塾電極3則未受損傷。因此，即使第2墊電極 因才貝傷而腐韻’第1塾電極3也不會腐钱，故能確實達 成作為外部連接用端子的功能。 完成該測試後，可如第4圖所示，根據需要而於半導 體基板1的表面形成支持體7。該支持體7係隔著樹脂層6 而形成於半導體基板丨的表❼在此，電子電路3()為受光 疋件或發光元件時，支持體7係藉由例如具有如同玻璃之 透明或半透明性質的材料所形成。電子電路3〇非為受光元 件或發光元件時，支持體7可藉由不具有透明或半透明性 質的材料所形成。此外’支持體7亦可為帶狀者。該支持 體：可於後段製程中去除。或者，支撐體7可不去除而存 留者。 接著，如第5圖所示，以從背面選擇性地蝕刻（較佳為 乾蝕刻)半導體基板1的方式，進行半導體基板1的蝕刻。 半導體基板1由矽所構成時，可使用CHF3(三氟曱烷）來作 為⑽刻的蝴氣體。藉由該㈣，在半導體基板i之與 第1墊電極3對應的位置形成從背面|穿至表面的通孔。 318581 8〇形成第2絕緣膜卩在涵^丨s从士 2的上方接有第！墊雷二底部露出，且们絕緣膜 墊電極3的狀態。秋德，里兹士 或濕姓刻來钱刻在通孔8:1再猎由乾钱刻 薄膜化，或將之完全去除::出的第1絕緣膜2,使之 驟，亦可不在此階段進〜5 ^帛1絕緣臈2的姓刻步 進行。 又仃，而與後述的其他蝕刻步驟同時 形成包含通孔8内壁的半導體基板1的背面全面 的有機膜、=9°在此第2絕緣膜9係例如光阻之類 ”成第2絕緣膜9後’進行使其硬化 %^ 此時’雖然第2絕緣膜9會收縮，而對第i 塾電極3施加拉應力，作由 在第1墊電極3表面密接有 /、濩膜5 ’故拉應力有第i保護膜5加以對抗，而防 j 1塾電極3之翹曲。之後’藉由曝光/顯像使第2絕 细、9圖案化’去除通孔8底部的第2絕緣膜9，使第1 電極3的背面露出。於半導體基板1的背面及通孔8的 侧壁殘存著第2絕緣膜9。 此外，第2絕緣膜9亦可由氧化矽膜（Si〇2膜）或氮化 石夕膜（SiN膜）所構成’且藉由例如電漿〇^法而形成。此 時，於第2絕緣膜9上形成未圖示的阻劑（resist)層，以 此阻^層作為遮罩，將通孔8底部的第2絕緣膜％若第1 絕緣膜2仍殘存的情形亦包含在内）予以㈣去除。此钱刻 較佳為例如反應性離子蝕刻（reactive i〇n etching)，亦 可為其他㈣刻。藉由上述姓刻’能使形成於通孔8側壁 的第2絕緣膜9殘存，而去除通孔8底部的第2絕緣膜9， 318581 11 1335644 使第1墊電極3的背面露出。 接著，如第6圖所示，形成配線層1〇，此配線層1〇 it git孔8 π連接_£第i墊電極3的背面’且從通孔8延 伸至半導體基板1的t面。配線们〇係能藉 ㈣法以及其後的選擇性㈣】來形成。此外，配 亦能藉由電解鍍覆法來形成。此時，於包含通孔8在内的 半導體基板1的背面的第2絕緣膜9上形成種子層（seed layer)，然後藉由電解鍍覆法於該種子層上形成由銅（cu) 所構成的配線層10。鍍覆膜厚可調整為配線層1〇完全或 不完全填人通孔8内之厚度。上述種子層係例如，層積例 如鈦鎢（Tiw)層、氮化鈦（TiN)層或氮化鈕（TaN)層等的金屬 層，以及銅（Cu)等的金屬層而形成。種子層係例如藉由錢 鍍法、CVD法、無電解錢覆法或其他的成膜方法而形成。 並且，通孔8側壁的第2絕緣膜9由氮化矽膜（SiN膜）所 形成時，由於該氮化矽膜（SiN膜）會成為銅擴散時的阻障 (barrler)，故種子層可具有由銅（Cu)所構成的單層構造。 接著，如第7圖所示，於半導體基板丨的背面上形成 由例如阻焊劑（s〇lder resist)之類的阻劑材料等所構成 2第2保護膜11。於第2保護膜u中的配線層1〇的一部 分上設置開口部。然&，在從該開口部露出的配線層 上’使用網版印刷法形成由例如銲錫等金屬所構成的球狀 導電端子12,而構成BGA型半導體裝置。 並且，本發明的半導體裝置係LGA(LandGridArray; 平面栅格陣列）型時’無須於從第2保護膜u局部露出的
31S58I 12 1335644 配線層10的一部分上形成導電端子12。 【圖式簡單說明】 第1圖係有關本發明實施形態的半導體裝置的全體之 平面圖。 第2圖係第1圖中以虛線圍住部分的放大圖。 第3圖係沿著第2圖的χ_χ線的剖面圖。 第4圖係顯示有關本發明實施形態的半導體裝置的製 造方法之剖面圖。 第5圖係顯示有關本發明實施形態的半導體裝置的製 造方法之剖面圖。 、第6圖係顯不有關本發明實施形態的半導體裝置的製 造方法之剖面圖。 ^第7圖係顯不有關本發明實施形態的半導體裝置的製 乂方法之剖面圖。 第8圖係顯不有關習知例的半導體裝置的製造方法之 習知例的半導體裝置的製造方法之 第9圖係顯示有關 剖面圖。 主要元件符號說明】 '50 半導體基板 第1墊電極 '53 第1保護膜 支持體 '58 第2絕緣膜 2、51 第1絕緣膜 4 第2墊電極 6 樹脂層 8、57 通孔 10、59配線層 318581 1335644 11 ' 60 第2保護膜 12 ' 61 導電端子 20 ' 21 配線 30 電子電路 52 墊電極 54 測試探針 55 樹脂膜 56 玻璃基板 100 LSI測試器 K 開口部

Claims (1)

1335644 (9 TTil專趟讀案 ，“ ri r
十、申請專利範圍： 1. 一種半導體裝置，係具備有： 半導體基板； 電子電路，其形成於前述半導體基板上； 第1墊電極，其形成於前述半導體基板上，且盥箭 述電子電路連接； ’ 第2墊電極，其形成於前述半導體基板上，且與前 述第1墊電極連接，用以使測試探針接觸以進行前述Z 子電路的測試； 保護膜，其覆蓋前述第丨.墊電極，並且僅於前述第 2塾電極上具有開口部； 及支持體，隔著接著層貼附於前述半導體基板上；以 ▲配線層.，其連接至前述第！墊電極的背面， 至刖述半導體基板的背面。 2· 請專利範圍第1項之半導體裝置，其中，於前述配 線層上形成有導電端子。" 3. 一種半導體裝置之製造方法，其特徵在於： 準備表面形成有電子電路、與該電子電路連接的第 導體基:、广及與該第1塾電極連接的第2塾電:極之半 且該製造方法具備··. 的茅盍“第1墊電極並且僅於前述第2墊電極 的表面具有開口部的保護m之步驟、夺 (修正本)318581 15 第95133583號專利申請案 <98年；1〇月22日7 使測試探針通過煎述 9 極以谁并乂、上 。丨而接觸刖述第2墊電 订别述電子電路的測試之步驟；以及 形成連接至前述第丨墊電極的背面，且延伸至前述 導體基板的背面之配線層之步驟。 4.如申請專利範圍第3項之半導體裝置之製造方法，其. 中’具備有於前述半導體基板上貼附支持.體之步驟。 5·如申請專利範圍第3項或第4項之半導體裝置之製造方 法，其中’具備有於前述配線層上形成導電端子之步驟。 16 (修正本)318581
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