CN1700457A - 用于测试凸点的倒装芯片半导体封装及其制造方法 - Google Patents

用于测试凸点的倒装芯片半导体封装及其制造方法 Download PDF

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CN1700457A
CN1700457A CNA2005100667232A CN200510066723A CN1700457A CN 1700457 A CN1700457 A CN 1700457A CN A2005100667232 A CNA2005100667232 A CN A2005100667232A CN 200510066723 A CN200510066723 A CN 200510066723A CN 1700457 A CN1700457 A CN 1700457A
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testing
pads
semiconductor packages
salient points
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郑镇国
裵庸太
金映旲
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Samsung Electronics Co Ltd
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Abstract

本发明涉及一种半导体封装，其包括：沿着半导体芯片的表面边缘设置的多个焊盘；形成在所述半导体芯片的表面上并设置为离开所述多个焊盘一预定距离的多个安装凸点；将所述多个焊盘电连接至所述多个安装凸点的多条再分布连接布线；以及设置在所述多个焊盘上的多个测试凸点。

Description

用于测试凸点的倒装芯片半导体封装及其制造方法
技术领域
本公开涉及一种半导体封装及其制造方法，更特别地，涉及用于测试凸点的倒装芯片(flip chip)半导体封装及其制造方法。
背景技术
随着半导体器件的集成度提高，半导体器件输入/输出端子的数量增加。表面安装型封装比针插入型封装更常使用，这是因为针插入型封装中电路板上能够形成的外部引线(outer lead)数量受到限制。提出了诸如球栅阵列(BGA)封装和芯片规模封装的封装方法，以将半导体芯片设置在更小空间中。半导体芯片安装在封装上。半导体芯片和封装使用电连接的方法连接，例如，引线键合，载带自动键合，及倒装芯片键合。
使用倒装芯片键合的半导体封装的尺寸能够小于使用引线键合的半导体封装的尺寸。倒装芯片封装具有高速电特性并且输入/输出端子能够形成在半导体芯片的任何位置。通过凸点(bump)的再分布(redistribution)能够减小倒装芯片封装的尺寸。
图1至3示出了传统倒装芯片半导体封装及其制造方法。参考图1，在绝缘层101的边缘形成多个上焊盘(upper pad)112。上焊盘112通过接触通孔(via contact hole)(未示出)电连接到多个下焊盘(未示出)。参考图2，形成多条再分布连接布线120并连接至所述多个上焊盘112。该再分布连接布线120可由导电层形成。该再分布连接布线从上焊盘112朝封装的中央延伸。参考图3，在封装上形成钝化层103。该钝化层103具有用于露出再分布连接布线120的开口。通过传统工艺，可以在再分布连接布线120的露出部分上形成凸点142。
执行电芯片筛选(EDS，electrical die sorting)测试以测试倒装芯片封装的电特性。EDS测试包括使用垂直探针板的方法和使用传统探针板的方法。
参考图4，示出了使用垂直探针板(probe card)300的EDS测试。垂直探针板300包括体310和设置在体310底表面上的多个探针320。探针320对应凸点142排列。接着，垂直探针板300下降，使得探针320接触倒装芯片半导体封装的对应凸点142。然后，加上信号以进行EDS测试。
使用传统探针板的EDS测试需要在图1所示的上焊盘112上进行，这是因为传统探针板的探针不能够对应凸点142排列。
当使用垂直探针板300用于EDS测试时，倒装芯片半导体封装的制造成本会增加，因为垂直探针板300昂贵。当使用传统探针板用于EDS测试时，倒装芯片封装会受到污染，因为需要在封装制造工艺期间将倒装芯片封装转移到测试线上。
发明内容
在本发明的一个示范实施例中，一种半导体封装包括：沿着半导体芯片的表面边缘设置的多个焊盘；形成在半导体芯片的表面上并离开多个焊盘一预定距离设置的多个安装凸点；将多个焊盘电连接至多个安装凸点的多条再分布连接布线；以及设置在多个焊盘上的多个测试凸点。
在本发明的另一个示范实施例中，一种半导体封装包括：半导体芯片；沿着半导体芯片的表面边缘设置的多个焊盘；形成在半导体芯片的表面上并离开多个焊盘一预定距离设置的多个安装凸点；将多个焊盘电连接至多个安装凸点的多条再分布连接布线；以及设置在多个焊盘和多个安装凸点之间的多个测试凸点。
在本发明的又一个示范实施例中，一种用于制造半导体封装的方法包括：在半导体芯片上形成第一绝缘层，该第一绝缘层具有用于露出半导体芯片的多个焊盘的一部分的开口；在第一绝缘层上形成多条再分布连接布线，其中所述多条再分布连接布线电连接至多个焊盘；形成具有用于露出多条再分布连接布线的第一区和第二区的开口的第二绝缘层；以及分别在多条再分布连接布线的第一区和第二区上形成多个安装凸点和多个测试凸点。
通过参考附图详细地描述其示范实施例，上述和其它示范实施例将变得更加明晰。
附图说明
图1至3是示出传统倒装芯片半导体封装的制造工艺的平面图；
图4是示出关于传统倒装芯片半导体封装的EDS测试的示范实施例的截面图；
图5至8是示出根据本发明示范实施例的倒装芯片半导体封装制造方法的平面图；
图9和10是示出根据本发明另一示范实施例的倒装芯片半导体封装制造方法的平面图；
图11至14是分别沿图5至8的A-A’线截取的截面图；以及
图15和16是沿图9和10的A-A’线截取的截面图。
具体实施方式
现在将参考附图更加充分地描述本发明的示范实施例。然而，本发明能够以许多不同的形式实施，并且不应当理解成局限于这里列举的示范实施例的限制。更确切地，提供这些示范实施例是使得本公开彻底和完整，并向本领域技术人员充分传达本发明的理念。在附图中，为了清楚起见放大了层的厚度和区域。
图8和14示出了根据本发明示范实施例的倒装芯片半导体封装。该倒装芯片半导体封装包括半导体芯片200、绝缘层201、下焊盘211、接触层202、上焊盘212、测试凸点241、再分布连接布线220和安装凸点242。绝缘层201形成在半导体芯片200的表面上，在该表面上已经形成了下焊盘211。形成在半导体芯片200的表面上的绝缘层201覆盖下焊盘211。上焊盘212形成在绝缘层201上。上焊盘212通过穿过绝缘层201的接触通孔202与下焊盘211电连接。再分布连接布线220设置在绝缘层201的一部分上。再分布连接布线可由导电层形成并从上焊盘212朝倒装芯片半导体封装的中央延伸。
钝化层203覆盖上焊盘212、再分布连接布线220和绝缘层201。该钝化层203具有用于露出上焊盘212的一部分的第一开口231和露出再分布连接布线220的一部分的第二开口232。通常，对应再分布连接布线220的第一端形成所述第二开口232，该第一端与上焊盘212相对。安装凸点242设置在再分布连接布线220的通过第二开口232露出的部分上。测试凸点241设计为在EDS测试期间接触传统探针板的探针。安装凸点242设计为在将倒装芯片半导体封装安装在印刷电路板或基板上时是倒装芯片键合的(flip-chip-bonded)。测试凸点241和安装凸点242可通过相同制造工艺由相同材料形成。
根据本发明的示范实施例，可以在没有于制造线的外部进行的单独测试的情况下制造倒装芯片半导体封装。因为倒装芯片半导体封装不需要在制造该倒装芯片封装时转移到测试线，因此可以防止倒装芯片半导体封装的污染。
根据本发明的示范实施例，可以使用传统探针板进行用于最终倒装芯片封装的EDS测试。传统探针板的探针接触倒装芯片半导体封装的测试凸点241。由于测试凸点241设置在上焊盘212之上，传统探针板的探针能够接触设置在上焊盘212上的测试凸点241。在探针接触测试凸点241后，施加基于EDS测试程序的信号以探测缺陷。
参考图5至8以及11至14描述根据本发明示范实施例的倒装芯片半导体封装制造工艺。参考图5和11，在半导体芯片200和下焊盘211上形成绝缘层201。下焊盘设置在半导体芯片200的边缘处。接触通孔202穿过绝缘层201形成。上焊盘212和下焊盘211通过接触通孔202彼此接触。
参考图6和12，在绝缘层201上形成再分布连接布线220。该再分布连接布线可以通过常规金属化工艺(metallization process)由导电层形成。该再分布连接布线220从上焊盘212朝倒装芯片半导体封装的中央延伸。在本发明的示范实施例中，再分布连接布线220的长度可以基于第二开口232的位置而彼此不相同。
参考图7和13，钝化层203覆盖上焊盘212、再分布连接布线220和绝缘层201。通过移除钝化层203的一部分，形成用于露出每个上焊盘212的一部分和每个再分布连接布线220的一部分的第一开口231和第二开口232。该第一开口231形成在上焊盘212上，且该第二开口232形成在再分布连接布线220上。
参考图8和14，使用诸如例如电镀工艺(electrolytic plating)、丝网印刷工艺、球布置(ball placement)工艺的传统凸点形成方法，形成测试凸点241和安装凸点242。测试凸点241设置在上焊盘212的通过第一开口231露出的部分上。安装凸点242设置在再分布连接布线220的通过第二开口232露出的部分上。测试凸点241和安装凸点242可以由金或者焊料形成。
参考图10和16，根据本发明的另一示范实施例，测试凸点341设置在再分布连接布线220的露出部分上。
钝化层203覆盖上焊盘212、再分布连接布线220和绝缘层201。钝化层203包括用于露出每个再分布连接布线220的部分的第一开口331和第二开口332。第一开口331靠近上焊盘212形成在钝化层上。第二开口332靠近倒装芯片半导体封装的中央形成在钝化层203上。
测试凸点341设置在再分布连接布线220的通过第一开口331露出的部分上。安装凸点342设置在再分布连接布线220的通过第二开口332露出的部分上。安装凸点342和上焊盘212之间的距离可以变化。然而，测试凸点341和上焊盘212之间的距离(图10中示出为“d”)基本上相同。因此，使用传统探针板的EDS测试可在测试凸点341上进行。当测试凸点341中的凸点的尺寸大于上焊盘212中的焊盘的尺寸时，可以使用根据本发明示范实施例的倒装芯片半导体封装。
参考图9、10、15和16，在半导体芯片200上形成绝缘层201，并在绝缘层201上形成上焊盘212。在绝缘层201上形成再分布连接布线220。
参考图9和15，钝化层203覆盖上焊盘212、再分布连接布线220和绝缘层201。通过移除钝化层203的一部分，形成用于露出再分布连接布线220的第一开口331和第二开口332。该第一开口331容纳测试凸点341。该第二开口332容纳安装凸点342。该第一开口331设置在距上焊盘212的预定距离(d)处。第一开口331比第二开口332更加靠近上焊盘212。
参考图10和16，使用诸如例如电镀工艺、丝网印刷工艺、球布置工艺的传统凸点形成方法，形成测试凸点341和安装凸点342。测试凸点341设置在再分布连接布线220的通过第一开口331露出的部分上。安装凸点342设置在再分布连接布线220的通过第二开口332露出的部分上。测试凸点341和安装凸点342可以由金或焊料形成。
尽管在此参考附图描述了示范实施例，但是可以理解的是，本发明不限于这些示范实施例，且本领域普通技术人员可以在其中实施各种其它变化和修改，而不脱离本发明的范围或者精神。所有这些变化和修改确定为包括在由所附权利要求限定的发明保护范围内。
本申请要求于2004年5月4日向韩国知识产权局提交的第10-2004-0031357号韩国专利申请的优选权，其公开的全文在此作参照引用。

Claims (16)

1.一种半导体封装，包括：
沿着半导体芯片的表面边缘设置的多个焊盘；
形成在所述半导体芯片的表面上并设置为离开所述多个焊盘一预定距离的多个安装凸点；
用于将所述多个焊盘电连接至所述多个安装凸点的多条再分布连接布线；以及
设置在所述多个焊盘上的多个测试凸点。
2.如权利要求1的半导体封装，其中所述再分布连接布线由导电层形成，每个所述再分布连接布线具有接触对应焊盘的第一端和接触对应安装凸点的第二端。
3.如权利要求1的半导体封装，其中所述多个测试凸点的每一个接触对应的再分布连接布线的上表面的一部分，该再分布连接布线接触对应的焊盘。
4.如权利要求1的半导体封装，其中所述多个安装凸点和所述多个测试凸点通过相同工艺由相同材料形成。
5.如权利要求4的半导体封装，其中所述多个安装凸点和所述多个测试凸点由金或者焊料形成。
6.一种半导体封装，包括：
半导体芯片；
沿着所述半导体芯片的表面边缘设置的多个焊盘；
形成在所述半导体芯片的表面上并设置为离开所述多个焊盘一预定距离的多个安装凸点；
将所述多个焊盘电连接至所述多个安装凸点的多条再分布连接布线；以及
设置在所述多个焊盘和所述多个安装凸点之间的多个测试凸点。
7.如权利要求6的半导体封装，其中所述多条再分布连接布线由导电层形成，且所述多条再分布连接布线的每一个具有接触对应的焊盘的第一端和接触对应的安装凸点的第二端。
8.如权利要求6的半导体封装，其中所述多个安装凸点和所述多个测试凸点通过相同工艺由相同材料形成。
9.如权利要求8的半导体封装，其中所述多个安装凸点和所述多个测试凸点由金或者焊料形成。
10.如权利要求6的半导体封装，其中所述多个测试凸点中的凸点的尺寸大于所述多个焊盘中的焊盘的尺寸。
11.如权利要求6的半导体封装，其中所述多个测试凸点和所述多个焊盘之间的距离基本上相等。
12.一种用于制造半导体封装的方法，包括：
在半导体芯片上形成第一绝缘层，该第一绝缘层具有用于露出所述半导体芯片的多个焊盘的一部分的开口；
在所述第一绝缘层上形成多条再分布连接布线，其中所述多条再分布连接布线电连接至所述多个焊盘；
形成第二绝缘层，其具有用于露出所述多条再分布连接布线的第一区和第二区的开口的；以及
分别在所述多条再分布连接布线的所述第一区和所述第二区上形成多个安装凸点和多个测试凸点。
13.如权利要求12的方法，其中所述第一区形成为与所述多个焊盘相对且所述第二区形成在所述多个焊盘上。
14.如权利要求12的方法，其中所述第一区形成为与所述多个焊盘相对且所述第二区形成在所述多个焊盘和所述第一区之间。
15.如权利要求12的方法，其中所述多个安装凸点和所述多个测试凸点在一个工艺中同时形成。
16.如权利要求15的方法，其中所述多个安装凸点和所述多个测试凸点由金或者焊料形成。
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