CN111916363A - 制造倒装芯片封装的方法和测试倒装芯片的设备 - Google Patents

制造倒装芯片封装的方法和测试倒装芯片的设备 Download PDF

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Publication number
CN111916363A
CN111916363A CN201911106041.8A CN201911106041A CN111916363A CN 111916363 A CN111916363 A CN 111916363A CN 201911106041 A CN201911106041 A CN 201911106041A CN 111916363 A CN111916363 A CN 111916363A
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testing
package substrate
semiconductor chips
test
semiconductor
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郑知远
金东真
金秉虎
金昌炫
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SK Hynix Inc
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SK Hynix Inc
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Abstract

制造倒装芯片封装的方法和测试倒装芯片的设备。一种制造倒装芯片封装的方法，该方法包括形成多个半导体芯片以及将半导体芯片结合到封装基板的步骤。该方法还包括对在封装基板上的多个半导体芯片进行电测试，对经测试的半导体芯片进行模制以及将经模制的芯片单片化的步骤。对半导体芯片进行电测试的步骤包括利用保护构件覆盖半导体芯片的步骤。

Description

制造倒装芯片封装的方法和测试倒装芯片的设备
技术领域
各个实施方式总体上可能涉及一种制造半导体装置的方法，并且更具体地，涉及一种制造倒装芯片封装(flip chip package)的方法和测试倒装芯片的设备。
背景技术
在制造半导体芯片时，可以在半导体芯片上执行各种级别的测试。未通过这种测试的半导体芯片可以被确定为异常。例如，测试可能与半导体芯片的工艺变化、电压和温度(PVT)、半导体芯片的符号间干扰(ISI)等有关。当及早发现异常半导体芯片时，避免了不必要的成本，从而降低了制造半导体装置的价格。
为了提供小尺寸的半导体装置，已经提出使用凸块(bump)作为导电构件的倒装芯片封装结构作为半导体封装。可以通过以下步骤制造倒装芯片封装：将凸块结合在倒装芯片上，模制(molding)倒装芯片的上部，使用激光标记倒装芯片的模制部分，将焊球附接到倒装芯片上以将焊球与凸块连接，将半导体基板单片化(singulating)以形成多个倒装芯片封装，并且测试每个倒装芯片封装的电特性。
在制造倒装芯片封装中，在将半导体芯片结合到封装基板上时可能经常产生错误。但是，由于可能在模制工艺之后对倒装芯片封装的电特性进行测试，因此可能难以修复倒装芯片封装的错误。
发明内容
根据本公开，一种制造倒装芯片封装的方法包括形成多个半导体芯片并将半导体芯片结合到封装基板的步骤。该方法还包括以下步骤：对封装基板上的多个半导体芯片进行电测试，模制经测试的半导体芯片并且将模制的芯片单片化。对半导体芯片进行电测试的步骤包括利用保护构件覆盖半导体芯片的步骤。
此外，根据本公开，一种用于测试倒装芯片的设备包括：测试壁，该测试壁被配置为限定测试空间；以及测试板，该测试板被布置在测试空间中，以在测试期间设置封装基板，多个半导体芯片电连接到该封装基板。该设备还包括保护构件，该保护构件联接到测试壁并且被配置为在测试期间覆盖半导体芯片。
此外，根据本公开，一种用于测试封装基板上的未模制裸半导体芯片的设备包括保护构件，该保护构件被配置为在测试工艺期间接触封装基板的边缘部分，该保护构件包括被划分为多个分隔件的凹槽，该多个分隔件被配置为单独地容纳半导体芯片。多个分隔件中的每一个具有用于在分隔件和在分隔件中的对应半导体芯片之间形成间隙的尺寸，以在分隔件和半导体芯片的每个表面之间提供空隙。
附图说明
从以下结合附图的详细描述中，将更清楚地理解本公开的主题的上述和其他方面、特征和优点，其中：
图1是示出根据示例实施方式的制造倒装芯片封装的方法的流程图；
图2是示出根据示例实施方式的半导体芯片的立体图；
图3是示出图2的半导体芯片的焊盘区域的截面图；
图4是示出根据示例实施方式的倒装芯片的结合工艺的截面图；
图5是示出根据示例实施方式的测试倒装芯片的设备的截面图；
图6是示出根据示例实施方式的基板固定构件的平面图；
图7是示出根据示例实施方式的保护构件的立体图；
图8是示出根据示例实施方式的保护构件的立体图；
图9是沿图8的线VIII-VIII’获取的截面图；以及
图10是示出根据示例实施方式的半导体芯片的模制工艺和装配工艺的截面图。
具体实施方式
参照附图详细描述本教导的各种实施方式。附图是各种实施方式(和中间结构)的示意图示。因此，由于例如制造技术和/或公差，可以预期与图示的构造和形状不同的变型。因此，所描述的实施方式不应被解释为限于在此示出的特定构造和形状，而是可以包括不脱离所附权利要求所限定的本教导的精神和范围的在构造和形状上的偏差。
本文中参照理想化的实施方式的截面图和/或平面图描述了本教导。然而，本教导的实施方式不应被解释为限制本教导。尽管示出并描述了本教导的一些实施方式，但是本领域普通技术人员将理解，可以在不脱离本教导的原理和精神的情况下对这些实施方式进行改变。
图1是示出根据示例实施方式的制造倒装芯片封装的方法的流程图。
参照图1，根据示例实施方式的制造倒装芯片封装的方法可以包括以下步骤：形成半导体芯片(S1)，将作为倒装芯片的半导体芯片结合(bonding)到封装基板(S2)，对倒装芯片进行电测试(S3)，模制/焊接倒装芯片(S4)以及将倒装芯片单片化(S5)。
形成半导体芯片(S1)
图2是示出根据示例实施方式的半导体芯片的立体图。
参照图2，半导体芯片100可以包括诸如半导体电路的器件层(未示出)、多个导电层(未示出)以及绝缘层(未示出)。
半导体芯片100可以具有焊盘区域Pa。焊盘区域Pa可以位于半导体芯片100的上表面的中央部分。电极焊盘(未示出)可以布置在焊盘区域Pa中。可以在焊盘区域Pa中的电极焊盘上布置多个凸块135。凸块135可以与电连接到半导体电路的导电层直接/间接连接。导电层可以包括连接在器件层之间的布线和布线触点。另选地，焊盘区域Pa可以布置在半导体芯片100的上表面的边缘部分处。
图3是示出图2中的半导体芯片的焊盘区域的截面图。
参照图3，可以在半导体基板101的上表面上形成多个器件层110。器件层110可以包括电路、连接在电路之间的布线(导电层)以及布置在电路和布线之间的绝缘层。电极焊盘115可以布置在器件层110的上表面上的焊盘区域Pa中。电极焊盘115可以与器件层110的至少一个导电层电连接。钝化层120和缓冲层125可以依次形成在电极焊盘115上。可以部分地蚀刻钝化层120和缓冲层125，以暴露电极焊盘115的上表面。因此，可以通过钝化层120和缓冲层125形成被配置为暴露电极焊盘115的开口。钝化层120可以包括用于保护器件层110免受外部环境影响的氧化物层。缓冲层125可以包括绝缘材料、聚酰亚胺或环氧树脂。缓冲层125可以吸收凸块的重量以防止凸块的重量传递到器件层110。
凸块135可以形成在钝化层120和缓冲层125的开口中。凸块135可以电连接到通过开口暴露的电极焊盘115。凸块135可以包括球形焊料凸块。凸块下金属(UBM)130可以插入在凸块135和电极焊盘115之间以防止焊料扩散，从而完成半导体芯片100。
在示例实施方式中，可以在对电极焊盘115进行开口的步骤与形成凸块135的步骤之间通过电极焊盘115执行诸如探针测试的晶圆级别测试。
在示例实施方式中，在形成凸块135以完成半导体芯片100之后，可以另外执行基板背面研磨工艺和切割工艺。
结合倒装芯片(S2)
图4是示出根据示例实施方式的倒装芯片的结合工艺的截面图。
参照图4，结合倒装芯片(S2)的步骤可以包括以下步骤：翻转半导体芯片以使凸块135朝向封装基板200，以及将半导体芯片100结合到封装基板200。
封装基板200可以包括主体层210、上层220和下层230。上层220可以包括电连接到凸块135的第一连接端子220a。下层230可以包括第二连接端子230a。可以在第二连接端子230a和外部装置之间传送电信号。
封装基板200可以包括印刷电路板(PCB)、玻璃基板、柔性膜等。主体层210可以包括电连接在第一连接端子220a和第二连接端子230a之间的电路图案。第一连接端子220a和第二连接端子230a可以包括光阻焊剂。
当通过倒装芯片结合工艺将半导体芯片100的凸块135连接到封装基板200的第一连接端子220a时，半导体芯片100的内部信号可以通过封装基板200的第一连接端子220a、电路图案和第二连接端子230a而被发送到外部装置。此外，外部装置的外部信号可以通过第一连接端子220a、电路图案和第二连接端子230a而被发送到半导体装置100。外部装置可以包括具有逻辑电路、存储器模块的系统,包括逻辑电路的系统以及存储器模块等。
可以使用芯片结合设备的机械压力来执行倒装芯片的结合。
对倒装芯片进行电测试(S3)
图5是示出根据示例实施方式的用于测试倒装芯片的设备的截面图。
可以在模制工艺之前对结合到封装基板200的裸半导体芯片100进行电测试。
在电测试中，可以向封装基板200的第二连接端子230a提供各种电压或各种电流以检测半导体芯片100的凸块135是否可以正常地连接到封装基板200的第一连接端子220a。电测试还可以包括电容测试、电阻测试等。
可以使用图5所示的设备来执行电测试。
参照图5，电测试设备300可以包括装载器310、测试器350和卸载器370。
具有半导体芯片100的封装基板200可以在装载器310中待命。
测试器350可以包括测试壁352、测试板354、基板固定构件356以及保护构件360。
测试壁352可以限定可以在其中执行测试工艺的测试空间。测试壁352可以包括连接到装载器310和卸载器370的门G。封装基板200可以通过门G传送。
测试板354可以布置在由测试壁352限定的测试空间中。
测试板354可以包括基板台354a和支承件354b。基板台354a可以具有用于容纳封装基板200的尺寸。基板台354a可以被配置为与封装基板200的下表面230接触。基板台354a可以包括多个测试引脚355。测试引脚355可以被布置在基板台354a的面向封装基板200的表面上。测试引脚355可以与封装基板200的第二连接端子230a接触。
支承件354b可以被配置为支承基板台354a的下表面的中央部分。支承件354b可以垂直移动。因此，当具有半导体芯片100的封装基板200可以被装载到测试空间中时，支承件354b可以向上移动以使测试引脚355与封装基板200的第二连接端子230a接触。
图6是示出根据示例实施方式的基板固定构件的平面图。
参照图6，基板固定构件356可以具有框架形状。基板固定构件356可以主要将封装基板200固定在测试空间中。尽管未在附图中示出，但是基板固定构件356可以机械地连接到测试壁352或测试板354的至少一部分，以将封装基板200与半导体芯片100固定。
图7是示出根据示例实施方式的保护构件的立体图。
参照图7，保护构件360可以在电测试期间保护被装载到测试设备300中的裸半导体芯片100。保护构件360可以可移动地连接到测试空间的上表面(也被称为测试壁352的一部分)，使得保护构件360能够在垂直方向上上下移动。保护构件360可以具有凹槽H，该凹槽H被配置为容纳被结合到封装基板200的半导体芯片100。保护构件360的凹槽H可以具有在凹槽H的内表面360a与被结合到封装基板200的半导体芯片100的任何外表面之间形成间隙的尺寸。因此，凹槽H的内表面360a可以不与被结合到封装基板200的半导体芯片100的任何外表面接触。例如，为了防止凹槽H的内表面360a与半导体芯片100的外表面之间的接触，凹槽H的深度d可以比半导体芯片100的厚度和凸块135的厚度之和大约1mm至约10mm。此外，保护构件360可以包括具有散热特性、易可加工性和良好的耐久性的导电材料或耗散材料(dissipative material)。
图8是示出根据示例实施方式的保护构件的立体图，图9是沿图8中的线VIII-VIII’获取的截面图。
参照图8和图9，保护构件360还可以包括被布置在凹槽H中以单独地容纳每个半导体芯片100的分隔件365。例如，当八个半导体芯片100被结合到封装基板200时，分隔件365可以在凹槽H中限定八个空间。此外，可以穿过保护构件360和分隔件365形成真空孔367，以在由分隔件365限定的空间中设置半导体芯片100。因此，可以通过真空孔367向每个半导体芯片100提供真空，以牢固地固定半导体芯片100，从而减少对半导体芯片100的损坏。真空孔367可以连接到测试设备中的真空泵。
在下文中，详细描述根据该示例实施方式的测试设备的操作。
可以在模制过程之前将已执行倒装芯片结合工艺(S2)的封装基板200容纳在盒(magazine)中。封装基板200可以被依次装载到装载器310中。盒中的封装基板200可以通过推动器依次装载到装载器310中。
装载器310中的封装基板200可以待命，直到测试器350中的先前测试工艺完成为止。在先前的测试工艺完成之后，可以将装载器310中的封装基板200传送到测试器350。封装基板200可以通过传送带传送到测试器350。
基板固定构件356可以主要将封装基板200固定在测试器350中。保护构件360可以向下移动以使由基板固定构件356固定的封装基板200的边缘部分与保护构件360的边缘部分接触。因此，封装基板200和保护构件360可以完全包围半导体芯片100。
测试板354的支承件354b可以向上移动，使得基板台354a的测试引脚355接触封装基板200的第二连接端子230a。测试板354可以通过测试引脚355为封装基板200的第二连接端子230a提供电流或电压。因此，可以基于从封装基板200发送到半导体芯片100的电流/电压/电阻的电特性来检测半导体芯片100与封装基板200之间(即，凸块135和第一连接端子220a之间)的结合故障，半导体芯片100和凸块135等之间的接触故障等。另选地，测试工艺可以使用其他测试技术以及电流/电压测试。
根据示例实施方式，尽管可能对尚未进行模制工艺的半导体芯片执行电测试，但是因为保护构件360可以完全覆盖半导体芯片100，所以不会损坏半导体芯片100。
在测试工艺之后，封装基板200可以通过门被卸载到卸载器370。因为半导体芯片100尚未模制，所以可以修复在电测试(S3)中被确定为异常的半导体芯片100。
模制/装配(Mounting)和单片化半导体芯片
图10是示出根据示例实施方式的半导体芯片的模制工艺和装配工艺的截面图。
参照图10，可在进行了电测试(S3)和/或修复工艺(S4)的半导体芯片100的凸块135与封装基板200之间形成底部填充层150。底部填充层150可以保护凸块135免受外部环境的影响。可以对底部填充层150进行退火以增强凸块135与封装基板200的第一连接端子220a之间的粘附力。
模制构件160可以形成在封装基板200上以覆盖半导体芯片100。模制构件160可以包括环氧树脂。在对模制构件160进行退火之后，可以在模制构件160上执行激光标记工艺。
诸如焊球的外部端子240可以被装配在封装基板200的第二连接端子230a上。在此，可以改变模制工艺、激光标记工艺和装配工艺的顺序。
可以将半导体芯片100单片化以完成倒装芯片封装。
根据示例实施方式，在将半导体芯片结合到封装基板之后，可以在模制工艺之前执行电测试。因此，因为在执行模制工艺之前执行电测试，所以可以修复半导体芯片与封装基板之间的任何接触故障。然后可以在具有经修复的接触的半导体芯片和封装基板上执行封装工艺。
此外，可以在测试器处安装被配置为在测试工艺中覆盖半导体芯片的保护构件，以减少对裸半导体芯片的损坏。保护构件可以覆盖半导体芯片，以防止在测试工艺中对半导体芯片的影响，从而减少对半导体芯片的可能损坏。
本教导的上述实施方式旨在说明而不是限制本教导。各种替代方案和等效方案是可能的。本教导不限于本文描述的实施方式。本教导也不限于任何特定类型的半导体装置。基于本公开，其他增加、减少或修改是可能的，并且意在落入所附权利要求的范围内。
相关申请的交叉引用
本申请要求于2019年5月10日在韩国知识产权局提交的韩国申请第10-2019-0054896号的优先权，其全部内容通过引用合并于此。

Claims (20)

1.一种制造倒装芯片封装的方法，该方法包括以下步骤：
形成多个半导体芯片；
将所述多个半导体芯片结合到封装基板；
对在所述封装基板上的所述多个半导体芯片进行电测试；
对经测试的所述半导体芯片进行模制；以及
将经模制的所述半导体芯片单片化，
其中，对所述多个半导体芯片进行电测试的步骤包括利用保护构件覆盖所述半导体芯片的步骤。
2.根据权利要求1所述的方法，其中，形成所述多个半导体芯片的步骤包括针对每个半导体芯片的以下步骤：
在具有器件层的半导体基板上形成至少一个电极焊盘；以及
在所述至少一个电极焊盘上形成至少一个导电凸块。
3.根据权利要求2所述的方法，其中，所述封装基板包括：
上层，该上层包括多个第一连接端子；
下层，该下层包括多个第二连接端子；以及
主体层，该主体层插入在所述上层和所述下层之间以将所述多个第一连接端子与所述多个第二连接端子电连接。
4.根据权利要求3所述的方法，其中，将所述半导体芯片结合到所述封装基板的步骤包括以下步骤：翻转所述半导体芯片，以使得每个半导体芯片的所述至少一个导电凸块与所述多个第一连接端子接触。
5.根据权利要求3所述的方法，其中，对所述多个半导体芯片进行电测试的步骤包括以下步骤：通过所述封装基板的所述多个第二连接端子向所述多个半导体芯片施加电压和电流中的至少一者，以测试所述封装基板与所述多个半导体芯片之间的电特性。
6.根据权利要求1所述的方法，该方法还包括以下步骤：在对所述多个半导体芯片进行电测试之后并且在对经测试的所述半导体芯片进行模制之前，在每个半导体芯片的至少一个导电凸块与所述封装基板之间形成底部填充层。
7.根据权利要求1所述的方法，该方法还包括以下步骤：在对所述多个半导体芯片进行电测试之后并且在对经测试的所述半导体芯片进行模制之前，对所述多个半导体芯片中的未通过电测试的半导体芯片进行修复。
8.根据权利要求3所述的方法，该方法还包括以下步骤：在对经测试的半导体芯片进行模制之后并且在将经模制的半导体芯片单片化之前，将外部端子装配到所述多个第二连接端子。
9.一种用于测试倒装芯片的设备，该设备包括：
测试壁，该测试壁被配置为限定测试空间；
测试板，该测试板被布置在所述测试空间中以在测试期间设置封装基板，多个半导体芯片电连接到所述封装基板；以及
保护构件，该保护构件联接到所述测试壁并且被配置为在测试期间覆盖所述半导体芯片。
10.根据权利要求9所述的用于测试倒装芯片的设备，其中，所述测试板包括：
基板台，该基板台被配置为容纳所述封装基板；
支承件，该支承件被配置为支承并垂直移动所述基板台，以使得所述基板台与所述封装基板接触；以及
多个测试引脚，该多个测试引脚被布置在所述基板台上以将所述封装基板的端子与所述基板台电连接，以接收电信号。
11.根据权利要求10所述的用于测试倒装芯片的设备，该设备还包括基板固定构件，该基板固定构件被配置为在将所述封装基板装载到所述测试空间中时固定所述封装基板。
12.根据权利要求9所述的用于测试倒装芯片的设备，其中，所述保护构件包括凹槽，该凹槽被配置为容纳所述半导体芯片。
13.根据权利要求12所述的用于测试倒装芯片的设备，其中，所述凹槽的深度大于所述多个半导体芯片中的半导体芯片的厚度与将所述半导体芯片与所述封装基板电连接的导电凸块的厚度之和。
14.根据权利要求13所述的用于测试倒装芯片的设备，其中，所述凹槽的深度在0.5毫米至10.5毫米之间。
15.根据权利要求13所述的用于测试倒装芯片的设备，其中，所述保护构件还包括分隔件，该分隔件被布置在所述凹槽中，以形成用于单独容纳所述多个半导体芯片中的半导体芯片的空间。
16.根据权利要求15所述的用于测试倒装芯片的设备，其中，所述保护构件还包括真空孔，该真空孔形成在所述分隔件中以向所述空间提供真空。
17.根据权利要求9所述的用于测试倒装芯片的设备，其中：
所述保护构件安装在所述测试壁的上表面处；并且
当电连接有多个半导体芯片的所述封装基板被装载到所述测试空间中时，所述保护构件向下移动以接触所述封装基板的边缘部分。
18.根据权利要求9所述的用于测试倒装芯片的设备，其中，所述保护构件包括导电材料和耗散材料中的至少一者。
19.一种用于测试封装基板上的未模制裸半导体芯片的设备，该设备包括：
保护构件，该保护构件被配置为在测试工艺期间接触所述封装基板的边缘部分，该保护构件包括被划分为多个分隔件的凹槽，该多个分隔件被配置为单独地容纳所述半导体芯片，
其中，所述多个分隔件中的每一个具有用于在所述分隔件和在所述分隔件中的对应半导体芯片之间形成间隙的尺寸，以在所述分隔件和所述半导体芯片的每个表面之间提供空隙。
20.根据权利要求19所述的用于测试封装基板上的未模制裸半导体芯片的设备，其中，所述保护构件还包括用于在所述测试工艺期间向所述分隔件提供真空的真空孔。
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