CN100477194C - 电路板及其制造方法以及半导体封装及其制造方法 - Google Patents
电路板及其制造方法以及半导体封装及其制造方法 Download PDFInfo
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- CN100477194C CN100477194C CNB2006100051723A CN200610005172A CN100477194C CN 100477194 C CN100477194 C CN 100477194C CN B2006100051723 A CNB2006100051723 A CN B2006100051723A CN 200610005172 A CN200610005172 A CN 200610005172A CN 100477194 C CN100477194 C CN 100477194C
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- B05B1/304—Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means designed to control volume of flow, e.g. with adjustable passages the control being effected by relative coaxial longitudinal movement of the controlling element and the spray head the controlling element being a lift valve
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Abstract
本发明公开了一种电路板及其制造方法以及一种半导体封装及其制造方法。所述电路板包括:电路板本体,其具有用于安装半导体器件的半导体器件安装区域;布线图案,其将被电连接到将安装于所述半导体器件安装区域上的半导体器件上;以及,用于覆盖所述布线图案的绝缘层,所述绝缘层具有在其上设置有凸点的区域处形成于其中的开口,所述凸点用于将所述布线图案电连接到安装衬底,其中所述开口的开口尺寸根据所述开口形成的位置而变化。
Description
技术领域
本发明涉及一种电路板及其制造方法以及一种半导体封装及其制造方法。更具体而言,本发明涉及一种其中获得了良好的端子平面度从而改善安装成品率的电路板和该电路板的制造方法,以及包括这种电路板的半导体封装和该半导体封装的制造方法。
背景技术
随着电子设备的尺寸和重量的减小、操作速度的增大以及功能性的增加,需要半导体器件的小型化和集成化。在物理上已经变得难以简单地通过增大半导体芯片的引脚数量来满足这样的需求。近来,取代引脚插入型(pin-insertion-type)半导体封装,已经提出了球栅阵列(BGA)半导体封装和焊盘栅阵(LGA)半导体封装。例如,参照日本未审专利申请公开No.11-102988。
以下将参照附图描述一种已知的BGA半导体封装。
图5A和5B分别是一种已知半导体封装的示意性截面图和示意性底视图。半导体封装101包括插入衬底102、管芯结合(die-bonded)到插入衬底102的上表面的半导体芯片103,以及密封半导体芯片103的密封树脂104。
半导体芯片103的每个芯片电极经由薄的金线(gold wire)106引线键合到形成在插入衬底102的芯片安装表面上的芯片安装表面布线图案105的引出线。芯片安装表面布线图案105通过插入衬底102连接到形成在衬底安装表面(面对安装衬底的表面)上的衬底安装表面布线图案107。衬底安装表面布线图案107的引出线连接到设置在衬底安装表面上的外部端子(焊盘(land))。在每个焊盘和连接于焊盘的布线图案107的引出线的端部上形成有镍镀层108,并且在镍镀层108上形成有金镀层109。
此外,用阻焊剂层111覆盖引出线,该阻焊剂层111在焊盘形成区域中具有开口110。每个焊盘通过该开口电连接到焊球112(见图6)。需注意的是,形成在阻焊剂层111中的开口的开口尺寸(由图5A中的符号A表示)对于所有的焊盘均是相同的。
如图6所示,通过将焊球112结合到安装衬底113的端子114上,将具有上述结构的半导体封装111安装在安装衬底113上。
以下将描述具有上述结构的半导体封装的制造方法。
在已知的半导体封装的制造方法中,首先,如图7A所示,在插入衬底102的芯片安装表面上形成用于安装半导体芯片的管芯安装盘(die pad)115和芯片安装表面布线图案105,并且在与所述芯片安装表面相对的衬底安装表面上形成衬底安装表面布线图案107和焊盘。
然后,如图7B所示,在将光致抗蚀剂116施加到插入衬底102的整个表面上之后,去除设置在管芯安装盘115和将被引线键合到半导体芯片芯片电极的芯片安装表面布线图案105的引出线基部上以及设置在焊盘和衬底安装表面布线图案107的引出线端部上的光致抗蚀剂,从而暴露这些区域。
之后,如图7C所示,通过进行镀镍,在暴露的管芯安装盘115、芯片安装表面布线图案105的引出线基部、焊盘以及衬底安装表面布线图案107的引出线端部上形成镍镀层108。然后,通过进行镀金,在镍镀层108上形成金镀层109,所述镍镀层108形成在暴露的管芯安装盘115、芯片安装表面布线图案105的引出线基部、焊盘以及衬底安装表面布线图案107的引出线端部上。
随后,去除光致抗蚀剂,然后,如图7D所示,将阻焊剂施加到插入衬底102的整个表面从而形成阻焊剂层111。之后,如图7E所示,去除设置在管芯安装盘105、芯片安装表面布线图案105的引出线基部以及焊盘上的阻焊剂,从而形成开口110,以暴露焊盘上的金镀层109。去除阻焊剂使得形成在焊盘上的开口的开口尺寸对于所有焊盘是相同的。
之后,利用其间的安装材料117将半导体芯片103固定在管芯安装盘115上,并且使半导体芯片103的每个芯片电极经由薄的金线106结合到芯片安装表面布线图案105的引出线上。然后,用密封树脂104密封半导体芯片103、薄的金线106、芯片安装表面布线图案105等,由此得到图7F所示的半导体封装101。
发明内容
关于以上描述的已知的半导体封装,在通过将安装衬底的端子结合到焊球上而将半导体封装安装在安装衬底上时,在接近焊球熔点的温度环境下在半导体封装中发生弯曲,导致了安装可靠性的降低。
也就是说,当半导体封装呈凹形弯曲时,半导体封装周边区域中的焊球与安装衬底的端子不接触,即使焊料熔化也不能实现连接。类似地,当半导体封装呈凸形弯曲时,半导体封装中心区域中的焊球与安装衬底的端子不接触,即使焊料熔化也不能实现连接。由于这个原因,相对于已知的半导体封装,安装可靠性低。
所希望的是提供一种能够制造相对于安装衬底具有高安装可靠性的半导体封装的电路板以及该电路板的制造方法,包括这种电路板的半导体封装以及该半导体封装的制造方法。
根据本发明的一实施例,一种电路板包括:电路板本体,其具有用于安装半导体器件的半导体器件安装区域;布线图案,其将被电连接到将安装于所述半导体器件安装区域上的半导体器件上;以及,用于覆盖所述布线图案的绝缘层,所述绝缘层具有在其上设置有凸点(bump)的区域处形成于其中的开口,所述凸点用于将所述布线图案电连接到安装衬底,其中所述开口的开口尺寸根据所述开口形成的位置而变化。
根据本发明的另一实施例,一种电路板的制造方法包括以下步骤:在电路板本体上形成布线图案,所述布线图案将被电连接到将安装于所述电路板本体上的半导体器件上;用绝缘层覆盖所述布线图案;以及,在其上设置有凸点的区域的所述绝缘层中形成开口,所述凸点用于将所述布线图案电连接到安装衬底,其中使所述开口的开口尺寸根据所述开口形成的位置而变化。
根据本发明的另一实施例,一种半导体封装包括:半导体器件;电连接到所述半导体器件的布线图案;覆盖所述布线图案的绝缘层;以及,密封所述半导体器件的密封树脂,所述绝缘层具有在其上设置有凸点的区域处形成于其中的开口,所述凸点用于将所述布线图案电连接到安装衬底,其中所述开口的开口尺寸根据所述开口形成的位置而变化。
根据本发明的另一实施例,一种半导体封装的制造方法包括以下步骤:在电路板本体上形成布线图案,所述布线图案将被电连接到将安装于所述电路板本体上的半导体器件上;用绝缘层覆盖所述布线图案;在其上设置有凸点的区域的所述绝缘层中形成开口,所述凸点用于将所述布线图案电连接到安装衬底;以及,在所述电路板本体上安装半导体器件,将所述布线图案电连接到所述半导体器件,然后用树脂密封所述半导体器件,其中使所述开口的开口尺寸根据所述开口形成的位置而变化。
此处,通过使所述开口的开口尺寸根据所述开口形成的位置而变化,能够依据所述开口形成的位置而改变凸点的高度。
也就是说,在形成凸点时,通常,将相同量的凸点材料提供给其上形成凸点的绝缘层的开口区域(例如,在所有开口中设置具有相同直径和相同质量的焊球),然后,通过加热使凸点材料熔化以形成凸点。在向开口区域提供相同量的凸点材料然后进行加热的情况下,当开口的开口尺寸较大时,在加热后所得凸点的高度较低(参照图9A),而当开口的开口尺寸较小时,在加热后所得凸点的高度较高(参照图9B)。
因此,通过减小在电路板与其上安装电路板的安装衬底之间的距离较大的区域(例如,图8A中由符号B所表示的周边区域,其中半导体封装呈凹形弯曲,以及,图8B中由符号C所表示的中心区域,其中半导体封装呈凸形弯曲)中开口的开口尺寸,并且通过增大在电路板与安装衬底之间的距离较小的区域(例如,图8A中的中心区域和图8B中的周边区域)中开口的开口尺寸,能够在电路板与安装衬底之间的距离较大的区域中形成高的凸点并在电路板与安装衬底之间的距离较小的区域中形成低的凸点。
当绝缘层中的所有开口形成为具有相同的开口尺寸时,如在日本未审专利申请公开No.10-107176中所描述的,可以构想通过依据开口形成的位置提供不同量的凸点材料而使凸点的高度变化,例如,在形成高的凸点时增大所供应的凸点材料的量,并在形成低的凸点时减小所供应的凸点材料的量。然而,为了依据开口形成的位置提供不同量的凸点材料,会增加用于提供凸点材料的工艺步骤的数目,导致了产量的降低,对于凸点高度的控制会变得不够,或者会需要高精度的凸点材料供给器(例如,焊球安装设备)。因此,这种方法并非必然合适。
在根据本发明实施例的电路板或者包括由根据本发明实施例的电路板制造方法所制造的电路板的半导体封装中,在根据本发明实施例的半导体封装或者由根据本发明实施例的半导体封装制造方法所制造的半导体封装中,即使在将半导体封装安装在安装衬底中时发生弯曲,也能够改善相对于安装衬底的安装可靠性。
附图说明
图1A和1B分别是根据本发明一实施例的半导体封装的示意性截面图和示意性底视图;
图2A至2D是示意性截面图,示出了根据本发明一实施例的半导体封装的制造方法;
图3是示意性截面图,示出了形成在根据本发明实施例的半导体封装中的焊球;
图4A和4B是截面图,每一张都示出了将根据本发明一实施例的半导体封装安装在安装衬底上;
图5A和5B分别是一种已知的半导体封装的示意性截面图和示意性底视图;
图6是示意性截面图,示出了将已知半导体封装安装在安装衬底上;
图7A至7F是截面图,示出了一种已知半导体封装的制造方法;
图8A和8B是示意性截面图,示出了半导体封装的弯曲;以及
图9A和9B是截面图,每一张都示出了开口与凸点高度之间的关系。
具体实施方式
现将参照附图描述本发明的实施例。在以下实施例中,将描述其中在将半导体封装安装在安装衬底上时发生凹形弯曲的半导体衬底以作为一个实例(参照图8A)。
图1A和1B分别是根据本发明一实施例的半导体封装的示意性截面图和示意性底视图。类似于以上描述的半导体封装101,半导体封装1包括插入衬底2、管芯结合到插入衬底2的上表面的半导体芯片3,以及密封半导体芯片3的密封树脂4。
半导体芯片3的每个芯片电极经由薄的金线6引线键合到形成在插入衬底2的芯片安装表面上的芯片安装表面布线图案5的引出线。芯片安装表面布线图案5通过插入衬底2连接到形成在衬底安装表面上的衬底安装表面布线图案7。衬底安装表面布线图案7的引出线连接到设置在衬底安装表面上的焊盘(land)。在每个焊盘和连接于焊盘的布线图案7的引出线的端部上形成有镍镀层8,并且在镍镀层8上形成有金镀层9。
此外,用阻焊剂层11覆盖引出线,该阻焊剂层11在焊盘形成区域中设置有开口10。每个焊盘通过该开口电连接到焊球12(见图3)。
在根据本发明实施例的半导体封装中,形成在半导体封装1中心区域(由图1A和1B中的符号b表示)的阻焊剂层11中的开口10的开口尺寸大于形成在周边区域(由图1A和1B中的符号a表示)的阻焊剂层11中的开口10的开口尺寸。
将形成在半导体封装1中心区域的阻焊剂层11中的开口10的开口尺寸设定成大于形成在周边区域的阻焊剂层11中的开口10的开口尺寸的原因在于,根据本发明实施例的半导体封装1在安装于安装衬底期间呈凹形弯曲。也就是说,半导体封装1改变了其形状使得半导体封装1的周边区域与安装衬底之间的距离大于半导体封装1的中心区域与安装衬底之间的距离。
因此,当半导体封装1改变了其形状使得在安装于安装衬底期间半导体封装1的中心区域与安装衬底之间的距离大于半导体封装1的周边区域与安装衬底之间的距离时(例如,如图8B所示,当半导体封装呈凸形弯曲时),有必要将形成在中心区域的阻焊剂中的开口的尺寸设定成小于形成在周边区域的阻焊剂中的开口的尺寸。
以下将描述上述半导体封装的制造方法。也就是说,以下将描述根据本发明一实施例的半导体封装的制造方法。
在根据本发明实施例的半导体封装的制造方法中,按照与已知半导体封装101的制造方法中类似的方式(参照图7A至7D),在插入衬底2上形成管芯安装盘15、芯片安装表面布线图案5、衬底安装表面布线图案7和焊盘,并且形成镍镀层8和金镀层9。然后,在插入衬底2的整个表面之上形成阻焊剂层11(参照图2A)。
然后,如图2B所示,在将光致抗蚀剂16施加到阻焊剂层11的整个表面之后,去除设置在管芯安装盘15和将被引线键合到半导体芯片芯片电极的芯片安装表面布线图案5的引出线的基部上以及设置在焊盘和衬底安装表面布线图案7的引出线的端部上的光致抗蚀剂,从而暴露阻焊剂。
然后去除光致抗蚀剂,使得在半导体封装中心区域中光致抗蚀剂的衬底安装表面上的每个开口区域大于在半导体封装周边区域中光致抗蚀剂的衬底安装表面上的每个开口区域,即,其中在焊盘和衬底安装表面布线图案7的引出线的端部上光致抗蚀剂被去除的区域。因此,在半导体封装中心区域中衬底安装表面上的暴露的阻焊剂区域大于在半导体封装周边区域中衬底安装表面上的暴露的阻焊剂区域。
随后,如图2C所示,通过去除暴露的阻焊剂,在管芯安装盘15和将被引线键合到半导体芯片的芯片电极的芯片安装表面布线图案5的引出线的基部上以及焊盘和衬底安装表面布线图案7的引出线的端部上形成了开口10,从而暴露了焊盘上的金镀层9。需注意的是,由于在半导体封装中心区域中衬底安装表面上的暴露的阻焊剂区域大于在半导体封装周边区域中衬底安装表面上的暴露的阻焊剂区域,所以形成在半导体封装中心区域中衬底安装表面上的阻焊剂中的开口的尺寸大于形成在半导体封装周边区域中衬底安装表面上的阻焊剂中的开口的尺寸。
之后,利用其间的安装材料17将半导体芯片3固定在管芯安装盘15上,并且使半导体芯片3的每个芯片电极经由薄的金线6结合到芯片安装表面布线图案105的引出线上。然后,用密封树脂4密封半导体芯片3、薄的金线6、芯片安装表面布线图案5等,由此得到图2D所示的半导体封装1。
在上述根据本发明实施例的半导体封装中,通过将相同量的焊料材料提供给阻焊剂的开口,之后进行回流处理,能够获得依据开口的开口尺寸的焊球12的高度。也就是说,能够将半导体封装1的周边区域中的焊球12的高度设定成高于在半导体封装1的中心区域中的焊球12的高度(参照图3)。
因此,如图4A所示,当试图通过将焊球12结合到安装衬底13的端子14上而使半导体封装1被安装在安装衬底13上时,即使如图4B所示,在接近焊剂熔点的温度下在半导体封装1中发生弯曲,焊球12的高度差异也能够减小由于半导体封装1的弯曲所致的变形,由此能够实现半导体封装1的令人满意的安装。
此外,通过将阻焊剂中开口的尺寸设定成在半导体封装的中心区域与周边区域之间不同,能够控制焊球的高度。因此,能够以高的精度相对容易地控制焊球的高度。
可以通过其他方法来实现对于焊球高度的控制,例如,(1)通过涂刷器(squeegee)向半导体封装的周边区域和中心区域提供不同量的焊料材料的方法,以及(2)其中在阻焊剂层的开口上安装具有不同体积的精细焊球的方法。然而,在方法(1)中,难以以高的精度控制焊球的高度;而在方法(2)中,尽管能够以高的精度控制焊球的高度,但为了在阻焊剂层的开口上安装具有不同体积的精细焊球,需要高度精确的焊球安装设备。相反,在根据本发明任一实施例的半导体封装中,无需使用高度精确的焊球安装设备,并且仅通过使阻焊剂层中的开口的开口尺寸变化就能够控制焊球的高度,由此能够以高的精度相对容易地控制焊球的高度。
本领域技术人员应理解的是,依据设计需要和其他因素,可以进行各种修改、组合、子组合和变更,只要其在权利要求及其等同物的范围内。
本发明包含与2005年1月20日在日本专利局提交的日本专利申请JP2005-013244相关的主题内容,其全部内容在此引入作为参考。
Claims (8)
1.一种电路板,包括:
电路板本体,其具有用于安装半导体器件的半导体器件安装区域;
布线图案,其将被电连接到将安装于所述半导体器件安装区域的半导体器件上;以及
用于覆盖所述布线图案的绝缘层,所述绝缘层具有在其上设置有凸点的区域处形成于其中的开口,所述凸点用于将所述布线图案电连接到安装衬底,
其中所述开口的开口尺寸根据所述开口形成的位置而变化。
2.根据权利要求1所述的电路板,其中所述开口的开口尺寸随着所述电路板与其上安装所述电路板的所述安装衬底之间距离的增大而减小。
3.一种电路板的制造方法,包括以下步骤:
在电路板本体上形成布线图案,所述布线图案将被电连接到将安装于所述电路板本体上的半导体器件上;
用绝缘层覆盖所述布线图案;以及
在其上设置有凸点的区域的所述绝缘层中形成开口,所述凸点用于将所述布线图案电连接到安装衬底,
其中使所述开口的开口尺寸根据所述开口形成的位置而变化。
4.根据权利要求3所述的电路板的制造方法,其中所述开口的开口尺寸随着所述电路板与其上安装所述电路板的所述安装衬底之间距离的增大而减小。
5.一种半导体封装,包括:
半导体器件;
电连接到所述半导体器件的布线图案;
覆盖所述布线图案的绝缘层,所述绝缘层具有在其上设置有凸点的区域处形成于其中的开口,所述凸点用于将所述布线图案电连接到安装衬底;以及
密封所述半导体器件的密封树脂,
其中所述开口的开口尺寸根据所述开口形成的位置而变化。
6.根据权利要求5所述的半导体封装,其中所述开口的开口尺寸随着所述半导体封装与其上安装所述半导体封装的所述安装衬底之间距离的增大而减小。
7.一种半导体封装的制造方法,包括以下步骤:
在电路板本体上形成布线图案,所述布线图案将被电连接到将安装于所述电路板本体上的半导体器件上;
用绝缘层覆盖所述布线图案;
在其上设置有凸点的区域的所述绝缘层中形成开口,所述凸点用于将所述布线图案电连接到安装衬底;以及
在所述电路板本体上安装半导体器件,将所述布线图案电连接到所述半导体器件,然后用树脂密封所述半导体器件,
其中使所述开口的开口尺寸根据所述开口形成的位置而变化。
8.根据权利要求7所述的半导体封装的制造方法,其中所述开口的开口尺寸随着所述半导体封装与其上安装所述半导体封装的所述安装衬底之间距离的增大而减小。
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JP013244/05 | 2005-01-20 | ||
JP2005013244A JP2006202991A (ja) | 2005-01-20 | 2005-01-20 | 回路基板及びその製造方法、並びに半導体パッケージ及びその製造方法 |
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KR100723529B1 (ko) * | 2006-05-10 | 2007-05-30 | 삼성전자주식회사 | 홀을 갖는 솔더볼 랜드를 구비하는 회로기판 및 이를구비하는 반도체 패키지 |
WO2008032755A1 (en) * | 2006-09-11 | 2008-03-20 | Panasonic Corporation | Electronic component placing apparatus and electronic component mounting method |
JP4963989B2 (ja) * | 2007-03-08 | 2012-06-27 | パナソニック株式会社 | 半導体素子搭載用基板およびその製造方法 |
TW200906263A (en) * | 2007-05-29 | 2009-02-01 | Matsushita Electric Ind Co Ltd | Circuit board and method for manufacturing the same |
US8592691B2 (en) * | 2009-02-27 | 2013-11-26 | Ibiden Co., Ltd. | Printed wiring board |
JP2011243683A (ja) * | 2010-05-17 | 2011-12-01 | Fujitsu Ltd | 電子部品の実装方法、電子部品の製造方法および電子部品、電子部品の製造装置 |
WO2011158456A1 (ja) * | 2010-06-16 | 2011-12-22 | パナソニック株式会社 | 半導体装置及びその製造方法並びに該半導体装置を備えた実装体 |
TWI546911B (zh) * | 2012-12-17 | 2016-08-21 | 巨擘科技股份有限公司 | 封裝結構及封裝方法 |
JP2015088539A (ja) * | 2013-10-29 | 2015-05-07 | 株式会社デンソー | 半導体パッケージ、および、これを実装する配線基板 |
JP2016122802A (ja) | 2014-12-25 | 2016-07-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20210035898A1 (en) * | 2019-07-30 | 2021-02-04 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
CN112701099A (zh) * | 2019-10-22 | 2021-04-23 | 中兴通讯股份有限公司 | 一种封装结构及封装方法 |
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US20010007373A1 (en) * | 2000-01-12 | 2001-07-12 | Yoshinori Kadota | Tape carrier for semiconductor device and method of producing same |
JP3666591B2 (ja) * | 2002-02-01 | 2005-06-29 | 株式会社トッパンNecサーキットソリューションズ | 半導体チップ搭載用基板の製造方法 |
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CN1815726A (zh) | 2006-08-09 |
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