TWI546911B - 封裝結構及封裝方法 - Google Patents

封裝結構及封裝方法 Download PDF

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TWI546911B
TWI546911B TW101147927A TW101147927A TWI546911B TW I546911 B TWI546911 B TW I546911B TW 101147927 A TW101147927 A TW 101147927A TW 101147927 A TW101147927 A TW 101147927A TW I546911 B TWI546911 B TW I546911B
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package substrate
pads
circuit board
flexible package
bumps
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TW101147927A
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TW201426924A (zh
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薛淦浩
楊之光
古永延
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巨擘科技股份有限公司
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Priority to TW101147927A priority Critical patent/TWI546911B/zh
Priority to CN201310025212.0A priority patent/CN103871990A/zh
Priority to EP13192760.0A priority patent/EP2750186A3/en
Priority to US14/079,377 priority patent/US20140167255A1/en
Priority to KR1020130149619A priority patent/KR20140078541A/ko
Priority to JP2013254874A priority patent/JP2014120773A/ja
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Description

封裝結構及封裝方法
本發明係與封裝結構及封裝方法有關,特別是與一種能降低封裝應力之封裝結構及封裝方法有關。
隨著積體電路(Integrated Circuit)技術的發展的積集度飛快發展,相應的封裝技術亦不斷地達到前所未有、創新的技術水準。當前IC裸晶、封裝基板及電路板等元件對外進行電性連接的錫球(solder ball)、凸塊(stud)、焊墊(pad)或電性連接接點不僅數量越來越多、尺寸越來越小,該些錫球、凸塊接點之間的距離亦同樣地不斷縮減(fine pitch),以符合當前電子產品體積不斷地微縮之設計趨勢。同樣地,封裝基板、電路板之厚度亦越來越薄。
一般而言,目前為符合高積集度之封裝需求,覆晶封裝(Flip-Chip)為主要採用之技術。早期採用錫球的直徑(高度bump height),大約為100μm,隨著積體電路積集度的不斷提高,封裝密度亦持續攀升。當前一般業界多已採用凸塊,並且若為球型則直徑約在30μm-50μm,而任何類型之凸塊則高度約在20-30μm之譜。如第1圖所示,現今覆晶封裝(Flip-Chip)中,IC裸晶1包括複數個焊墊(未顯示),會先將複數個直徑為30μm-50μm或高度為20μm-30μm左右之凸塊(stud)2形成於IC裸晶1之表面。硬性封裝基板3上下表面皆具有複數個封裝焊墊(未顯示)。IC裸晶1透過上表面具有之該些凸塊(stud)2與硬性之多層封裝基板3之該些封裝焊墊接觸,實施加壓或加熱之製程後,以進行對IC裸晶1之封裝。所述凸塊(stud)2間之間隔(pitch)大約是100μm左右,視設計要求所需,當前凸塊(stud)2 間之間隔(pitch)甚至可能小至50μm。
如第1圖所示,硬性電路板(PCB)4上表面具有複數個電性連接接點(未顯示)。接著,硬性多層封裝基板3藉由錫球5與硬性電路板4上表面之該些電性連接接點接觸後,實施加壓或加熱之製程後,以使IC裸晶1藉由硬性封裝基板3與硬性電路板4接合。
如前所述,當錫球(solder ball)、凸塊(stud)、焊墊(pad)或電性連接接點數量尚不多,且硬性多層封裝基板3、硬性電路板4亦相對地具有相當之厚度,如第1圖所示,實施加壓或加熱製程,進行硬性多層封裝基板3對IC裸晶1之封裝或進行硬性多層封裝基板3與硬性電路板4之接合,各元件之尺度誤差可容許值較大,然而更重要的問題是,如圖所示,由於硬性多層封裝基板3必然存在厚度不均、不平坦或者因電路設計而金屬層、介電層分佈不可能平均,其表面亦為非平坦的情形,同樣地亦如硬性多層封裝基板3,硬性電路板4必然存在厚度不均、不平坦或者因電路設計而金屬層、介電層分佈不可能平均,其表面亦為非平坦的情形。
一般而言,Flip-Chip技術中,凸塊或錫球接合製程對硬性多層封裝基板3與硬性電路板4施加之壓力可達每平方公分1-10kgf/cm2,對凸塊2、硬性多層封裝基板3、硬性電路板4及錫球5等材料而言均為不小的壓力。是以,進行前述封裝及接合時,硬性多層封裝基板3與硬性電路板4必因複數個凸塊2或複數個錫球5的接合,所承受一定相當程度的應力。前述程度之應力在其相對其他元件具有尺寸較為大的厚度時,並不會對多層封裝基板3與電路板4產生明顯的影響。而現有技術亦有將凸塊2先形成於封裝基板3上後實施加壓或加熱製程, 進行對IC裸晶1之封裝。然其目的僅在消除對IC裸晶1所造成之損傷。
再者,甚至可能進行前述封裝及接合時,出現如圖中所示因IC裸晶1、多層封裝基板3及電路板4皆為硬性、具剛性之元件,而硬性多層封裝基板3,硬性電路板4必然存在厚度不均、不平坦或者因電路設計而金屬層、介電層分佈不可能平均,其表面亦為非平坦的情形,即便凸塊2或錫球5製作得再精細,多個凸塊2之間或多個錫球5之間一定會有存在的大小尺寸形狀等的差異,因而導致空焊、冷焊的情形。
請參閱第2圖,係現有技術中當錫球(solder ball)、凸塊(stud)、焊墊(pad)或電性連接接點數量越來越多,且硬性封裝基板、硬性電路板亦越來越薄,該些元件封裝接合完成之狀態。如第2圖所示,在覆晶封裝(Flip-Chip)製程中,IC裸晶1具有複數個第一焊墊(pad)11,硬性封裝基板3之上表面具有複數個第二焊墊31,下表面具有複數個第三焊墊32。硬性電路板4之上表面具有複數個電性連接接點41。
可先將複數個凸塊(stud)2形成於硬性封裝基板3之上表面,且與硬性封裝基板3之該些第二焊墊(pad)31接合。使該些凸塊2與IC裸晶1之該些第一焊墊11接觸,實施加壓或加熱,以進行對IC裸晶1封裝之製程後。接著,硬性封裝基板3下表面具有之該些第三焊墊32藉由錫球5與硬性電路板4上表面之該些電性連接接點41接觸後,實施加壓或加熱,以使IC裸晶1藉由硬性封裝基板3與硬性電路板4接合之製程後,完成一電子裝置之封裝製作。並且完成前述製作後,會進行翹曲量測。一般在Shadow Moiré翹曲量測儀,實際所得數據大多介於20μm-50μm,由此可明白,現有技術勢必無法避免導致完成 之電子裝置的翹曲發生。如前述凸塊(stud)2之直徑為30μm-50μm或高度為20μm-30μm左右,兩者已為相當之尺度。因此,於凸塊覆晶封裝中,要能解決電路板翹曲的問題是非常重要的課題。
並且,於實施加壓或加熱之製程進行對IC裸晶1之封裝之步驟中現有技術更進一步會在IC裸晶1與硬性封裝基板3之間填充非導電之接合材料,例如環氧樹脂12。其目的不僅在於使相鄰凸塊2、第一焊墊11及第二焊墊31處於絕緣狀態,更重要的是在於加強IC裸晶1與硬性封裝基板3間之接合力,以對抗如前述說明中提及封裝後IC裸晶1與硬性封裝基板3所承受之應力。
並且,相同地於實施加壓或加熱之製程使硬性封裝基板3與硬性電路板4接合之步驟中,現有技術亦更進一步會在硬性封裝基板3與硬性電路板4之間填充非導電之接合材料,例如環氧樹脂6。其目的亦不僅在於使相鄰凸塊2、第一焊墊11及第二焊墊31處於絕緣狀態,更重要的是在於加強硬性封裝基板3與硬性電路板4間之接合力,以對抗如前述說明中提及接合後硬性封裝基板3與硬性電路板4所承受之應力。
特別是當前封裝基板之厚度可製作層間厚度(兩金屬層間之距離或介電層厚度)小於50μm之尺度,甚至小於30μm時,幾乎未見有文獻將基板因承受應力而變形的情形繪示出。然經發明者銳意的觀察,實際上當基板厚度越來越薄至如前述尺度時,如第2圖所示,封裝接合後,硬性封裝基板3與硬性電路板4的確會因封裝接合產生應力。甚至,如第1圖所示硬性多層封裝基板3,硬性電路板4必然存在厚度不均、不平坦或者因電路設計而金屬層、介電層分佈不可能平均,其表面亦為非 平坦的情形,而由於多個凸塊2之間必然會有高度之差異,錫球5亦然。即便凸塊2或錫球5製作得再精細,多個凸塊2之間或多個錫球5之間一定會有存在的大小尺寸形狀等的差異。
是以,若非封裝接合的斷裂而致使電子裝置的失效。亦即會提高後續製作中及採用此封裝之電子裝置成品的使用期間,發生失效(failure)的機率,是以,前述硬性封裝基板3與硬性電路板4間持續存在的應力及封裝接合斷裂的缺陷實際上導致此封裝製程毫無實用性,則即發生空焊、冷焊的情形而直接導致此封裝製程失敗。現有技術的唯一解決方案也僅有如前述填充環氧樹脂,以對抗封裝及接合後,IC裸晶1、硬性封裝基板3及硬性電路板4間存在之應力。並且,需在封裝及接合前先對凸塊2或錫球5的大小尺寸形狀進行嚴格的篩選,加上對硬性封裝基板3與硬性電路板4表面實施所謂的全面平坦化技術製程(CMP,Chemical Mechanical Polishing),以力求提高封裝及接合之良率。
是以,確有一提供封裝過程中能對封裝基板、電路板僅產生極低應力且提高封裝接合良率,避免空焊、冷焊情形發生之封裝結構及封裝方法的必要。
本發明之主要目的在於提供一種封裝結構及封裝方法,特別是在凸塊、焊錫微小化、封裝密度高之封裝過程中對封裝基板、電路板能僅產生極低的應力同時提高封裝接合良率,避免空焊、冷焊情形發生,以解決因凸塊、焊錫之封裝接合對封裝基板、電路板產生應力,導致封裝基板、電路板變形及凸塊、焊錫之接合斷裂而影響產品製造良率與產品使用壽命的問題,甚至因空焊、冷焊情形導致封裝接合失敗的問題。
本發明之封裝結構包括:一IC裸晶,具有複數個裸晶焊墊形成於一表面;一軟性封裝基板,具有複數個上部焊墊形成於一上表面及複數個下部焊墊形成於一下表面;以及複數個凸塊,預先形成於該軟性封裝基板之該上表面,該些凸塊分別具有不同的高度,與該些上部焊墊分別對應,其中該軟性封裝基板之該上表面接合的該些凸塊分別與該些裸晶焊墊接合,用以對該IC裸晶封裝。
本發明之封裝結構更包括一電路板,具有複數個電路板接點,該軟性封裝基板的該下表面形成之該些下部焊墊分別藉由焊錫與該些電路板接點接合。並且本發明之封裝結構中,軟性封裝基板之該上表面不平坦。
本發明提供之封裝方法包括下列步驟:提供一IC裸晶,具有複數個裸晶焊墊形成於一表面;提供一軟性封裝基板,具有複數個上部焊墊形成於一上表面及複數個下部焊墊形成於一下表面;形成複數個凸塊於該軟性封裝基板之該上表面,該些凸塊分別具有不同的高度;以及使該IC裸晶具有該些裸晶焊墊之該表面朝向該軟性封裝基板之該上表面,該些裸晶焊墊分別接觸該些凸塊後,實施加壓或加熱以進行該軟性封裝基板對該IC裸晶之封裝。並且本發明之封裝結構中,軟性封裝基板之該上表面不平坦。
本發明之封裝方法於提供該軟性封裝基板之步驟前,更包括一將該軟性封裝基板自一載板平台分離之步驟。
本發明之封裝方法於形成焊錫之步驟後,更包括一步驟:提供具有複數個電路板接點之一電路板,使該些電路板接點朝向該軟性封裝基板之該下表面,該些焊錫分別接觸該些電路板 接點後,實施加壓或加熱以進行該軟性封裝基板對該電路板之接合。
請參考本發明第3圖,係本發明之封裝結構的簡單示意圖。本發明之封裝結構包括IC裸晶100、軟性封裝基板200、電路板300、複數個凸塊400及複數個焊錫500。如第3圖所示,IC裸晶100具有複數個裸晶焊墊150形成於表面。軟性封裝基板200具有複數個上部焊墊251形成於其上表面,同時具有複數個下部焊墊252形成於其下表面。軟性封裝基板200是如第1圖所示的硬性多層封裝基板3相似的,皆具有多層金屬層及多層介電層所構成,但其具備隨遇平衡,變形密接特性之一多層軟性基板。當然亦與習知技術中提及的硬性多層封裝基板3相似,軟性封裝基板200上表面的上部焊墊251中,至少一個與其他的上部焊墊251並不處於共平面,亦即軟性封裝基板200表面可能是不平坦的。此些凸塊400係分別預先形成在軟性封裝基板200上表面,分別對應之上部焊墊251上,與此些上部焊墊251接合。並且凸塊400與上部焊墊251接合部分之寬度大於凸塊400對應裸晶焊墊150接合部份之寬度。
軟性封裝基板200之製作例如:於一載板平台(未顯示)上交替形成複數個金屬層及複數個介電層。載板平台可以玻璃、晶圓或其他金屬載板為例。金屬層則以金屬剝離製程(Metal Lift Off)形成;介電層則能以聚醯亞胺(Polyimide)為材料,如以旋轉塗佈法(Spin Coating)而形成。本發明採用之軟性多層軟性基板單一層之厚度可小於20μm,甚至可小於10μm。並且,由於所有介電層均採用單一材質,是以多層軟性基板之各層間之應力一致性高。軟性封裝基板200於自載板平台分離後,不 會有翹曲之現象,同時亦能具備柔軟、可折曲、延展性佳等特性,軟性封裝基板200於進行加壓或加熱,或同時加壓及加熱之封裝製程時,皆具備隨遇平衡,變形密接之技術特徵,能在局部區域變形而仍不影響其本身的物理特性及電路特性。再者,本發明之軟性封裝基板200要求符合MIT flex test中當測試彎折曲率半徑R<10mm,甚至彎折曲率半徑R<1mm之標准。
並且,前述凸塊400與上部焊墊251接合之程序能在軟性封裝基板200自載板平台分離前或後,如於自載板平台分離後,以特殊設計之夾持系統並利用設置於軟性封裝基板200下方之支撐構件,進行前述凸塊400與上部焊墊251之接合或者附著於真空吸附之載板平台上,本發明並未有特別之限定。即如前述由於本發明軟性封裝基板200具備不翹曲、平坦、柔軟、可折曲、延展性佳等特性,亦即在封裝製程中或者封裝後,因本發明軟性封裝基板200最重要的特性:於進行加壓或加熱,或同時加壓及加熱之封裝製程時,皆具備隨遇平衡,變形密接之技術特徵。
是以,對IC裸晶100與軟性封裝基板200實施加壓或加熱以進行利用軟性封裝基板200對IC裸晶100之封裝後,由於軟性封裝基板200隨遇平衡,變形密接之可適性,前述之封裝接合對IC裸晶100、軟性封裝基板200及凸塊400僅會產生極低之應力。特別是當前封裝基板之厚度可製作層間厚度(兩金屬層間之距離或介電層厚度)小於50μm之尺度,甚至小於30μm時,無論是封裝製程中抑或封裝製程後,更不會發生如現有技術中因所述應力導致凸塊400封裝接合的斷裂而致使電子裝置的失效。並且,更不會出現如圖中所示因IC裸晶100、電路板300皆為硬性、具剛性之元件,而即便軟性封裝基板200與電 路板300必然存在厚度不均、不平坦或者因電路設計而金屬層、介電層分佈不可能平均,其表面亦為非平坦的情形,加上凸塊400或焊錫500製作得再精細,多個凸塊400之間或多個焊錫500之間一定會有存在的大小、尺寸、形狀等的差異,因而如習知技術發生空焊、冷焊情形,導致電子裝置的封裝及接合失敗的問題。
前述凸塊製程的製作方式可以是一般的錫凸塊(Solder bump),也可以是金凸塊(Gold bump)或打線金凸塊(Gold stud bump),然無論前述何種製程,其凸塊高度必有一定誤差,即便最佳之製造狀況亦存在0.5μm~3μm之差異。是以如前所述,於高密度之封裝製程中,凸塊高度可能僅需20um,甚至更低,而0.5μm~3μm之凸塊高度誤差即可能造成空焊、冷焊情形。同樣的,即使是製作最良好之基板製程,基板焊墊之共平面度亦常見1~5um以上之誤差存在,此多層基板之不平坦,或多個焊墊的不共平面即可能導致空焊、冷焊情形,本發明軟性基板隨遇平衡,變形密接之技術特徵,即能解決封裝高度誤差造成的空焊、冷焊情形。
再者,本發明之電路板300具有複數個電路板接點350。軟性封裝基板200於其下表面形成而具有之該些下部焊墊252分別藉由焊錫500與此些電路板接點350接合。似如前述,由於本發明軟性封裝基板200具備不翹曲、平坦、柔軟、可折曲、延展性佳等特性,亦即在封裝製程中或者封裝後,因本發明軟性封裝基板200最重要的特性:於進行加壓或加熱,或同時加壓及加熱之封裝製程時,皆具備隨遇平衡,變形密接之技術特徵。
是以,對IC裸晶100、軟性封裝基板200與電路板300實 施加壓或加熱以進行軟性封裝基板200藉由焊錫500對電路板300之接合製程,對軟性封裝基板200、電路板300、凸塊400及焊錫500僅會產生極低之應力。特別是當前封裝基板之厚度可製作層間厚度(兩金屬層間之距離或介電層厚度)小於50μm之尺度,甚至小於30μm時,無論是封裝製程中抑或封裝製程後,更不會發生如現有技術中所述因應力導致凸塊400或焊錫500接合的斷裂而致使電子裝置的失效。
是以,依據本發明提供之封裝結構的隨遇平衡,變形密接之技術特徵,在凸塊、焊錫微小化、封裝密度不斷提高之封裝技術領域中,對封裝基板、電路板能僅產生極低的應力。本發明解決因凸塊、焊錫之封裝接合對封裝基板、電路板產生應力,導致封裝基板、電路板變形及凸塊、焊錫之接合斷裂而影響產品製造良率與產品使用壽命的問題。
並且,本發明提供一種封裝方法。請參考第3圖及第4圖。第4圖係表示本發明封裝方法之流程圖。本發明之封裝方法包括下列步驟:步驟410:提供IC裸晶100,具有複數個裸晶焊墊150形成於表面;步驟420:提供軟性封裝基板200,具有複數個上部焊墊251形成於上表面及複數個下部焊墊252形成於下表面,如前述,軟性封裝基板200係可先形成於一載板平台上,或者軟性封裝基板200自載板平台分離後,附著於一真空吸附之載板平台上;步驟430:形成複數個凸塊400於軟性封裝基板200之上表面,將軟性封裝基板200自載板平台分離,該些凸塊分別具有不同的高度; 步驟440:使IC裸晶100具有裸晶焊墊150之表面朝向軟性封裝基板200之上表面,裸晶焊墊150則分別對應且接觸凸塊400後,對IC裸晶100與軟性封裝基板200實施加壓、實施加熱或者加壓同時亦加熱,可視材料而定,以進行軟性封裝基板200對IC裸晶100之封裝,由於軟性封裝基板200具備不翹曲、平坦、柔軟、可折曲、延展性佳等之可適性,因此次步驟之封裝對IC裸晶100及軟性封裝基板200僅會產生極低之應力並且不會發生空焊、冷焊情形,而導致電子裝置之封裝及接合失敗;於前述步驟440後,可更包括一於IC裸晶100及軟性封裝基板200之間填充非導電材料,例如似環氧樹脂,即縫隙充填(underfill)之步驟;並且再前述縫隙充填之步驟後,可更包括一以非導電材料,例如似環氧樹脂對IC裸晶100進行模封(molding)之步驟;步驟450:分別於軟性封裝基板200的下表面之複數個下部焊墊252上形成焊錫500;步驟460:提供電路板300,其具有複數個電路板接點350,使電路板接點350朝向軟性封裝基板200之下表面,使焊錫500分別接觸電路板接點350後,對對IC裸晶100、軟性封裝基板200與電路板300實施加壓或加熱以進行軟性封裝基板200對電路板300之接合。由於軟性封裝基板200具備不翹曲、平坦、柔軟、可折曲、延展性佳等之可適性,因此次步驟之接合對IC裸晶100、軟性封裝基板200及電路板300僅會產生極低之應力。並且不會發生空焊、冷焊情形,而導致電子裝置之封裝及接合失敗。
總言之,由於本發明封裝結構及封裝方法的隨遇平衡,變 形密接之技術特徵特別適用在凸塊、焊錫微小化、封裝密度高之封裝結構中。依據本發明對凸塊、焊錫、封裝基板及電路板皆能僅產生極低的應力。因凸塊、焊錫之封裝接合對封裝基板、電路板產生應力,導致封裝基板、電路板變形或凸塊、焊錫之封裝接合斷裂而影響產品製造良率與產品使用壽命的問題可迎刃而解。再者亦可避免發生因凸塊、焊錫大小、尺寸、形狀等差異發生空焊、冷焊的情形。
雖然本發明已就較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之變更和潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1‧‧‧IC裸晶
11‧‧‧第一焊墊
12‧‧‧環氧樹脂
2‧‧‧凸塊
3‧‧‧硬性多層封裝基板
31‧‧‧第二焊墊
32‧‧‧第三焊墊
4‧‧‧硬性電路板
41‧‧‧電性連接接點
5‧‧‧焊錫
6‧‧‧環氧樹脂
100‧‧‧IC裸晶
150‧‧‧裸晶焊墊
200‧‧‧軟性封裝基板
251‧‧‧上部焊墊
252‧‧‧下部焊墊
300‧‧‧電路板
350‧‧‧電路板接點
400‧‧‧凸塊
500‧‧‧焊錫
第1圖係現有技術之封裝結構的剖面示意圖。
第2圖係現有技術採用硬性封裝基板及硬性電路板進行封裝接合之封裝結構的剖面示意圖。
第3圖係本發明之封裝結構的簡單示意圖。
第4圖係本發明封裝方法之流程圖。
100‧‧‧IC裸晶
150‧‧‧裸晶焊墊
200‧‧‧軟性封裝基板
251‧‧‧上部焊墊
252‧‧‧下部焊墊
300‧‧‧電路板
350‧‧‧電路板接點
400‧‧‧凸塊
500‧‧‧焊錫

Claims (9)

  1. 一種封裝結構,包括:一IC裸晶,具有複數個裸晶焊墊形成於一表面;一軟性封裝基板,具有複數個上部焊墊形成於一上表面及複數個下部焊墊形成於一下表面;以及複數個凸塊,預先形成於該軟性封裝基板之該上表面,該些凸塊分別具有不同的高度,與該些上部焊墊分別對應,其中該軟性封裝基板之該上表面接合的該些凸塊分別與該些裸晶焊墊接合,用以對該IC裸晶封裝,該軟性封裝基板包括複數個金屬層及複數個介電層,所有介電層由單一材質製成。
  2. 如申請專利範圍第1項所述封裝結構,其中形成於該上表面之該些上部焊墊中,至少一焊墊與其他焊墊不處於一共平面。
  3. 如申請專利範圍第1項所述封裝結構,更包括一電路板,具有複數個電路板接點,該軟性封裝基板的該下表面形成之該些下部焊墊分別藉由焊錫與該些電路板接點接合。
  4. 如申請專利範圍第1項所述封裝結構,其中該些凸塊與該些上部焊墊接合部分之寬度大於該些凸塊對應該些裸晶焊墊接合部份之寬度。
  5. 一種封裝方法,包括下列步驟:提供一IC裸晶,具有複數個裸晶焊墊形成於一表面;提供一軟性封裝基板,具有複數個上部焊墊形成於一上表面及複數個下部焊墊形成於一下表面,該軟性封裝基板包括複數個金屬層及複數個介電層,所有介電層由單一材質製成;形成複數個凸塊於該軟性封裝基板之該上表面,該些凸塊分別具有不同的高度;以及 使該IC裸晶具有該些裸晶焊墊之該表面朝向該軟性封裝基板之該上表面,該些裸晶焊墊分別接觸該些凸塊後,實施加壓或加熱以進行該軟性封裝基板對該IC裸晶之封裝。
  6. 如申請專利範圍第5項所述封裝方法,其中形成於該上表面之該些上部焊墊中,至少一焊墊與其他焊墊不處於一共平面。
  7. 如申請專利範圍第5項所述封裝方法,於該加壓或加熱之步驟後更包括一分別於該些下部焊墊上形成焊錫之步驟。
  8. 如申請專利範圍第5項所述封裝方法,於提供該軟性封裝基板之步驟前,更包括一將該軟性封裝基板自一載板平台分離之步驟。
  9. 如申請專利範圍第7項所述封裝方法,於形成焊錫之步驟後更包括一步驟:提供具有複數個電路板接點之一電路板,使該些電路板接點朝向該軟性封裝基板之該下表面,該些焊錫分別接觸該些電路板接點後,實施加壓或加熱以進行該軟性封裝基板對該電路板之接合。
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