JP5657908B2 - インターポーザ基板アセンブリ、電子デバイス・アセンブリ及びこれの製造方法 - Google Patents
インターポーザ基板アセンブリ、電子デバイス・アセンブリ及びこれの製造方法 Download PDFInfo
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- JP5657908B2 JP5657908B2 JP2010096609A JP2010096609A JP5657908B2 JP 5657908 B2 JP5657908 B2 JP 5657908B2 JP 2010096609 A JP2010096609 A JP 2010096609A JP 2010096609 A JP2010096609 A JP 2010096609A JP 5657908 B2 JP5657908 B2 JP 5657908B2
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- conductive contacts
- interposer
- integrated circuit
- circuit chip
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Wire Bonding (AREA)
Description
インターポーザと基板との間に第1の複数の導電性コンタクト及びこれら第1の複数の導電性コンタクトの少なくとも一部を取り囲みインターポーザを基板に結合する接着材料を設けることにより、インターポーザを基板に結合するステップであって、基板は第1の熱膨張率を有する第1材料で構成され、インターポーザは第2熱膨張率を有する第2材料で構成され、第2熱膨張率は第1熱膨張率と異なり、基板の第1材料とインターポーザの第2材料との間に熱膨張係数の不一致が存在し、接着材料はインターポーザを基板に接着すると共に、インターポーザの第2材料と基板の第1材料との間の熱膨張係数の不一致に基づいて第1の複数の導電性コンタクトに加わる応力を減少する上記ステップと、
第2の複数の導電性コンタクトを使用することにより集積回路チップをインターポーザに結合するステップであって、第2の複数の導電性コンタクトの周りには接着材料が設けられておらず、集積回路チップは第2熱膨張率を有する第2材料で構成され、そして第2の複数の導電性コンタクトは第1の複数の導電性コンタクトよりも低いリワーク温度(溶融温度)を有する上記ステップとを含む。
330,730,830 インターポーザ
310,710,810 基板
315,325,615,625,715,725,815,825 導電性コンタクト
331,611,731,831 導電性バイア
332 表面パッド
316,716,816 アンダーフィル接着剤
312、712、812 ボール・グリッド・アレイ
Claims (11)
- 第1熱膨張率を有する第1材料のラミネート基板と、
前記第1熱膨張率と異なる第2熱膨張率を有する第2材料の集積回路チップであって、前記基板の前記第1材料と前記集積回路チップの前記第2材料との間に熱膨張係数の不一致が存在する、前記集積回路チップと、
前記基板に結合され、前記第2熱膨張率を有する前記第2材料で形成され、第1の複数の導電性コンタクト及び該第1の複数の導電性コンタクトの少なくとも一部を取り囲む接着材料を介して、前記基板に結合されたインターポーザであって、前記接着材料は、前記インターポーザを前記基板に接着すると共に前記インターポーザの前記第2材料及び前記基板の前記第1材料の間の熱膨張係数の不一致に基づいて前記第1の複数の導電性コンタクトに加えられる応力を減少する、前記インターポーザと、
前記集積回路チップを前記インターポーザに結合する第2の複数の導電性コンタクトとを備え、
前記第1の複数の導電性コンタクト及び前記第2の複数の導電性コンタクトのうち、前記第1の複数の導電性コンタクトだけに前記接着材料が設けられ、
前記第2の複数の導電性コンタクトは、前記集積回路チップを前記インターポーザへと前記インターポーザからの前記集積回路チップを除去することによる電子デバイス・アセンブリをリワークするための接着材料を使用することなく接着されており、
前記インターポーザは第1の厚さを有し、前記集積回路チップは前記第1の厚さよりも厚い第2の厚さを有し、
前記インターポーザの厚さは、前記集積回路チップの第2の厚さの1/3である、電子デバイス・アセンブリ。 - 第1熱膨張率を有する第1材料のラミネート基板と、
前記第1熱膨張率と異なる第2熱膨張率を有する第2材料の集積回路チップであって、前記基板の前記第1材料と前記集積回路チップの前記第2材料との間に熱膨張係数の不一致が存在する、前記集積回路チップと、
前記基板に結合され、前記第2熱膨張率を有する前記第2材料で形成され、第1の複数の導電性コンタクト及び該第1の複数の導電性コンタクトの少なくとも一部を取り囲む接着材料を介して、前記基板に結合されたインターポーザであって、前記接着材料は、前記インターポーザを前記基板に接着すると共に前記インターポーザの前記第2材料及び前記基板の前記第1材料の間の熱膨張係数の不一致に基づいて前記第1の複数の導電性コンタクトに加えられる応力を減少する、前記インターポーザと、
前記集積回路チップを前記インターポーザに結合する第2の複数の導電性コンタクトとを備え、
前記第1の複数の導電性コンタクト及び前記第2の複数の導電性コンタクトのうち、前記第1の複数の導電性コンタクトだけに前記接着材料が設けられ、
前記第2の複数の導電性コンタクトは、前記集積回路チップを前記インターポーザへと前記インターポーザからの前記集積回路チップを除去することによる電子デバイス・アセンブリをリワークするための接着材料を使用することなく接着されており、
前記インターポーザは第1の厚さを有し、前記集積回路チップは前記第1の厚さよりも厚い第2の厚さを有し、
前記集積回路チップは、薄くされた集積回路チップであり、前記集積回路チップの前記第2の厚さは、通常の集積回路チップの厚さよりも薄く、そして前記インターポーザの厚さの5倍以上である、請求項1に記載の電子デバイス・アセンブリ。 - 前記集積回路チップは第1の薄くされた集積回路チップであり、前記第2材料の第2の薄くされた集積回路チップが、第3の複数の導電性コンタクトを介して前記第1の薄くされた集積回路チップに接続されており、前記第1の複数の導電性コンタクト、前記第2の複数の導電性コンタクト及び前記第3の複数の導電性コンタクトのうち、前記第1の複数の導電性コンタクトだけに前記接着材料が設けられている、請求項1に記載の電子デバイス・アセンブリ。
- 前記第2の複数の導電性コンタクトは、導電性コンタクトのアレイであり、該導電性コンタクトのアレイは前記集積回路チップの外周エッジに近接して設けられた複数の外周部導電性コンタクトを有し、該複数の外周部導電性コンタクトは前記集積回路チップの角部以外に設けられている、請求項1に記載の電子デバイス・アセンブリ。
- 前記第1の複数の導電性コンタクトは第1の面積内に形成され、前記第2の複数の導電性コンタクトは第2の面積内に形成され、前記第1の面積は前記第2の面積よりも大きい、請求項1に記載の電子デバイス・アセンブリ。
- 前記インターポーザは前記第1の面積を有し、前記集積回路チップは第2の面積を有し、前記第1の面積は前記第2の面積よりも大きく、前記インターポーザの前記第1の面積内に設けられた前記第1の複数の導電性コンタクトは前記インターポーザの外周エッジに近接して設けられた複数の外周部導電性コンタクトを有し、該外周部導電性コンタクトは、前記第2の複数の導電性コンタクトにより前記インターポーザに結合されている前記集積回路チップの前記第2の面積の外側に設けられている、請求項5に記載の電子デバイス・アセンブリ。
- 電子デバイス・アセンブリを製造する方法であって、
インターポーザとラミネート基板との間に第1の複数の導電性コンタクト及び前記第1の複数の導電性コンタクトの少なくとも一部を取り囲む接着材料を設けることにより前記インターポーザを前記基板に結合するステップであって、前記基板は第1熱膨張率を有する第1材料で構成され、前記インターポーザは第2熱膨張率を有する第2材料で構成され、前記第2熱膨張率は前記第1熱膨張率と異なり、前記基板の前記第1材料と前記インターポーザの前記第2材料との間に熱膨張係数の不一致が存在し、前記接着材料は電子デバイス・アセンブリをリワークするための接着材料を使用することなく前記インターポーザを前記基板に接着すると共に、前記インターポーザの前記第2材料と前記基板の前記第1材料との間の熱膨張係数の不一致に基づいて前記第1の複数の導電性コンタクトに加わる応力を減少する上記ステップと、
第2の複数の導電性コンタクトにより集積回路チップを前記インターポーザに結合するステップであって、前記第2の複数の導電性コンタクトのうちの所定のコンタクトを、前記第1の複数の導電性コンタクトの所定のコンタクトに電気的に接続するために前記インターポーザの第1主表面から第2主表面にまで延びている導電性バイアを形成して接続し、前記集積回路チップは前記第2熱膨張率を有する前記第2材料で構成され、前記第2の複数の導電性コンタクトが前記第1の複数の導電性コンタクトよりも低い溶融温度を有する上記ステップとを含み、
前記インターポーザは第1の厚さを有し、前記集積回路チップは前記第1の厚さよりも厚い第2の厚さを有し、前記インターポーザの厚さは、前記集積回路チップの第2の厚さの1/3であって、
前記第1の複数の導電性コンタクト及び前記第2の複数の導電性コンタクトのうち、前記第1の複数の導電性コンタクトだけに前記接着材料が設けられている、方法。 - 更に、前記集積回路チップが不良であることに応答して、前記不良である集積回路チップを前記インターポーザから取り外すステップと、
前記不良である集積回路チップに代わる集積回路チップを接続するステップとを含む、請求項7に記載の方法。 - 前記インターポーザは、前記第2の複数の導電性コンタクトのうちの所定のコンタクトを、前記第1の複数の導電性コンタクトの所定のコンタクトに電気的に接続するために前記インターポーザの第1主表面から第2主表面にまで延びている導電性バイアを有する、請求項7に記載の方法。
- 前記集積回路チップを前記インターポーザに接続する前に、前記集積回路チップの厚さを減少するステップを含み、前記インターポーザは第1の厚さを有し、前記集積回路チップは第2の厚さを有し、前記第2の厚さが前記第1の厚さよりも厚い、請求項7に記載の方法。
- 前記集積回路チップは第1の薄くされた集積回路チップであり、
前記第2材料の第2の薄くされた集積回路チップを第3の複数の導電性コンタクトを介して前記第1の薄くされた集積回路チップに接続するステップを含み、
前記第1の複数の導電性コンタクト、前記第2の複数の導電性コンタクト及び前記第3の複数の導電性コンタクトのうち、前記第1の複数の導電性コンタクトだけに前記接着材料が設けられている、請求項7に記載の方法。
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KR101013558B1 (ko) * | 2008-11-06 | 2011-02-14 | 주식회사 하이닉스반도체 | 인터포저 및 이를 이용한 반도체 패키지 |
US7936060B2 (en) * | 2009-04-29 | 2011-05-03 | International Business Machines Corporation | Reworkable electronic device assembly and method |
-
2009
- 2009-04-29 US US12/431,827 patent/US7936060B2/en active Active
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2010
- 2010-03-26 KR KR1020100027296A patent/KR101242796B1/ko not_active IP Right Cessation
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- 2010-04-27 CN CN2010101667705A patent/CN101877341B/zh not_active Expired - Fee Related
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Also Published As
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US20110171756A1 (en) | 2011-07-14 |
US8227264B2 (en) | 2012-07-24 |
KR20100118935A (ko) | 2010-11-08 |
US20100276796A1 (en) | 2010-11-04 |
KR101242796B1 (ko) | 2013-03-12 |
JP2010263205A (ja) | 2010-11-18 |
US7936060B2 (en) | 2011-05-03 |
CN101877341B (zh) | 2013-06-12 |
CN101877341A (zh) | 2010-11-03 |
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