JP5116268B2 - 積層型半導体装置およびその製造方法 - Google Patents
積層型半導体装置およびその製造方法 Download PDFInfo
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- JP5116268B2 JP5116268B2 JP2006224310A JP2006224310A JP5116268B2 JP 5116268 B2 JP5116268 B2 JP 5116268B2 JP 2006224310 A JP2006224310 A JP 2006224310A JP 2006224310 A JP2006224310 A JP 2006224310A JP 5116268 B2 JP5116268 B2 JP 5116268B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
次に、本発明の効果を確認すべくシミュレーションを実施した。その解析モデルおよび解析結果を以下に説明する。
2 第1層の半導体装置
3a、3b 第2層の半導体装置
10 配線基板
11、12a、12b、13 外部接続端子
21 配線基板
22、32a、32b 半導体素子
25 熱硬化性樹脂
Claims (7)
- 配線基板の表面に半導体素子が実装された第1層の半導体装置と、接合手段を介して前記第1層の半導体装置の前記表面側に積層された第2層の半導体装置とを有する積層型半導体装置において、
前記接合手段は、前記第1層の半導体装置と前記第2層の半導体装置との間をはんだによって接合したはんだ接合部と、前記第1層の半導体装置と前記第2層の半導体装置との間を、はんだ溶融温度より低い硬化温度を有する熱硬化性樹脂によって接着固定した接着固定部であり、前記熱硬化性樹脂は、前記第1の配線基板が水平状態となる温度領域で完全硬化することを特徴とする積層型半導体装置。 - 前記熱硬化性樹脂は、150℃以上180℃以下の温度で30秒以上90秒以下の時間加熱することにより完全硬化する樹脂であることを特徴とする請求項1記載の積層型半導体装置。
- 前記熱硬化性樹脂は前記半導体素子の表面にのみ配置されていることを特徴とする請求項1または2記載の積層型半導体装置。
- 前記熱硬化性樹脂は前記半導体素子の複数箇所に配置されていることを特徴とする請求項1または2記載の積層型半導体装置。
- 前記熱硬化性樹脂は前記半導体素子の中央部から端部に向けて十字型に配置されていることを特徴とする請求項3記載の積層型半導体装置。
- 互に積層して配置された第1層および第2層の半導体装置を有する積層型半導体装置の製造方法において、
前記第1層の半導体装置は配線基板の表面に半導体素子が実装されており、
第1層の半導体装置と第2層の半導体装置の間に、両半導体装置を接合するためのはんだおよび熱硬化性樹脂を介在させる工程と、
前記第1層および第2層の半導体装置を、前記第1層の半導体装置の配線基板が水平状態となる第1の温度に加熱して熱硬化性樹脂を硬化させる工程と、
前記第1層および第2層の半導体装置を、第1の温度よりも高い第2の温度に昇温させてはんだを溶融する工程と、
前記第1層および第2層の半導体装置を冷却し、前記はんだを硬化させる工程とを経ることを特徴とする積層型半導体装置の製造方法。 - 熱硬化性樹脂の硬化温度は150℃以上180℃以下であり、加熱時間は30秒以上90秒以下であることを特徴とする請求項6記載の積層型半導体装置の製造方法。
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JP2006224310A JP5116268B2 (ja) | 2005-08-31 | 2006-08-21 | 積層型半導体装置およびその製造方法 |
US11/468,181 US20070045788A1 (en) | 2005-08-31 | 2006-08-29 | Stacking semiconductor device and production method thereof |
US12/501,939 US7863101B2 (en) | 2005-08-31 | 2009-07-13 | Stacking semiconductor device and production method thereof |
US12/958,584 US20110084405A1 (en) | 2005-08-31 | 2010-12-02 | Stacking semiconductor device and production method thereof |
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JP2006224310A JP5116268B2 (ja) | 2005-08-31 | 2006-08-21 | 積層型半導体装置およびその製造方法 |
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-
2006
- 2006-08-21 JP JP2006224310A patent/JP5116268B2/ja not_active Expired - Fee Related
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- 2009-07-13 US US12/501,939 patent/US7863101B2/en not_active Expired - Fee Related
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US20070045788A1 (en) | 2007-03-01 |
US20090275172A1 (en) | 2009-11-05 |
US20110084405A1 (en) | 2011-04-14 |
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