JP4585216B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4585216B2 JP4585216B2 JP2004093895A JP2004093895A JP4585216B2 JP 4585216 B2 JP4585216 B2 JP 4585216B2 JP 2004093895 A JP2004093895 A JP 2004093895A JP 2004093895 A JP2004093895 A JP 2004093895A JP 4585216 B2 JP4585216 B2 JP 4585216B2
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- Prior art keywords
- semiconductor chip
- chip
- semiconductor
- adhesive
- package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
図1は、本実施形態に係るチップ積層型パッケージ100の構成を説明するための断面図である。
102 アイランド
104 半導体チップ
106 金属片
108 半導体チップ
110 銀ペースト系接着剤
112a テープ接着剤
112b テープ接着剤
114a 金ボール
114b 金ボール
116a 金バンプ
116b 金バンプ
117a 金バンプ
117b 金バンプ
118a ワイヤ
118b ワイヤ
120a ワイヤ
120b ワイヤ
122a リード
122b リード
124 封止樹脂
Claims (3)
- リードフレームにより構成された基材と、
前記基材上に積層された複数の半導体素子と、
最上層の前記半導体素子の上に積層された固定板とを含み、
前記基材と、前記基材と接する前記半導体素子との間に、銀ペーストを含む接着剤により構成される接着層を備え、
前記半導体素子間に、絶縁性接着剤により構成される接着層を備え、
最上層の前記半導体素子と前記固定板との間に、絶縁性接着剤により構成される接着層を備え、
前記基材、前記複数の半導体素子、前記固定板、前記銀ペーストを含む接着剤により構成される前記接着層、前記半導体素子間の前記接着層、及び、最上層の前記半導体素子と前記固定板との間の前記接着層を封止する、エポキシ樹脂により構成される封止樹脂を備え、
前記封止樹脂が前記固定板の側面及び上面を覆っていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記固定板が金属片であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記固定板がシリコン片であることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004093895A JP4585216B2 (ja) | 2004-03-26 | 2004-03-26 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004093895A JP4585216B2 (ja) | 2004-03-26 | 2004-03-26 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005285877A JP2005285877A (ja) | 2005-10-13 |
JP4585216B2 true JP4585216B2 (ja) | 2010-11-24 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004093895A Expired - Fee Related JP4585216B2 (ja) | 2004-03-26 | 2004-03-26 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4585216B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013232495A (ja) | 2012-04-27 | 2013-11-14 | Mitsubishi Electric Corp | 半導体装置 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0582672A (ja) * | 1991-09-20 | 1993-04-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2000137781A (ja) * | 1998-10-30 | 2000-05-16 | Hitachi Ltd | カード型電子回路基板及びその製造方法 |
JP2000294723A (ja) * | 1999-04-09 | 2000-10-20 | Matsushita Electronics Industry Corp | 積層型半導体装置およびその製造方法 |
JP2001118877A (ja) * | 1999-10-19 | 2001-04-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2002118198A (ja) * | 2000-10-10 | 2002-04-19 | Toshiba Corp | 半導体装置 |
JP2002141459A (ja) * | 2000-10-31 | 2002-05-17 | Sony Corp | 半導体装置および製造方法 |
JP2003318360A (ja) * | 2002-04-19 | 2003-11-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2005197438A (ja) * | 2004-01-07 | 2005-07-21 | Renesas Technology Corp | Bga型半導体装置 |
JP2005209805A (ja) * | 2004-01-21 | 2005-08-04 | Renesas Technology Corp | 半導体装置およびその製造方法 |
-
2004
- 2004-03-26 JP JP2004093895A patent/JP4585216B2/ja not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0582672A (ja) * | 1991-09-20 | 1993-04-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2000137781A (ja) * | 1998-10-30 | 2000-05-16 | Hitachi Ltd | カード型電子回路基板及びその製造方法 |
JP2000294723A (ja) * | 1999-04-09 | 2000-10-20 | Matsushita Electronics Industry Corp | 積層型半導体装置およびその製造方法 |
JP2001118877A (ja) * | 1999-10-19 | 2001-04-27 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2002118198A (ja) * | 2000-10-10 | 2002-04-19 | Toshiba Corp | 半導体装置 |
JP2002141459A (ja) * | 2000-10-31 | 2002-05-17 | Sony Corp | 半導体装置および製造方法 |
JP2003318360A (ja) * | 2002-04-19 | 2003-11-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2005197438A (ja) * | 2004-01-07 | 2005-07-21 | Renesas Technology Corp | Bga型半導体装置 |
JP2005209805A (ja) * | 2004-01-21 | 2005-08-04 | Renesas Technology Corp | 半導体装置およびその製造方法 |
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JP2005285877A (ja) | 2005-10-13 |
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