JP5409427B2 - プリント回路板及び半導体装置 - Google Patents
プリント回路板及び半導体装置 Download PDFInfo
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Description
また、本発明の半導体装置は、複数の電極を有するインターポーザと、前記インターポーザに搭載された半導体素子と、前記インターポーザの一方の表面に設けられ、前記各電極を露出する複数の開口部が形成されたソルダーレジストと、前記開口部に配置され、前記電極に接続された複数のはんだバンプと、を備え、前記ソルダーレジストの厚さは、前記インターポーザの中央部から外周部に向かって厚くなっていることを特徴とする。
また、本発明の半導体装置は、複数の電極を有するインターポーザと、前記インターポーザに搭載された半導体素子と、前記インターポーザの一方の表面に設けられ、前記各電極を露出する複数の開口部が形成されたソルダーレジストと、前記開口部に配置され、前記電極に接続された複数のはんだバンプと、を備え、前記ソルダーレジストの厚さは、前記インターポーザの外周部から中央部に向かって厚くなっていることを特徴とする。
図1は、本発明の第1実施形態に係る半導体装置の概略構成を示す説明図である。図1(a)に示すように、半導体装置1は、半導体素子2と、半導体素子2が搭載されたインターポーザ6と、を備えており、配線基板としてのマザーボード等のプリント配線基板11に搭載される。
次に、本発明の第2実施形態に係る半導体装置について図3を参照しながら説明する。なお、図3において図1と同じ部材は同じ符号を付し、その説明は省略する。図3に示す本発明の半導体装置1Aのインターポーザ6は、はんだバンプ9a〜9fのはんだ接合時(210℃〜240℃)に上に凸状に反りが発生する点で異なる。
2 半導体素子
5a,5b,5c,5d,5e,5f 電極
6 インターポーザ
8 ソルダーレジスト
8a,8b,8c,8d,8e,8f 開口部
9a,9b,9c,9d,9e,9f はんだバンプ
11 プリント配線基板(配線基板)
Claims (8)
- プリント配線基板と、前記プリント配線基板に搭載された半導体装置と、を備えたプリント回路板において、
前記半導体装置は、
複数の電極を有するインターポーザと、
前記インターポーザに搭載された半導体素子と、
前記インターポーザの一方の表面に設けられ、前記各電極を露出する複数の開口部が形成されたソルダーレジストと、
前記開口部に配置され、前記電極と前記プリント配線基板の基板電極とを接続する複数のはんだバンプと、を備え、
前記開口部を形成するソルダーレジストの厚さが、前記インターポーザの電極と前記プリント配線基板に形成された基板電極との離間距離が大きくなるほど厚くなっていることを特徴とするプリント回路板。 - 前記ソルダーレジストの厚さは、前記インターポーザの電極と前記プリント配線基板に形成された基板電極との離間距離が大きくなるにつれて、段階的に厚くなっていることを特徴とする請求項1に記載のプリント回路板。
- 前記インターポーザは、前記インターポーザの中央部から外周部に向かって、前記プリント配線基板に形成された基板電極との離間距離が大きくなる方向に反っており、前記ソルダーレジストの厚さは、前記半導体装置の中央部から外周部に向かって厚くなっていることを特徴とする請求項1または2に記載のプリント回路板。
- 前記インターポーザは、前記インターポーザの外周部から中央部に向かって、前記プリント配線基板に形成された基板電極との離間距離が大きくなる方向に反っており、前記ソルダーレジストの厚さは、前記半導体装置の外周部から中央部に向かって厚くなっていることを特徴とする請求項1または2に記載のプリント回路板。
- 複数の電極を有するインターポーザと、
前記インターポーザに搭載された半導体素子と、
前記インターポーザの一方の表面に設けられ、前記各電極を露出する複数の開口部が形成されたソルダーレジストと、
前記開口部に配置され、前記電極に接続された複数のはんだバンプと、を備え、
前記ソルダーレジストの厚さは、前記インターポーザの中央部から外周部に向かって厚くなっていることを特徴とする半導体装置。 - 前記ソルダーレジストの厚さは、前記インターポーザの中央部から外周部に向かって、段階的に厚くなっていることを特徴とする請求項5に記載の半導体装置。
- 複数の電極を有するインターポーザと、
前記インターポーザに搭載された半導体素子と、
前記インターポーザの一方の表面に設けられ、前記各電極を露出する複数の開口部が形成されたソルダーレジストと、
前記開口部に配置され、前記電極に接続された複数のはんだバンプと、を備え、
前記ソルダーレジストの厚さは、前記インターポーザの外周部から中央部に向かって厚くなっていることを特徴とする半導体装置。 - 前記ソルダーレジストの厚さは、前記インターポーザの外周部から中央部に向かって、段階的に厚くなっていることを特徴とする請求項7に記載の半導体装置。
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US13/578,109 US8853866B2 (en) | 2010-02-17 | 2011-02-10 | Semiconductor device and stacked-type semiconductor device |
PCT/JP2011/000742 WO2011102100A1 (en) | 2010-02-17 | 2011-02-10 | Semiconductor device and stacked-type semiconductor device |
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US9059106B2 (en) | 2012-10-31 | 2015-06-16 | International Business Machines Corporation | Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip |
US8952532B2 (en) * | 2013-05-13 | 2015-02-10 | Intel Corporation | Integrated circuit package with spatially varied solder resist opening dimension |
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JP6335513B2 (ja) * | 2014-01-10 | 2018-05-30 | 新光電気工業株式会社 | 半導体装置、半導体装置の製造方法 |
TWI588958B (zh) * | 2014-12-11 | 2017-06-21 | 精材科技股份有限公司 | 晶片封裝體及其製作方法 |
US11094658B2 (en) * | 2019-05-22 | 2021-08-17 | Lenovo (Singapore) Pte. Ltd. | Substrate, electronic substrate, and method for producing electronic substrate |
CN112992805B (zh) * | 2021-01-28 | 2022-09-27 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
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JPH08125062A (ja) * | 1994-10-28 | 1996-05-17 | Seiko Epson Corp | 半導体装置とその製造方法 |
JP3885254B2 (ja) * | 1996-08-14 | 2007-02-21 | イビデン株式会社 | プリント配線板の製造方法 |
US6271109B1 (en) * | 1999-07-27 | 2001-08-07 | Texas Instruments Incorporated | Substrate for accommodating warped semiconductor devices |
US6750549B1 (en) | 2002-12-31 | 2004-06-15 | Intel Corporation | Variable pad diameter on the land side for improving the co-planarity of ball grid array packages |
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