KR20120054371A - 원통형 패키지, 이를 이용한 전자장치 및 그 제조방법 - Google Patents

원통형 패키지, 이를 이용한 전자장치 및 그 제조방법 Download PDF

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Publication number
KR20120054371A
KR20120054371A KR1020100115716A KR20100115716A KR20120054371A KR 20120054371 A KR20120054371 A KR 20120054371A KR 1020100115716 A KR1020100115716 A KR 1020100115716A KR 20100115716 A KR20100115716 A KR 20100115716A KR 20120054371 A KR20120054371 A KR 20120054371A
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South Korea
Prior art keywords
substrate
cylindrical
flexible substrate
semiconductor chip
cylindrical package
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KR1020100115716A
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English (en)
Inventor
이강원
김현주
이규제
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에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100115716A priority Critical patent/KR20120054371A/ko
Priority to TW100141992A priority patent/TW201246412A/zh
Priority to US13/298,512 priority patent/US20120127660A1/en
Priority to CN2011103716293A priority patent/CN102479757A/zh
Publication of KR20120054371A publication Critical patent/KR20120054371A/ko

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

본 발명의 원통형 패키지는, 내부에 중공부를 갖는 원통형 기판과, 그리고 상기 원통형 기판의 외주면을 따라 실장된 하나 이상의 반도체 칩을 포함한다.

Description

원통형 패키지, 이를 이용한 전자장치 및 그 제조방법{Cylindrical package, electronic apparatus using the same, and method for fabricating the same}
본 발명은 디자인의 자유도를 증가시키며 곡률을 갖는 전자제품에 채용될 수 있는 원통형 패키지 및 그 제조방법, 그리고 이를 이용한 전자장치에 관한 것이다.
반도체 칩은 수 많은 미세 전기 회로가 집적되어 있으나 그 자체로는 반도체 완제품으로서의 역할을 할 수 없으며, 외부의 물리적, 화학적 충격에 의해 손상될 수 있다. 그러므로 반도체 칩을 기판(리드프레임 또는 인쇄회로기판)에 탑재하여 전기적으로 연결해 주고, 외부의 습기나 불순물로부터 보호할 수 있게 EMC(Epoxy Molding Compound) 등으로 밀봉 포장하여 패키지화한다.
종래의 반도체 패키지는 칩 자체의 본질적인 휨(warpage)이 존재함에도 불구하고 평평한 기판에 평면 형태로 칩을 실장하고 와이어나 범프 등으로 연결시키는 구조를 취하고 있다. 이경우 평판형으로의 물리적 변형에 의한 잔류응력의 영향을 반도체 칩과 패키지가 감수해야 했다. 또한, 향후 다양하고 역동적인 IT 제품의 디자인에 대한 시장의 요구가 더욱 가속화될 것으로 예측된다. 카메라 모듈이나 곡률을 가지는 제품에 대한 소비자의 선호도는 매우 커질 것으로 예상되며 이러한 디자인의 자유도를 더욱 확장시켤 줄 수 있는 반도체 패키지 혹은 모듈의 필요성이 매우 커졌으나 이러한 요구에 부응할 수 있는 반도체 패키지가 존재하지 않는 실정이다.
본 발명이 해결하려는 과제는, 반도체 칩 자체의 본질적인 휨 자체를 수용하여 잔류응력을 감소시키고, 곡면(곡률)을 갖는 전자제품에 채용될 수 있는 반도체 패키지를 제공하는 것이다.
본 발명의 일 실시예에 따른 원통형 패키지는, 내부에 중공부를 갖는 원통형 기판 및 상기 원통형 기판의 외주면을 따라 실장된 하나 이상의 반도체 칩을 포함한다.
일 실시예로, 상기 기판은 플렉서블 기판일 수 있다.
일 실시예로, 상기 기판은 PET, PEN, PES, PAR, PC, COC, PS 및 PI 중에서 어느 하나 이상 선택된 플라스틱을 포함할 수 있다.
일 실시예로, 상기 반도체 칩의 칩패드와 상기 기판의 기판패드를 연결하는 와이어를 포함할 수 있다.
일 실시예로, 상기 기판의 외주면과 상기 반도체 칩의 하부면을 접착하는 접착제를 포함할 수 있다.
일 실시예로, 상기 반도체 칩의 칩패드와 상기 기판의 기판패드를 전기적으로 연결하는 인터커넥션부를 포함할 수 있다.
일 실시예로, 상기 인터커넥션부는 금속범프 또는 솔더범프를 포함할 수 있다.
일 실시예로, 상기 인터커넥션부는 이방성 도전필름을 포함할 수 있다.]
일 실시예로, 상기 반도체 칩을 몰딩하는 몰딩재를 포함할 수 있다.
본 발명의 일 실시예에 따른 전자장치는, 내부에 중공부를 갖는 원통형 기판 및 상기 원통형 기판의 외주면을 따라 실장된 하나 이상의 반도체 칩을 포함하는 원통형 패키지를 포함한다.
일 실시예로, 상기 원통형 패키지의 중공부를 흐르는 냉매를 더 포함할 수 있다.
본 발명의 일 실시예에 따른 원통형 패키지 제조방법은 일면 및 이에 대향하는 타면을 갖는 평평한 플렉서블 기판에 회로패턴을 형성하는 단계; 상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계 및 상기 원통형 플렉서블 기판의 외주면에 하나 이상의 반도체 칩을 실장하는 단계를 포함한다.
또한, 본 발명의 일 실시예에 따른 원통형 패키지 제조방법은 일면 및 이에 대향하는 타면을 갖는 평평한 플렉서블 기판에 회로패턴을 형성하는 단계; 상기 평평한 플렉서블 기판의 일면에 하나 이상의 반도체 칩을 실장하는 단계 및 상기 일면이 외주면이 되도록 상기 평평한 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계를 포함한다.
일 실시예로, 상기 플렉서블 기판은 PET, PEN, PES, PAR, PC, COC, PS 및 PI 중에서 어느 하나 이상 선택된 플라스틱을 포함할 수 있다.
일 실시예로, 상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 접착제를 통해 상기 플렉서블 기판의 양측면을 접착시키는 단계를 포함할 수 있다.
일 실시예로, 상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 상기 플렉서블 기판의 양측면을 용융접합시키는 단계를 포함할 수 있다.
일 실시예로, 상기 플렉서블 기판의 양측면은 암수형 구조일 수 있다.
일 실시예로, 상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 상기 플렉서블 기판의 양측면이 연결된 부위를 체결밴드로 감싸는 단계를 포함할 수 있다.
일 실시예로, 상기 반도체 칩을 실장하는 단계 이후 상기 반도체 칩을 몰딩하는 단계를 더 포함할 수 있다.
일 실시예로, 상기 반도체 칩을 몰딩하는 단계 이후 상기 플렉서블 기판을 절단하여 싱귤레이션하는 단계를 더 포함할 수 있다.
본 발명의 원통형 패키지는, 반도체 칩 자체의 본질적인 휨 자체를 수용하여 잔류응력을 감소시킬 수 있고, 디자인의 자유도를 증가시키며 곡률을 갖는 전자제품에 채용될 수 있는 잇점이 있다.
도 1은 본 발명의 일 실시예에 따른 원통형 패키지의 단면도이다.
도 2는 본 발명의 다른 실시예에 따른 원통형 패키지의 단면도이다.
도 3은 플립칩 인터커넥션부의 다양한 실시예를 나타낸 단면도이다.
도 4a 내지 4e는 본 발명의 일 실시예에 따른 원통형 패키지 제조방법의 공정 흐름도이다.
도 5a 내지 도 5f는 평평한 플렉서블 기판의 양측면을 물리적으로 연결(접착)하는 방법의 다양한 실시예를 나타낸 것이다.
도 6은 본 발명의 일 실시예에 따른 원통형 패키지를 채용한 전자장치의 사시도, 도 7은 도 6의 A-A' 단면도이다.
본 발명의 일 실시예에 따른 원통형 패키지의 단면도인 도 1을 참조하면, 본 발명의 일 실시예에 따른 원통형 패키지는 원통형 기판(100), 하나 이상의 반도체 칩(200, 202, 204, 206, 208, 210, 212, 214)을 포함하며 몰딩재(300)를 더 포함할 수 있다.
기판(100)은 그 내부에 중공부(H)를 가지며 원통형으로 표현되어 있으나 그 단면이 반드시 원형일 필요는 없으면 각종 대칭 또는 비대칭 타원형도 가능하다. 기판(100)은 원형으로 구부려져야 하므로 플렉서블 기재로 이루어질 수 있다. 예를 들어, PET(polyethylene terephthalate), PEN(polyethylene naphthalate), PES(polyether sulfone), PAR(polyarylate), PC(polycarbonate), COC(cycloolefin copolymer), PS(polystyrene) 및 PI(polyimide) 중에서 어느 하나 이상 선택된 플라스틱, 금속재질 등을 포함할 수 있으나 본 발명이 이에 제한되는 것은 아니다. 또 다른 예로, 기판(100)은 복 수개의 절단된 원형(타원형) 모양의 기판을 연결하여 원형으로 구성할 수도 있다. 이 경우 기판(100)은 플렉서블 재질이 아니어도 무방하다.
반도체 칩(200, 202, 204, 206, 208, 210, 212, 214)은 하나 이상 포함되어 있을 수 있으며, 이하에서는 설명의 편의상 하나의 반도체 칩(200)을 기준으로 설명하도록 한다. 반도체 칩(200)에는 메모리소자, 로직로자, 광전소자 또는 파워소자 등의 반도체 소자가 형성될 수 있으며 상기 반도체 소자에는 저항, 콘덴서 등의 각종 수동소자가 포함될 수 있다.
반도체 칩(200)의 하부면과 기판의 외주면(100a) 사이의 접착제(150)는 반도체 칩(200)과 기판(100) 간에 접착력을 부여하여 반도체 칩이 견고하게 부착되도록 할 수 있다. 또한 반도체 칩(200)과 기판(100) 간의 전기적 연결을 위해 와이어(160)에 의해 본딩될 수 있다. 즉, 와이어(160)는 칩패드(도시하지 않음)와 기판의 기판패드(102)를 연결하며 기판의 내주면(100b)에는 다른 전자장치와의 전기적 신호 연결을 위한 접속패드(104)가 형성될 수 있다. 접착제(150)는 접착 조성물을 코팅하여 사용하는 접착제, 양면 테이프 등을 이용할 수 있으며, 반도체 칩(200)과 기판(100)을 연결할 수 있는 접착제면 제한없이 이용할 수 있다.
반도체 칩(200)을 몰딩하는 몰딩재(300)는 반도체 칩(200)을 외부 환경으로부터 보호하기 위해 형성되며 에폭시 몰딩 컴파운드일 수 있다.
도 2는 본 발명의 다른 실시예에 따른 원통형 패키지의 단면도이며, 도 3은 플립칩 인터커넥션부의 다양한 실시예를 나타낸 단면도이다.
도 2 및 도 3을 참조하면, 반도체 칩(200)이 기판(100)의 외주면(100a)에 인터커넥션부(400)에 의해 플립칩(flip chip) 실장될 수 있다.
인터커넥션부(400)는 반도체 칩(200)의 칩패드(220)와 기판(100)의 기판패드(102)를 전기적으로 연결하는 금속범프(402)를 포함할 수 있고(도 3(A)), 반도체 칩(200)과 기판(100)의 사이의 공간을 메우는 언더필수지(450)를 더 포함할 수 있다. 금속범프는 금(Au), 은(Ag), 구리(Cu), 알루미늄(Al), 니켈(Ni), 텅스텐(W), 티타늄(Ti), 백금(Pt), 팔라듐(Pd), 주석(Sn), 납(Pb), 아연(Zn), 인듐(In), 카드뮴(Cd), 크롬(Cr) 및 몰리브덴(Mo)으로 이루어진 군에서 어느 하나 이상 선택된 금속, 도전성 유기물 등을 포함하는 단층막, 다층막일 수 있으며, 무전해도금, 전해도금, 진공증착, 스퍼터링(sputtering) 등에 의해 형성할 수 있다. 구체적 예로, 금속범프(402)는 골드 범프, 골드 스터드(stud) 범프, 니켈 범프일 수 있다. 골드 범프는 무전해도금 또는 전해도금 방법 등에 의해 형성할 수 있으며, Cr/Cu-Cr/Cu/Au, TiW/Au, Ti/Au 등의 UBM(Under Bump Metallurgy)을 사용할 수 있다. 금 스터드 범프는 반도체 칩(200)의 칩패드(220)에 와이어 본더를 이용하여 스터드 범프(골드 볼)를 형성시키는 것으로 UBM 구조를 필요로 하지 않는다. 니켈 범프는 무전해도금 또는 전해도금 등에 의해 형성할 수 있다.
또한, 금속범프(402)와 기판패드(102) 간의 접착력을 향상시키기 위해 도전성 접착제(404)를 금속범프(402)와 기판패드(102) 간에 개재시킬 수도 있으며(도 3(B)), 반도체 칩(200)과 기판(100) 사이의 공간을 메우는 언더필수지(450)를 더 포함할 수 있다.
또한, 인터커넥션부(400)는 칩패드(220)와 기판패드(102)를 전기적으로 연결하는 솔더범프(406) 및 솔더(408)를 포함할 수 있으며(도 3(C)), 반도체 칩(200)과 기판(100) 사이의 공간을 메우는 언더필수지(450)를 더 포함할 수 있다. 솔더란 융점이 약 450℃이하의 금속을 의미한다. 솔더범프(406)는 진공증착, 전해도금, 스크린 인쇄(screen printing) 등에 의해 형성할 수 있으며, 솔더범프의 하부에는 UBM 구조가 더 존재할 수 있다. 전해도금 방법은 공융 솔더를 사용하고 UBM은 TiW를 사용할 수 있다. 스크린 인쇄는 Pb/In/Ag, Sn/Pb/In, Cu/Sb/Ag/An과 같은 솔더를 스텐실 마스크(stencil mask)를 통해 형성하는 방법으로 삼성분계 이상의 무연 솔더를 사용할 수 있으며 공정이 간단하다는 장점이 있다.
또한, 인터커넥션부(400)는 칩패드(220)와 기판패드(102)를 전기적으로 연결하는 금속범프(410) 및 이방성 도전필름(420)을 포함할 수 있다(도 3(D)). 금속범프(410)는 금, 은, 구리, 알루미늄, 니켈, 텅스텐, 티타늄, 백금, 팔라듐, 주석, 납, 아연, 인듐, 카드뮴, 크롬 및 몰리브덴 중에서 어느 하나 이상 선택된 금속, 도전성 유기물 등을 포함하는 단층막, 다층막일 수 있으며, 무전해도금, 전해도금, 진공증착, 스퍼터링 등에 의해 형성할 수 있다. 구체적 예로, 금속범프(410)는 골드 범프, 골드 스터드(stud) 범프, 니켈 범프일 수 있다. 이방성 도전필름(420)에는 도전성 입자(420a)가 들어 있으며 온도를 올리고 가압을 하면 도전성 입자(420a)에 의해 전기적 접촉이 이루어지게 된다. 도전성 입자(420a)는 니켈, 솔더, 은 등으로 이루어진 금속 입자와 카본 입자, 폴리스티렌, 에폭시 수지 등의 플라스틱 입자에 금속막이 피복된 입자 및 도전 입자 표면에 절연 수지가 피복된 입자 등이 가능하나 본 발명이 이에 제한되는 것은 아니다. 이방성 도전필름(420)에 접착성을 부여하는 접착 기재로는 폴리에틸렌계, 폴리프로필렌계의 열가소성 수지, 에폭시계, 폴리우레탄계, 아크릴계 등의 열경화성 수지 및 UV curable 수지 중에서 어느 하나 이상 사용할 수 있으나 본 발명이 이에 제한되는 것은 아니다.
도 4a 내지 4e는 본 발명의 일 실시예에 따른 원통형 패키지 제조방법의 공정 흐름도이고, 도 5a 내지 도 5f는 평평한 플렉서블 기판의 양측면을 물리적으로 연결(접착)하는 방법의 다양한 실시예를 나타낸 것이다.
도 4a를 참조하면, 기판(100)에 반도체 칩과 기타 전자 부품과의 전기적 연결을 위한 쓰루홀(도시하지 않음), 도전성 패턴 등을 형성할 수 있다. 일례로, 기판의 일면(100a)에는 반도체 칩과의 전기적 연결을 위한 기판패드(102)를, 상기 일면(100a)에 대향하는 기판의 타면(100b)에는 완성된 패키지와 기타 전자장치(모듈)와의 전기적 연결을 위한 접속패드(104)를 나타내었다. 기판(100)은 기판은 PET, PEN, PES, PAR, PC, COC, PS 및 PI 중에서 어느 하나 이상 선택된 플라스틱을 포함할 수 있으나, 본 발명이 이에 제한되는 것은 아니다.
도 4b, 도 5a 내지 도 5f를 참조하면, 평평한 플렉서블 기판(100)을 구부려 양측면을 물리적으로 연결하여 중공부(H)를 갖는 원통형 기판을 형성한다.
예를 들어, 기판(100)의 일측면(100c)과 이에 대향하는 타측면(100d) 사이에 접착제(110)를 개재시켜 접착할 수 있으며, 기판의 양측면(100c, 100d)이 분리되지 않도록 체결밴드(112)로 기판의 양측면이 접합하는 부위를 둘러싸도록 할 수 있다(도 5a). 다른 예를 들어, 기판(100)의 일측면(100c)과 이에 대향하는 타측면(100d)이 서로 마주 본 상태에서 순간적으로 열을 가해 용융접합시킬 수 있다. 이 경우 기판의 양측면(100c, 100d)은 용융되어 접합되며 그 경계면은 용융접합면(100e)을 형성하고 상기 용융접합면(100e) 주위로 일정 부분 용융상태 내지 용융상태에 가까운 상태까지 도달했다가 냉각되는 용융부(114)가 존재할 수 있다(도 5b). 또 다른 예를 들어, 접착강도를 향상시키기 위해 기판(100)의 일측면(100c)과 이에 대향하는 타측면(100d)은 그 접촉 부위를 넓게 할 수 있는 구조를 가질 수 있다. 도 5c에는 기판(100)의 일측면(100c)은 'ㄴ'자형, 기판의 타측면(100d)은 'ㄱ'자형 구조를 예시하였으나 그 밖에 다향한 형상을 가질 수 있다. 상기 일측면(100c)과 타측면(100d)의 접촉 부위에는 접착제(110)가 개재될 수 있다. 또 다른 예를 들어, 기판(100)의 일측면(100c)은 'ㄴ'자형, 기판의 타측면(100d)은 'ㄱ'자형 구조를 가져 접촉 부위를 넓게 한 상태에서 용융접합될 수 있다. 용융접합면(100e) 주위로 일정 부분 용융상태 내지 용융상태에 가까운 상태까지 도달했다가 냉각되는 용융부(114)가 존재할 수 있다(도 5d). 또 다른 예를 들어, 기판(100)의 일측면(100c)은 'ㄴ'자형, 기판의 타측면(100d)은 'ㄱ'자형 구조를 가져 접촉 부위를 넓게 한 상태에서 고정구(120)에 의해 체결될 수 있으며(도 5e). 기판(100)의 일측면(100c)과 타측면(100d)은 서로 암수구조를 취할 수 있다. 즉, 기판의 일측면(100c)이 암구조이고 타측면(100d)은 숫구조이거나 기판의 일측면(100c)이 숫구조이고 타측면(100d)이 암구조일 수 있고, 양측면을 체결한 상태에서 고정구(120)에 의해 보다 견고하게 고정될 수 있다(도 5f).
전술한 기판의 양측면(104c, 104d)을 물리적으로 연결(접착)하는 방법의 다양한 실시예는 서로 혼용될 수 있음은 물론이다. 예를 들어, 기판의 양측면(104c, 104d)이 암수구조를 취한 상태에서 용융접착될 수도 있고, 체결밴드로 보다 강하게 체결될 수도 있고, 용융접착과 체결밴드 양자를 모두 취할 수도 있다.
도 4c를 참조하면, 원통형 기판(100)의 외주면(100a)에 하나 이상의 반도체 칩을 실장한다. 반도체 칩은 와이어 본딩, 플립칩 실장 등의 다양한 방식으로 실장될 수 있다. 이를 위해 원통형 기판의 중공부(H)에 회전 샤프트(도시하지 않음)를 체결하고 원통형 기판을 회전시키면서 반도체 칩을 실장할 수도 있고, 원통형 기판을 그대로 둔 상태에서 반도체 칩의 실장장치가 회전하면서 실장할 수도 있다.
도 4d를 참조하면, 반도체 칩(200)을 몰딩재로 몰딩한다. 몰딩재는 에폭시 수지를 포함하는 몰딩재일 수 있다. 에폭시 수지 외에 경화제, 경화촉진제, 필러 또는 기타 첨가제 중 어느 하나 이상을 더 포함할 수 있다. 에폭시 수지의 예로 비스페놀계 에폭시, 페놀 노볼락(Phenol novolac)계 에폭시, 크레졸 노볼락(Cresol novolac)계 에폭시, 다관능 에폭시, 아민계 에폭시, 복소환 함유 에폭시, 치환형 에폭시, 나프톨계 에폭시 및 이들의 유도체로 이루어진 군으로부터 1종 이상 선택된 에폭시를 들 수 있으나 그 제한이 있는 것은 아니다. 경화제는 아민 경화제, 산 무수물 경화제, 폴리아미드 수지, 폴리설파이드 수지, 페놀 수지 중에서 어느 하나 이상을 포함할 수 있으나 그 제한이 있는 것은 아니다. 경화 촉진제는 에폭시 수지와 경화제 사이의 경화 반응을 촉진시키기 위해 사용될 수 있으며, 경화 반응을 촉진시키는 물질이면 무엇이든 가능하다. 예를 들어, 트리에틸아민, 벤질디메틸아민, α-메틸벤질디메틸아민, 및 1,8-디아자비시클로-운데센-7과 같은 아민 화합물, 2-메틸-이미다졸, 2-페닐이미다졸, 2-페닐-4-메틸이미다졸과 같은 이미다졸 화합물, Salicylic acid, 페놀, 트리페닐포스핀, 트리부틸포스핀, 트리(p-메틸페닐)포스핀, 트리(논일페닐)포스핀, 트리페닐포스핀 트리페닐보레이트, 및 테트라페닐포스핀 테트라페닐보레이트와 같은 유기 인 화합물 등이 있으나 본 발명이 이에 제한되는 것은 아니다. 필러는 유기 필러, 무기 필러 중에서 어느 하나 이상을 사용할 수 있으며, 예를 들어 활석, 모래, 실리카, 탈크, 탄산칼슘, 마이카, 석영, Glass fiber, 그라파이트, 알루미나, 산화안티몬(Sb2O3), 티탄산바륨, 벤토나이트 등으로 이루어진 군에서 선택된 어느 하나 이상의 무기 필러, 페놀수지, 요소수지 등으로 유기 비드 등의 유기 필러를 사용할 수 있으나 본 발명이 이에 제한되는 것은 아니다. 에폭시 수지에 칙소트로픽(thixotropic) 성질을 부여하기 위해 콜로이드상의 실리카(aerosil), 벤토나이트 계열의 점토질 필러를 첨가할 수 있다. 기타 첨가제로 유?무기염료 등의 착색제, 커플링제, 소포제 등을 필요에 따라서 첨가할 수 있다
도 4e를 참조하면, 싱귤레이션 단계를 수행할 수 있다. 싱귤레이션(sigulation)은 각각의 패키지(P1, P2, P3, P4, P5)별로 잘라내는(sawing) 공정이다. 하나의 기판에 하나의 패키지가 제작될 수 있으며 이 경우 싱귤레이션 공정을 생략할 수 있다.
한편, 도 4a 내지 4e에서는 평평한 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성한 후 상기 원통형 플렉서블 기판의 외주면에 하나 이상의 반도체 칩을 실장하는 실시예를 나타내었으나 평평한 플렉서블 기판의 일면에 하나 이상의 반도체 칩을 실장한 후 상기 일면이 외주면이 되도록 평평한 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 것도 가능하다.
도 6은 본 발명의 일 실시예에 따른 원통형 패키지를 채용한 전자장치의 사시도, 도 7은 도 6의 A-A' 단면도이다.
도 6 및 도 7을 참조하면, 본 발명의 일 실시예에 따른 원통형 패키지의 내부(중공부)에는 원통형 패키지와 전기적으로 연결되어 전기신호를 주고받을 수 있는 전자모듈(500)이 존재한다. 전자모듈(500) 또한 중공부를 가지고 있으며 전자모듈(500)과 원통형 패키지에서 발생하는 열을 식히기 위한 냉매(600)가 전자모듈(500)의 중공부를 흐르도록 할 수 있다. 원통형 패키지에 대해서는 전술하였으므로 그 설명을 생략하기로 한다. 냉매(600)는 증류수, 빗물, 수돗물 등의 물일 수 있으나 그 밖에 다른 냉매가 사용될 수도 있다.
100...기판 102...기판패드
104...접속패드 112...체결밴드
120...고정구 150, 404...접착제
160...와이어 220...칩패드
200, 202, 204, 206, 208, 210, 212, 214...반도체칩
300...몰딩재 400...인터커넥션부
402, 410...금속범프 406...솔더범프
408...솔더 420...이방성 도전필름

Claims (19)

  1. 내부에 중공부를 갖는 원통형 기판; 및
    상기 원통형 기판의 외주면을 따라 실장된 하나 이상의 반도체 칩
    을 포함하는 원통형 패키지.
  2. 제1항에 있어서,
    상기 기판은 플렉서블 기판으로 이루어진 원통형 패키지.
  3. 제1항에 있어서,
    상기 기판은 PET, PEN, PES, PAR, PC, COC, PS 및 PI 중에서 어느 하나 이상 선택된 플라스틱을 포함하는 원통형 패키지.
  4. 제1항에 있어서,
    상기 반도체 칩의 칩패드와 상기 기판의 기판패드를 연결하는 와이어를 포함하는 원통형 패키지.
  5. 제4항에 있어서,
    상기 기판의 외주면과 상기 반도체 칩의 하부면을 접착하는 접착제를 포함하는 원통형 패키지.
  6. 제1항에 있어서,
    상기 반도체 칩의 칩패드와 상기 기판의 기판패드를 전기적으로 연결하는 인터커넥션부를 포함하는 원통형 패키지.
  7. 제6항에 있어서,
    상기 인터커넥션부는 금속범프 또는 솔더범프를 포함하는 원통형 패키지.
  8. 제6항에 있어서,
    상기 인터커넥션부는 이방성 도전필름을 포함하는 원통형 패키지.
  9. 제1항에 있어서,
    상기 반도체 칩을 몰딩하는 몰딩재를 포함하는 원통형 패키지.
  10. 제1항의 원통형 패키지를 포함하는 전자장치.
  11. 제10항에 있어서,
    상기 원통형 패키지의 중공부를 흐르는 냉매를 더 포함하는 전자장치.
  12. 일면 및 이에 대향하는 타면을 갖는 평평한 플렉서블 기판에 회로패턴을 형성하는 단계;
    상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계; 및
    상기 원통형 플렉서블 기판의 외주면에 하나 이상의 반도체 칩을 실장하는 단계
    를 포함하는 원통형 패키지 제조방법.
  13. 제12항에 있어서,
    상기 플렉서블 기판은 PET, PEN, PES, PAR, PC, COC, PS 및 PI 중에서 어느 하나 이상 선택된 플라스틱을 포함하는 원통형 패키지 제조방법.
  14. 제12항에 있어서,
    상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 접착제를 통해 상기 플렉서블 기판의 양측면을 접착시키는 단계를 포함하는 원통형 패키지 제조방법.
  15. 제12항에 있어서,
    상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 상기 플렉서블 기판의 양측면을 용융접합시키는 단계를 포함하는 원통형 패키지 제조방법.
  16. 제12항에 있어서,
    상기 플렉서블 기판의 양측면은 암수형 구조인 원통형 패키지 제조방법.
  17. 제12항에 있어서,
    상기 플렉서블 기판의 양측면을 연결하여 원통형 플렉서블 기판을 형성하는 단계는 상기 플렉서블 기판의 양측면이 연결된 부위를 체결밴드로 감싸는 단계를 포함하는 원통형 패키지 제조방법.
  18. 제12항에 있어서,
    상기 반도체 칩을 실장하는 단계 이후 상기 반도체 칩을 몰딩하는 단계를 더 포함하는 원통형 패키지 제조방법.
  19. 제18항에 있어서,
    상기 반도체 칩을 몰딩하는 단계 이후 상기 플렉서블 기판을 절단하여 싱귤레이션하는 단계를 더 포함하는 원통형 패키지 제조방법.
KR1020100115716A 2010-11-19 2010-11-19 원통형 패키지, 이를 이용한 전자장치 및 그 제조방법 KR20120054371A (ko)

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TW100141992A TW201246412A (en) 2010-11-19 2011-11-17 Cylindrical packages, electronic apparatus including the same, and methods of fabricating the same
US13/298,512 US20120127660A1 (en) 2010-11-19 2011-11-17 Cylindrical packages, electronic apparatus including the same, and methods of fabricating the same
CN2011103716293A CN102479757A (zh) 2010-11-19 2011-11-21 圆筒形封装体及其制造方法、电子装置

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