CN101330069B - 倒装片封装及其制造方法 - Google Patents

倒装片封装及其制造方法 Download PDF

Info

Publication number
CN101330069B
CN101330069B CN200710149631XA CN200710149631A CN101330069B CN 101330069 B CN101330069 B CN 101330069B CN 200710149631X A CN200710149631X A CN 200710149631XA CN 200710149631 A CN200710149631 A CN 200710149631A CN 101330069 B CN101330069 B CN 101330069B
Authority
CN
China
Prior art keywords
conducting polymer
circuit board
printed circuit
pcb
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200710149631XA
Other languages
English (en)
Other versions
CN101330069A (zh
Inventor
金圣哲
徐敏硕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101330069A publication Critical patent/CN101330069A/zh
Application granted granted Critical
Publication of CN101330069B publication Critical patent/CN101330069B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种倒装片封装及其制造方法。该倒装片封装实现了精细节距且改善了凸点结合的可靠性。该倒装片封装包括：印刷电路板，在其一个表面上具有多个电极端子；面向下半导体芯片，位于印刷电路板上且具有多个接合垫；导电聚合物，用于将半导体芯片的接合垫电和机械连接到印刷电路板的电极端子；和密封剂，用于模塑包括导电聚合物和半导体芯片的印刷电路板的一个表面。

Description

倒装片封装及其制造方法
技术领域
本发明涉及一种倒装片封装，且更具体而言，涉及一种可以实现精细节距并改善凸点结合的可靠性的倒装片封装，及其制造方法。
背景技术
随着各种电或电子产品具有朝向微型化的趋势，研究者被积极地要求将更多数量的半导体芯片安装到印刷电路板并且具有有限的尺寸，从而实现微型化和高容量。另外，安装到印刷电路板的半导体封装的尺寸也已经减小。
例如，在本领域中已经提出了一种芯片尺寸封装，其中半导体芯片的尺寸大于封装的总体尺寸的80％。因此芯片尺寸封装就轻重量、纤细、紧凑和微型化而言具有优点，其已经被发展为各种形状。
同时，通过使用引线框架的焊接方法，典型的半导体芯片和一些芯片尺寸封装被安装到印刷电路板。然而，虽然使用引线框架的焊接方法就加工能力和可靠性而言提供了优点，因为半导体芯片和印刷电路板之间的电信号产生路径的长度增加，电特性很可能被降低。
因此，为了最小化半导体芯片和印刷电路板之间的电信号传输路径的长度，在本领域中已经披露了使用凸点的倒装片封装。
图1为示出根据常规技术的倒装片封装的剖面图。
参考图1，倒装片封装100具有一种结构，其中半导体芯片102和印刷电路板105通过凸点104被彼此机械接合和彼此电连接。
在倒装片封装100中，因为半导体芯片102和印刷电路板105之间的电信号传输仅通过凸点104的介质来完成，所以缩短了信号传输路径，且因此就电特性而言提供了优点。
在图1中，未解释的参考标号106和107分别指示底填(underfill)材料和焊料球，且未解释的参考标号108指示密封剂。
然而，常规倒装片封装遇到的问题在于半导体芯片和印刷电路板使用包含金属的金属化合物的焊料凸点来彼此机械和电连接。
具体而言，由于金属间化合物的形成，该金属间化合物可以通过连接金属材料，比如连接焊料凸点和半导体芯片的接合垫、或比如连接焊料凸点和印刷电路板的电极端子来产生，凸点结合的可靠性可能降低。而且，当进行比较复杂的倒装片接合工艺时，因为上述的材料彼此接合，加工缺陷可能产生。另外，如果缺陷产生，因为必须加入去除该缺陷的另一工艺，制造成本增加。
另外，当将焊料凸点结合到半导体芯片的接合垫或将焊料凸点结合到印刷电路板的电极端子时，由于使用了焊剂则必须加入一工艺，由此在制造工艺中导致了其他问题，因为金属材料之间的接合特性不良。
另外，当将半导体芯片贴附到印刷电路板时，在要求精细节距的倒装片封装的制造中产生了困难，因为由金属化合物制成的焊料凸块的破碎或短路可能产生。
发明内容
本发明的一实施方式涉及改善凸点结合的可靠性的倒装片封装及其制造方法。
本发明的另一实施方式涉及一种倒装片封装及其制造方法，该倒装片封装减轻了制造工艺中的困难。
本发明的又一实施方式涉及一种倒装片封装及其制造方法，该倒装片封装实现了精细节距。
在一个方面，倒装片封装包括：印刷电路板，在其一个表面上具有多个电极端子；面向下半导体芯片，位于印刷电路板上且具有多个接合垫；导电聚合物，用于将半导体芯片的接合垫电和机械连接到印刷电路板的电极端子；和密封剂，用于模塑包括导电聚合物和半导体芯片的印刷电路板的一个表面。
导电聚合物形成以具有5-500μm、优选地为50-200μm的尺寸。
导电聚合物包含导电颗粒。
导电聚合物包括选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
焊料球被贴附到印刷电路板的下表面。
在另一方面，制造倒装片封装的方法包括的步骤为：在位于半导体芯片上的多个接合垫上形成核生长层；在核生长层上允许核生长，从而生长导电聚合物；将具有生长导电聚合物的半导体芯片贴附到在其一个表面上具有多个电极端子的印刷电路板，使得接合垫和电极端子通过导电聚合物彼此电和机械连接；且使用密封剂，模塑具有贴附于其的半导体芯片的印刷电路板的一个表面。
导电聚合物形成以具有50-500μm的尺寸。
导电聚合物由选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
在使用密封剂模塑印刷电路板的一个表面的步骤之后，该方法还包括在印刷电路板的下表面上形成焊料球。
在又一方面，制造倒装片封装的方法包括的步骤为：在具有多个接合垫的半导体芯片上形成掩模，以暴露接合垫；通过丝网印刷，在通过掩模暴露的接合垫上形成导电聚合物；移除掩模；将具有形成的导电聚合物的半导体芯片贴附到在其一个表面上具有多个电极端子的印刷电路板，使得接合垫和电极端子通过导电聚合物彼此电和机械连接；且使用密封剂，模塑具有贴附于其的半导体芯片的印刷电路板的一个表面。
掩模由金属或光致抗蚀剂形成。
导电聚合物形成以具有5-500μm、优选地为50-200μm的尺寸。
导电颗粒被加入到导电聚合物。
导电聚合物包括选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
在使用密封剂模塑印刷电路板的一个表面的步骤之后，该方法还包括在印刷电路板的下表面上形成焊料球。
附图说明
图1为示出根据常规技术的倒装片封装的剖面图。
图2为示出根据本发明的实施方式的倒装片封装的剖面图。
图3A到3E为示出根据本发明的另一实施方式的倒装片封装的制造方法的工艺的剖面图。
图4A到4G为示出根据本发明的又一实施方式的倒装片封装的制造方法的工艺的剖面图。
具体实施方式
在本发明中，倒装片封装由使用导电聚合物电和机械相互连接半导体芯片和印刷电路板来制造。
倒装片封装由使用非金属的导电聚合物将半导体芯片连接到印刷电路板来构造，由于导电聚合物的特性，则可以避免根据常规技术由金属化合物制成的焊料凸点的破裂或延展。例如，导电聚合物具有比如出色的回力。因此，在本发明中，可以实现具有精细节距的倒装片封装，且可以改善凸点结合。
而且，在本发明中，因为使用了导电聚合物，不需要用于形成焊剂的附加工艺来改善焊料凸点和半导体芯片的接合垫之间或焊料凸点和印刷电路板的电极端子之间的连接特性。因此，可以防止在其他工艺中产生缺陷，由此可以防止封装的成本增加和制造产率下降。
其后，将参考图2详细描述根据本发明的实施方式的倒装片封装。
根据本发明的倒装片封装200具有一种结构，其中具有多个接合垫201的面向下半导体芯片202被贴附到在其一个表面上具有多个电极端子203的印刷电路板205。
半导体芯片202的接合垫201和印刷电路板205的电极端子203通过导电聚合物204的介质彼此电和机械连接。包括导电聚合物204和半导体芯片202的印刷电路板205的一个表面使用密封剂206来模塑，使得半导体芯片202被保护免受外部应力影响，密封剂206例如为环氧模塑化合物(EMC)。而且，用作安装构件的多个焊料球207被贴附到印刷电路板205的下表面。
导电聚合物204由包含大量导电颗粒的材料制成，且形成以具有约5-500μm、优选50-200μm的尺寸。例如，导电聚合物204由选自由包含有机磺酸的聚合物、包含噻吩、吡咯及其衍生物的任意一种的聚合物、包含聚乙烯二氧噻吩的聚合物、和包含聚磺苯乙烯的聚合物组成的组的一种形成。
在本发明中，因为倒装片封装由使用导电聚合物将半导体芯片和印刷电路板彼此电和机械连接来构造，可以改善凸点结合的可靠性，且可以减轻制造工艺的难度。
图3A到3E为示出根据本发明的另一实施方式的倒装片封装的制造方法的工艺的剖面图。
参考图3A，制备在其一个表面上具有多个接合垫301的半导体芯片302。在半导体芯片302的各个接合垫301上形成用于生长导电聚合物的核生长层“A”。
参考图3B和3C，在核生长层“A”上生长导电聚合物304以具有预定的高度，由此执行与常规凸点相同的功能。这里，导电聚合物304生长以具有约5-500μm、优选50-200μm的尺寸，而且包含大量的导电颗粒。
例如，通过生长选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、包含聚乙烯二氧噻吩的聚合物、和包含聚磺苯乙烯的聚合物组成的组的一种来形成导电聚合物304。
参考图3D，半导体芯片302通过导电聚合物304的介质被贴附到具有多个电极端子303的印刷电路板305，电极端子303对应于半导体芯片302的接合垫301。
参考图3E，通过比如EMC的密封剂306，模塑印刷电路板305的一个表面，该表面包括导电聚合物304和通过导电聚合物304的介质而贴附的半导体芯片302，使得半导体芯片302被保护免受外部应力影响。然后，用作对外部电路的连接端子的焊料球307被贴附到印刷电路板305的下表面，由此完成了根据本实施方式的倒装片封装300的制造。
在本发明中，因为使用不是金属化合物的导电聚合物来制造倒装片封装，可以改善凸点结合的可靠性并可以实现精细节距。
图4A到4G为示出根据本发明的又一实施方式的倒装片封装的制造方法的工艺的剖面图。
参考图4A和4B，制备在其一个表面上具有多个接合垫401的半导体芯片402。在半导体芯片402上形成掩模408以暴露接合垫401。掩模408由金属或光致抗蚀剂形成。
参考图4C、4D和4E，通过丝网印刷在通过掩模408暴露的半导体芯片402的接合垫401上印刷导电聚合物404，导电聚合物404执行与常规凸点相同的功能并具有预定形状。导电聚合物404被印刷以具有约5-500μm、优选50-200μm的尺寸，而且在其中包含大量的导电颗粒。导电聚合物404由选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种来形成。
参考图4F，在移除掩模408之后，半导体芯片402通过导电聚合物404的介质被贴附到具有多个电极端子403的印刷电路板405，电极端子403对应于半导体芯片402的接合垫401。
参考图4G，通过比如EMC的密封剂406，模塑印刷电路板405的一个表面，该表面包括导电聚合物404和通过导电聚合物404的介质而贴附的半导体芯片402，使得半导体芯片402被保护免受外部应力影响。然后，用作对外部电路的连接端子的焊料球407被贴附到印刷电路板405的下表面，由此完成了根据本实施方式的倒装片封装400的制造。
在本发明的第三实施方式中，因为形成导电聚合物并使用导电聚合物来制造倒装片封装，可以获得与第二实施方式的相同的效果。具体而言，通过根据与使用生长核的生长导电聚合物的方法相比相对优选的丝网印刷技术来形成导电聚合物，可以更容易实施利用导电聚合物的倒装片封装的制造。
虽然相对于芯片级示出并说明了本发明的上述的实施方式，本发明的实施方式也可以被应用于晶片级以获得相同的效果。具体而言，在导电聚合物被应用于晶片级封装以取代焊料凸点的情形，可以仅利用导电聚合物而不使用底填材料来形成封装。
从以上的描述显见，本发明提供的优点在于，因为利用导电聚合物将半导体芯片和印刷电路板彼此连接，可以避免根据常规技术的由金属化合物制成的凸点的破坏或扩展。因此，在本发明中，可以改善凸点结合的可靠性，并可以实现精细节距。
虽然为了说明的目的描述本发明的具体实施方式，然而本领域的技术人员可以理解，在不脱离在所附权利要求中所披露的本发明的范围和精神的情况下，各种修改、添加和替换是可能的。
本申请要求于2007年6月20日提交的韩国专利申请No.10-2007-00的优先权，其整体以引用的方式引入于此。

Claims (18)

1.一种倒装片封装，包括：
印刷电路板，在其一个表面上具有多个电极端子；
面向下半导体芯片，位于所述印刷电路板上且具有多个接合垫；
导电聚合物，用于将所述半导体芯片的接合垫电和机械连接到所述印刷电路板的电极端子；
密封剂，用于模塑包括所述导电聚合物和所述半导体芯片的所述印刷电路板的一个表面，以及
其中所述导电聚合物形成在各个接合垫上，以使形成在每个接合垫上的导电聚合物彼此隔开。
2.根据权利要求1所述的倒装片封装，其中所述导电聚合物形成以具有5-500μm的尺寸。
3.根据权利要求2所述的倒装片封装，其中所述导电聚合物形成以具有50-200μm的尺寸。
4.根据权利要求1所述的倒装片封装，其中所述导电聚合物包含导电颗粒。
5.根据权利要求1所述的倒装片封装，其中所述导电聚合物包括选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
6.根据权利要求1所述的倒装片封装，还包括被贴附到所述印刷电路板的下表面的焊料球。
7.一种制造倒装片封装的方法，包括的步骤为：
在位于半导体芯片的上表面上的多个接合垫上形成核生长层；
在所述核生长层上允许核生长，从而生长导电聚合物；
将具有生长导电聚合物的所述半导体芯片贴附到在其一个表面上具有多个电极端子的印刷电路板，使得所述接合垫和电极端子通过所述导电聚合物彼此电和机械连接；和
使用密封剂，模塑具有贴附于其的所述半导体芯片的所述印刷电路板的一个表面。
8.根据权利要求7所述的方法，其中所述导电聚合物形成以具有5-500μm的尺寸。
9.根据权利要求7所述的方法，其中所述导电聚合物形成以具有50-200μm的尺寸。
10.根据权利要求7所述的方法，其中导电颗粒被加入导电聚合物。
11.根据权利要求7所述的方法，其中所述导电聚合物包括选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
12.根据权利要求7所述的方法，其中，在使用所述密封剂模塑所述印刷电路板的一个表面的步骤之后，该方法还包括在所述印刷电路板的下表面上形成焊料球的步骤。
13.一种制造倒装片封装的方法，包括的步骤为：
在具有多个接合垫的半导体芯片上形成掩模，以暴露所述接合垫；
通过丝网印刷，在通过所述掩模暴露的所述接合垫上形成导电聚合物；
移除所述掩模；
将具有形成的导电聚合物的所述半导体芯片贴附到在其一个表面上具有多个电极端子的所述印刷电路板，使得所述接合垫和电极端子通过所述导电聚合物彼此电和机械连接；和
使用密封剂，模塑具有贴附于其的所述半导体芯片的所述印刷电路板的一个表面。
14.根据权利要求13所述的方法，其中所述掩模由金属或光致抗蚀剂形成。
15.根据权利要求13所述的方法，其中所述导电聚合物形成以具有50-500μm的尺寸。
16.根据权利要求13所述的方法，其中所述导电颗粒被加入到导电聚合物。
17.根据权利要求13所述的方法，其中导电聚合物包括选自由有机磺酸、噻吩、吡咯、噻吩的衍生物、吡咯的衍生物、聚乙烯二氧噻吩、和聚磺苯乙烯组成的组的一种。
18.根据权利要求13所述的方法，其中，在使用所述密封剂模塑所述印刷电路板的一个表面的步骤之后，该方法还包括：
在所述印刷电路板的下表面上形成焊料球。
CN200710149631XA 2007-06-18 2007-09-10 倒装片封装及其制造方法 Expired - Fee Related CN101330069B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070059313A KR100891517B1 (ko) 2007-06-18 2007-06-18 플립 칩 패키지 및 그의 제조방법
KR59313/07 2007-06-18

Publications (2)

Publication Number Publication Date
CN101330069A CN101330069A (zh) 2008-12-24
CN101330069B true CN101330069B (zh) 2010-08-25

Family

ID=40131539

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710149631XA Expired - Fee Related CN101330069B (zh) 2007-06-18 2007-09-10 倒装片封装及其制造方法

Country Status (3)

Country Link
US (2) US20080308949A1 (zh)
KR (1) KR100891517B1 (zh)
CN (1) CN101330069B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829390B2 (en) * 2008-11-20 2010-11-09 Azurewave Technologies, Inc. Packaging structure of SIP and a manufacturing method thereof
KR101046386B1 (ko) * 2009-03-31 2011-07-05 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
DE102012203373A1 (de) * 2012-03-05 2013-09-05 Robert Bosch Gmbh Mikromechanische Schallwandleranordnung und ein entsprechendes Herstellungsverfahren
US9851267B1 (en) * 2016-06-01 2017-12-26 Microsoft Technology Licensing, Llc Force-sensing element
CN111640728B (zh) * 2020-04-21 2022-06-28 江苏长电科技股份有限公司 一种易于sip封装底部填充的转接板及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1520448A (zh) * 2001-06-25 2004-08-11 泰勒弗氏股份有限公司 具有增强粘度的各向异性导电粘合剂及使用它的粘接方法和集成电路封装件
CN1567582A (zh) * 2003-06-18 2005-01-19 财团法人工业技术研究院 覆晶封装接合结构及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US6064120A (en) * 1997-08-21 2000-05-16 Micron Technology, Inc. Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes
US6333104B1 (en) * 2000-05-30 2001-12-25 International Business Machines Corporation Conductive polymer interconnection configurations
KR100398314B1 (ko) * 2001-07-19 2003-09-19 한국과학기술원 고접착력 3층 구조 ａｃａ 필름
US6555924B2 (en) * 2001-08-18 2003-04-29 Siliconware Precision Industries Co., Ltd. Semiconductor package with flash preventing mechanism and fabrication method thereof
AU2003223198A1 (en) * 2002-03-01 2003-09-16 E.I. Du Pont De Nemours And Company Printing of organic conductive polymers containing additives
TW583757B (en) * 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
KR100733208B1 (ko) * 2004-10-11 2007-06-27 삼성전기주식회사 플립칩 실장 기술을 이용한 반도체 패키지
US7344912B1 (en) * 2005-03-01 2008-03-18 Spansion Llc Method for patterning electrically conducting poly(phenyl acetylene) and poly(diphenyl acetylene)
KR20070119790A (ko) * 2006-06-16 2007-12-21 삼성전자주식회사 폴리머 범프를 갖는 적층 패키지, 그의 제조 방법 및 모기판 실장 구조

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1520448A (zh) * 2001-06-25 2004-08-11 泰勒弗氏股份有限公司 具有增强粘度的各向异性导电粘合剂及使用它的粘接方法和集成电路封装件
CN1567582A (zh) * 2003-06-18 2005-01-19 财团法人工业技术研究院 覆晶封装接合结构及其制造方法

Also Published As

Publication number Publication date
KR100891517B1 (ko) 2009-04-06
CN101330069A (zh) 2008-12-24
US20090298229A1 (en) 2009-12-03
KR20080111227A (ko) 2008-12-23
US20080308949A1 (en) 2008-12-18

Similar Documents

Publication Publication Date Title
CN1041254C (zh) 三维结构的半导体器件
JP5661225B2 (ja) 半導体デバイスのパッケージング方法
CN103201836B (zh) 具有面阵单元连接体的可堆叠模塑微电子封装
CN100477194C (zh) 电路板及其制造方法以及半导体封装及其制造方法
KR20080020069A (ko) 반도체 패키지 및 그 제조방법
JP2007123595A (ja) 半導体装置及びその実装構造
JP2002190551A (ja) 配線基板、半導体装置、及び配線基板の製造方法
CN101330069B (zh) 倒装片封装及其制造方法
US20080308951A1 (en) Semiconductor package and fabrication method thereof
CN114639666A (zh) 中介层和包括中介层的半导体封装
CN102543908A (zh) 倒装芯片封装件及其制造方法
US9252112B2 (en) Semiconductor package
KR20170005774A (ko) 인터포저 지지 구조 메커니즘을 갖는 집적 회로 패키징 시스템 및 그 제조 방법
US7498666B2 (en) Stacked integrated circuit
US6806581B2 (en) Bonded anisotropic conductive film
JP2006202997A (ja) 半導体装置およびその製造方法
CN112802816A (zh) 芯片封装结构及其制作方法
US7656021B2 (en) Integrated circuit package system with pedestal structure
CN110211954A (zh) 一种多芯片封装结构及其制造方法
JP5934057B2 (ja) プリント回路基板
CN113299626B (zh) 一种多芯片封装用的导电组件及其制作方法
US20070105270A1 (en) Packaging methods
CN102891118A (zh) 堆叠封装的下封装体构造及其制造方法
CN220254474U (zh) 一种滤波器封装结构、模组及电子产品
KR19980022344A (ko) 적층형 bga 반도체패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100825

Termination date: 20130910