CN113517254A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113517254A
CN113517254A CN202110143214.4A CN202110143214A CN113517254A CN 113517254 A CN113517254 A CN 113517254A CN 202110143214 A CN202110143214 A CN 202110143214A CN 113517254 A CN113517254 A CN 113517254A
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China
Prior art keywords
layer
pattern
conductive
semiconductor device
passivation layer
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Pending
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CN202110143214.4A
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English (en)
Inventor
慎重垣
李瑌真
李仁荣
崔智旻
韩正勳
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020200080050A external-priority patent/KR20210121999A/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN113517254A publication Critical patent/CN113517254A/zh
Pending legal-status Critical Current

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    • H01L2924/1517—Multilayer substrate
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    • H01L2924/1517—Multilayer substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/181—Encapsulation
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material

Abstract

公开了一种半导体装置，所述半导体装置包括：半导体基底；导电垫，位于半导体基底的第一表面上；钝化层，位于半导体基底的第一表面上，钝化层具有暴露导电垫的第一开口；有机介电层，位于钝化层上，有机介电层具有第二开口；以及凸块结构，位于导电垫上并且位于第一开口和第二开口中。有机介电层包括与钝化层的材料不同的材料。第二开口空间地连接到第一开口并且暴露钝化层的部分。凸块结构包括与钝化层和有机介电层接触的柱图案。

Description

半导体装置
本申请要求于2020年3月27日在韩国知识产权局提交的第10-2020-0037698号韩国专利申请和于2020年6月30日在韩国知识产权局提交的第10-2020-0080050号韩国专利申请的优先权，所述韩国专利申请的公开通过引用全部包含于此。
技术领域
本发明构思涉及一种半导体装置，更具体地，涉及一种包括凸块结构的半导体装置。
背景技术
已经迅速开发了半导体装置以增加电极端子的数量并且减小电极端子之间的节距。随之而来，对减小半导体装置的尺寸已经进行了越来越多的研究。半导体装置通常具有用于与其它电子装置或印刷电路板电连接的电连接端子(诸如焊球或凸块)。半导体装置受益于具有高度可靠的连接端子。
发明内容
本发明构思的一些示例实施例提供了一种具有增大的耐久性和可靠性的半导体装置。
根据本发明构思的一些示例实施例，半导体装置可以包括：半导体基底；导电垫，位于半导体基底的第一表面上；钝化层，位于半导体基底的第一表面上，钝化层具有暴露导电垫的部分的第一开口；有机介电层，位于钝化层上，有机介电层具有第二开口；以及凸块结构，位于导电垫上并且位于第一开口和第二开口中。有机介电层可以包括与钝化层的材料不同的材料。第二开口可以空间地连接到第一开口，并且可以暴露钝化层的部分。凸块结构可以包括与钝化层和有机介电层接触的柱图案。
根据本发明构思的一些示例实施例，半导体装置可以包括：半导体基底；导电垫，位于半导体基底的第一表面上；含硅层，位于半导体基底的第一表面上并且暴露导电垫的部分；聚合物层，位于含硅层上并且暴露含硅层的部分和导电垫的部分；柱图案，位于导电垫上并且与含硅层和聚合物层接触；以及焊料图案，位于柱图案上。
根据本发明构思的一些示例实施例，半导体装置可以包括：半导体基底；电路层，位于半导体基底上；导电垫，位于电路层上；含硅层，位于导电垫上，含硅层具有第一开口；聚合物层，位于含硅层上，聚合物层具有第二开口；以及凸块结构，设置在导电垫上。电路层可以包括：集成电路，位于半导体基底的第一表面上；介电层，位于半导体基底的第一表面上，介电层覆盖集成电路；以及互连结构，位于介电层中，互连结构结合到集成电路，互连结构包括布线图案和过孔图案。第一开口可以暴露导电垫的部分和含硅层的内壁。第二开口可以空间地连接到第一开口并且可以暴露含硅层的顶表面。凸块结构可以包括：柱图案，位于第一开口和第二开口中并且与导电垫、含硅层的内壁和暴露的顶表面以及聚合物层的内壁和顶表面接触；以及焊料图案，位于柱图案上。柱图案可以包括：种子图案，与导电垫接触；以及导电图案，位于种子图案上。
附图说明
图1A例示了示出根据一些示例实施例的半导体装置的剖视图。
图1B例示了示出根据一些示例实施例的半导体装置中包括的柱图案的平面图。
图1C例示了沿着图1B的线II-III截取的与图1A的部分I对应的放大剖视图。
图2A例示了示出根据一些示例实施例的半导体装置的凸块结构的剖视图。
图2B例示了示出根据一些示例实施例的半导体装置的凸块结构的剖视图。
图2C例示了示出根据一些示例实施例的半导体装置的钝化层的剖视图。
图2D例示了示出根据一些示例实施例的半导体装置的钝化层的剖视图。
图3例示了示出根据一些示例实施例的半导体封装件的剖视图。
图4A例示了示出根据一些示例实施例的半导体封装件的剖视图。
图4B例示了图4A的部分IV的放大图。
具体实施方式
在本描述中，同样的附图标记可以指示同样的组件。
现在将在下面描述根据本发明构思的半导体装置及制造半导体装置的方法。
图1A例示了示出根据一些示例实施例的半导体装置的剖视图。图1B例示了示出根据一些示例实施例的半导体装置中包括的柱图案的平面图。图1C例示了沿着图1B的线II-III截取的与图1A的部分I对应的放大剖视图。
参照图1A、图1B和图1C，半导体装置100可以包括基底110、电路层120、导电垫(pad，或称为“焊盘”或“焊垫”)130、钝化层140、有机介电层150和凸块结构160。半导体装置100可以是半导体芯片。例如，半导体装置100可以是存储器芯片、逻辑芯片或缓冲器芯片。基底110可以是半导体基底。例如，基底110可以包括半导体材料(诸如硅、锗或硅锗)或者可以由半导体材料(诸如硅、锗或硅锗)形成。基底110可以具有彼此背对的第一表面110a和第二表面110b。
电路层120可以设置在基底110的第一表面110a上。如图1C中所示，电路层120可以包括介电层121、集成电路125和互连结构127。集成电路125可以设置在基底110的第一表面110a上。集成电路125可以包括例如晶体管和/或电连接晶体管的布线。介电层121可以设置在基底110的第一表面110a上，并且可以覆盖集成电路125。尽管为了简洁未示出，但是介电层121可以包括多个堆叠层。介电层121可以包括含硅材料或可以由含硅材料形成。例如，介电层121可以是绝缘体层，或者可以包括在竖直方向上堆叠的多个绝缘体层。例如，介电层121可以包括氧化硅、氮化硅、氮氧化硅和/或原硅酸四乙酯，或者可以由氧化硅、氮化硅、氮氧化硅和/或原硅酸四乙酯形成。互连结构127可以设置在介电层121中。互连结构127可以电连接到集成电路125。在本描述中，当元件被描述为电连接到半导体装置时，元件可以电连接到半导体装置的集成电路，使得信号可以在元件与集成电路中的一个或更多个之间传递。当两个组件被描述为彼此电连接/结合时，两个组件可以彼此直接连接/结合(例如，使得它们物理接触并且也连接以在彼此之间传递电信号)，或者两个组件可以通过其它导电组件彼此间接连接/结合(例如，使得它们彼此不物理接触，但是它们仍然连接以在彼此之间传递电信号)。互连结构127可以包括布线图案和连接到布线图案的过孔图案。布线图案和过孔图案可以是多个布线图案和过孔图案的部分。每个布线图案可以在与基底110的第一表面110a平行的方向上延伸。例如，布线图案可以具有沿着布线图案纵向延伸并且在与第一表面110a平行的方向上延伸的长轴。布线图案可以包括置于包括在介电层121中的层(例如，绝缘体层)之间的多个布线图案。过孔图案可以均具有轴对称性，并且轴对称性的对称轴可以与基底110的第一表面110a相交。例如，过孔图案的对称轴可以与基底110的第一表面110a垂直。过孔图案可以设置在包括在介电层121中的层(例如，绝缘体层)中的至少一个中。例如，介电层121可以包括堆叠在一起的多个子层(例如，绝缘体层)，过孔图案可以穿透子层中的一个。多个过孔图案可以被包括在不同的相应子层处。每个过孔图案可以设置在多个布线图案之间并且结合到多个布线图案。每个布线图案可以具有比对应的过孔图案的宽度小的宽度。在这种情况下，对应的过孔图案可以直接连接到一个或更多个对应的布线图案。互连结构127可以包括金属(诸如铝或铜)。
导电垫130可以设置在基底110的第一表面110a上/之上。在本描述中，当某个组件被描述为在另一组件上时，所述某个组件可以直接形成在所述另一组件上，或者第三组件可以置于所述某个组件与所述另一组件之间。例如，导电垫130可以设置在电路层120上。导电垫130可以通过互连结构127电连接到集成电路125。导电垫130可以是芯片垫。例如，芯片垫可以是导体垫，在该导体垫上涂覆了焊球或另一焊料材料或者在该导体垫上在芯片垫与其中集成有电路和/或半导体装置的半导体基底之间没有涂覆其它焊球或材料。导电垫130可以包括金属(诸如铝)或者可以由金属(诸如铝)形成。尽管未示出，但是垫种子层还可以置于导电垫130与电路层120之间。垫种子层可以用于形成导电垫130。导电垫130可以包括边缘部和中央部。当在平面图中观看时，导电垫130的边缘部可以围绕导电垫130的中央部。导电垫130的边缘部可以包括导电垫130的侧壁以及与侧壁相邻的部分。
钝化层140可以设置在基底110的第一表面110a上。钝化层140可以覆盖电路层120。钝化层140可以包括第一钝化层141和第二钝化层142。第一钝化层141可以设置在电路层120上，并且可以覆盖介电层121的顶表面，并且也可以覆盖导电垫130的侧壁和边缘部。第一钝化层141可以包括含硅介电材料。第一钝化层141可以包括例如氧化硅和/或原硅酸四乙酯。第一钝化层141可以不包括氮。第二钝化层142可以设置在第一钝化层141上。第二钝化层142可以具有介电特性。第二钝化层142可以是含硅层。第二钝化层142可以包括与第一钝化层141的材料不同的材料。例如，第二钝化层142可以包括与第一钝化层141的含硅介电材料不同的含硅介电材料或可以由与第一钝化层141的含硅介电材料不同的含硅介电材料形成。例如，第一钝化层141和第二钝化层142两者可以包括彼此不同的含硅介电材料。第二钝化层142可以包括硅和氮。第二钝化层142可以包括例如氮化硅、氮氧化硅、碳氮化硅和/或碳氮氧化硅。钝化层140可以具有第一开口149，第一开口149可以暴露导电垫130的顶表面。第一开口149可以穿透第一钝化层141和第二钝化层142。第一开口149可以暴露第一钝化层141的内壁141c和第二钝化层142的内壁142c。例如，第一钝化层141的内壁141c可以是第一开口149的形成在第一钝化层141中的侧壁的一部分，第二钝化层142的内壁142c可以是第一开口149的形成在第二钝化层142中的侧壁的另一部分。第二钝化层142的内壁142c可以与第一钝化层141的内壁141c共面。例如，共同地形成第一开口149的侧壁的内壁141c和142c可以例如在剖视图中线性连接，并且可以具有基本上线性的斜率。例如，第一钝化层141的内壁141c的顶端和第二钝化层142的内壁142c的底端可以彼此接触，内壁141c和142c可以具有相对于基底110的第一表面110a的基本上相同的倾斜角。第一开口149可以具有比导电垫130的宽度小的宽度W1。例如，第一开口149的宽度W1可以等于或大于约5μm且小于约10μm。宽度W1可以是第一开口149的下部分的宽度/直径或者第一开口149的底表面/底端的宽度/直径。第一开口149的底表面可以与导电垫130的暴露的顶表面对应。例如，钝化层140可以暴露导电垫130的中央部处的顶表面。如图1B中所示，例如，当在平面图中观看时，第一开口149可以具有圆形形状。例如，第一开口149可以具有截圆锥形状，并且可以具有圆形顶端和圆形底端。例如，第一开口149的圆形顶端可以具有比第一开口149的圆形底端的直径大的直径。
当涉及方位、布局、位置、形状、尺寸、量或其它测量时，如在此所使用的诸如“相同”、“相等”、“平面”或“共面”的术语不一定表示完全相同的方位、布局、位置、形状、尺寸、量或其它测量，而是旨在涵盖在例如由于制造工艺可能发生的可接受变化内的几乎相同的方位、布局、位置、形状、尺寸、量或其它测量。除非上下文或其它陈述另有指示，否则术语“基本上”可以在此用于强调该含义。例如，描述为“基本上相同”、“基本上相等”或“基本上平面”的项可以是完全相同、完全相等或完全平面，或者可以是在例如由于制造工艺而可能发生的可接受变化内的相同、相等或平面。
诸如“约”或“近似”的术语可以反映仅以小的相对方式和/或以不显著改变某些元件的操作、功能或结构的方式变化的量、尺寸、方位或布局。例如，从“约0.1至约1”的范围可以涵盖诸如在0.1周围的0％-5％偏差和在1周围的0％至5％偏差(特别地，如果这种偏差保持与所列范围的效果相同的效果)的范围。
有机介电层150可以设置在钝化层140的顶表面上。例如，有机介电层150可以覆盖第二钝化层142的顶表面。除非在本描述中另有陈述，否则在钝化层140由第一钝化层141和第二钝化层142组成的情况下，钝化层140的顶表面可以表示第二钝化层142的顶表面。有机介电层150可以具有第二开口159。有机介电层150可以具有彼此背对的顶表面150a和底表面，第二开口159可以穿透有机介电层150的顶表面150a和底表面。例如，第二开口159可以穿透包括顶表面150a和底表面的有机介电层150。当在平面图中观看时，第二开口159可以与第一开口149叠置。第二开口159可以空间地连接到第一开口149。如图1B中所示，当在平面图中观看时，第二开口159可以具有圆形形状。例如，第二开口159可以具有截圆锥形状，并且可以具有圆形顶端和圆形底端。例如，第二开口159的圆形顶端可以具有比第二开口159的圆形底端的直径大的直径。第二开口159可以具有比第一开口149的直径大的直径。例如，第二开口159的圆形底端的直径可以比第一开口149的圆形顶端的直径大。第二开口159的宽度W2可以比第一开口149的宽度W1大。例如，第二开口159的宽度W2可以等于或大于约10μm并且小于约20μm。宽度W2可以是有机介电层150的下部分的宽度/直径或第二开口159的底表面/底端的宽度/直径。有机介电层150的底表面可以接触钝化层140。第二开口159可以暴露钝化层140的顶表面的部分和有机介电层150的内壁150c。例如，有机介电层150的内壁150c可以是第二开口159的侧壁。有机介电层150的内壁150c可以与第二钝化层142的内壁142c不对准。例如，如图1C中所示，由内壁150c在剖视图中形成的线可以不在由内壁142c在剖视图中形成的相同线上。例如，如图1C中所示，内壁150c和内壁142c可以不竖直叠置。钝化层140可以具有由其内壁和暴露的顶表面形成的台阶结构，有机介电层150也可以具有由其内壁150c和顶表面150a形成的台阶结构。例如，由第一开口149和第二开口159共同形成的开口可以具有台阶侧壁，所述台阶侧壁具有由内壁141c、142c及150c形成的倾斜部分以及由钝化层140的暴露的顶表面形成的平坦部分。有机介电层150可以是聚合物层。有机介电层150可以包括例如聚酰亚胺。聚酰亚胺可以包括光敏聚酰亚胺。
将理解的是，当元件被称为“连接”到或“结合”到另一元件或“在”另一元件“上”时，所述元件可以直接连接到或直接结合到所述另一元件或直接在所述另一元件上，或者可以存在中间元件。相反，当元件被称为“直接连接”到或“直接结合”到另一元件，或者被称为“接触”另一元件或“与”另一元件“接触”时，不存在中间元件。用于描述元件之间的关系的其它词语应该以类似的方式解释(例如，“在……之间”与“直接在……之间”、“相邻”与“直接相邻”等)。例如，除非上下文另有指示，否则如在此所使用的术语“接触”指直接连接(即，触摸)。
凸块结构160可以设置在导电垫130的顶表面上并且结合到导电垫130。例如，凸块结构可以接触导电垫130。凸块结构160可以包括柱图案161和焊料图案165。例如，焊料图案165可以是焊球。柱图案161可以设置在导电垫130的顶表面上并且在第一开口149和第二开口159中。柱图案161可以填充第一开口149和第二开口159。如图1B中所示，例如，当在平面图中观看时，柱图案161可以具有圆形形状。例如，柱图案161的顶表面可以具有圆形形状。柱图案161可以具有比第二开口159的直径大的直径。例如，柱图案161的顶表面可以具有比第二开口159的顶部分的直径大的直径。柱图案161可以具有比第二开口159的宽度W2大的宽度W3。例如，柱图案161的宽度W3可以等于或大于20μm并且可以等于或小于约70μm。宽度W3可以是柱图案161的上部分的宽度/直径。例如，宽度W3可以是在柱图案161的顶表面161a处的宽度/直径。柱图案161可以具有设置在有机介电层150的顶表面150a的部分上的侧壁，柱图案161的设置在有机介电层150的顶表面150a上的侧壁可以与有机介电层150的顶表面150a基本上垂直。因此，柱图案161可以在比有机介电层150的顶表面150a的水平高的水平范围内具有基本上均匀的宽度/直径。例如，柱图案161的设置在比有机介电层150的顶表面150a的水平高的水平处的部分可以具有圆柱形形状。由于柱图案161的宽度W3比第二开口159的宽度W2大，因此柱图案161可以覆盖有机介电层150的顶表面150a的部分。例如，本公开中的宽度W1、W2和W3可以是柱图案161在与基底110的第一表面110a平行的水平方向上测量的宽度/直径。
柱图案161的顶表面161a可以是基本上平坦的。当在本描述中将某个表面描述为平坦时，该表面可以包括在制造的工艺中可能发生的误差，并且可以排除台阶差、突起或凹陷的有意形成。柱图案161的顶表面161a可以与基底110的第一表面110a平行。柱图案161可以具有与顶表面161a背对的底表面161b。例如，柱图案161的底表面161b可以面对和/或接触形成在柱图案161下方(例如，导电垫130、钝化层140和/或有机介电层150)的顶表面。柱图案161的底表面161b可以具有由钝化层140和有机介电层150引起的台阶差。例如，柱图案161的底表面161b可以包括第一底表面161x、第二底表面161y和第三底表面161z。柱图案161的第一底表面161x可以与有机介电层150的顶表面150a接触。柱图案161的第二底表面161y可以定位在比第一底表面161x的水平低的水平处。柱图案161的第二底表面161y可以与钝化层140的顶表面接触。柱图案161的第三底表面161z可以定位在比第二底表面161y的水平低的水平处。柱图案161的第三底表面161z可以与导电垫130接触。在本描述中，语言“水平”可以指示竖直水平，术语“竖直”可以对应于与基底110的第一表面110a垂直的方向。可以在与基底110的第一表面110a垂直的方向上测量两个表面之间的水平的差。
第二钝化层142可以用作粘合层，该粘合层例如用于将柱图案161附着到下结构(钝化层/介电层/基底)。在柱图案161与第二钝化层142接触时，柱图案161可以稳定地附着到介电层121和第一钝化层141。例如，柱图案161与第二钝化层142之间的粘合力可以比柱图案161与介电层121之间的粘合力大。柱图案161与第二钝化层142之间的粘合力可以比柱图案161与第一钝化层141之间的粘合力大。
有机介电层150可以具有比第二钝化层142的柔软度大的柔软度。有机介电层150可以具有相对低的硬度。例如，有机介电层150可以具有比第二钝化层142的硬度低的硬度。因此，有机介电层150可以减轻施加到凸块结构160的应力。应力可以是物理应力。例如，应力可以是在例如再分布基底、封装基底或电路板上的安装工艺中施加到凸块结构160的压力。柱图案161与有机介电层150之间的接触面积可以比柱图案161与第二钝化层142之间的接触面积大，这可以有益于减小施加到凸块结构160的应力。因此，可以防止/保护柱图案161在将半导体装置100安装在例如再分布基底、封装基底或电路板上期间被损坏。柱图案161与有机介电层150之间的接触面积可以包括柱图案161与有机介电层150的内壁150c之间的接触面积以及柱图案161与有机介电层150的顶表面150a之间的接触面积。柱图案161与第二钝化层142之间的接触面积可以包括柱图案161与第二钝化层142的内壁142c之间的接触面积以及柱图案161与第二钝化层142的顶表面之间的接触面积。
柱图案161可以包括种子图案162和导电图案163。种子图案162可以设置在导电垫130的顶表面上，并且可以延伸到钝化层140和有机介电层150上。种子图案162可以共形地覆盖导电垫130的暴露的顶表面、钝化层140的内壁和顶表面以及有机介电层150的内壁150c和顶表面150a的部分。种子图案162可以与导电垫130的暴露的顶表面、钝化层140的内壁和顶表面以及有机介电层150的内壁150c和顶表面150a物理接触。除非在本描述中另有陈述，否则钝化层140的内壁可以包括第一钝化层141的内壁141c和第二钝化层142的内壁142c。除非上下文另有指示，否则如在此所使用的术语“物理接触”指类似于如上所述的“接触”的直接连接(即，触摸)。种子图案162可以包括例如从钛和铜中选择的至少一种。柱图案161的底表面161b可以指示种子图案162的底表面。导电图案163可以形成在种子图案162上。导电图案163可以包括金属(诸如铜、镍或其合金)。导电图案163可以通过其中种子图案162用作电极的电镀工艺形成。种子图案162可以暴露导电图案163的上侧壁163c。导电图案163的上侧壁163c可以定位在比有机介电层150的顶表面150a的水平高的水平处。柱图案161的顶表面161a可以指示导电图案163的顶表面。
焊料图案165可以设置在柱图案161的顶表面161a上并且电连接到柱图案161。焊料图案165可以包括与柱图案161的材料不同的材料。例如，焊料图案165可以包括锡(Sn)、银(Ag)、锌(Zn)、铅(Pb)或其合金。
为了在除了图1C、图2A至图2D和图4B之外的图中简洁地示出柱图案161，在种子图案162与导电图案163之间将不进行区分。然而，不旨在将种子图案162和/或导电图案163排除在实施例之外。此外，除了图1C、图2A至图2D和图4B之外的图省略了介电层121、集成电路125和互连结构127的图示，但是并不旨在从本发明构思中排除介电层121、集成电路125和互连结构127中的任何一个。附图中这些特征的省略仅仅是为了图示的简洁，在本申请中公开的并且与附图兼容的任何特征可以应用于附图。类似地，可以跨越本公开的实施例应用和/或互换其它兼容和/或可互换的特征。
图2A例示了沿着图1B的线II-III截取并且与图1A的部分I对应的放大剖视图，该剖视图示出了根据一些示例实施例的半导体装置的凸块结构。以下将参照图1A和图1B以及图2A，并且将进行省略以避免重复的描述。
参照图2A，半导体装置可以包括基底110、电路层120、导电垫130、钝化层140、有机介电层150、种子图案162、导电图案163和焊料图案165。种子图案162、导电图案163和焊料图案165可以与上面参照图1A至图1C讨论的种子图案162、导电图案163和焊料图案165基本上相同。然而，导电图案163可以由如图2A中所示的多层形成，这与图1C中所示的实施例的导电图案163的不同之处在于图1C的导电图案163是单层。例如，导电图案163可以包括竖直堆叠的导电层，导电层包括第一导电部/层1631、第二导电部/层1632和第三导电部/层1633。第一导电部1631可以与导电图案163的下部分对应。第一导电部1631可以覆盖种子图案162。第一导电部1631可以设置在第一开口149和第二开口159中，并且可以设置在有机介电层150的顶表面150a的部分上。第一导电部1631可以具有在比有机介电层150的顶表面150a的水平高的水平处的顶表面。第一导电部1631的顶表面可以是基本上平坦的。第一导电部1631可以包括第一金属或者可以由第一金属形成。第一金属可以是例如铜、镍、钨、铝等。
第二导电部1632可以设置在第一导电部1631上。第二导电部1632可以与种子图案162间隔开。例如，如图2A中所示，第一导电部/层1631可以置于种子图案162与第二导电部/层1632之间的所有区域中，并且可以填充种子图案162与第二导电部/层1632之间的间隙。第二导电部1632可以包括与第一金属不同的第二金属或者可以由与第一金属不同的第二金属形成。第二金属可以是例如镍、铜、钨、铝等。第二导电部1632可以具有基本上平坦的顶表面。
第三导电部1633可以设置在第二导电部1632上。第二导电部1632可以置于第一导电部1631与第三导电部1633之间。例如，如图2A中所示，第二导电部/层1632可以置于第一导电部/层1631与第三导电部/层1633之间的所有区域中，并且可以填充第一导电部/层1631与第三导电部/层1633之间的间隙。第三导电部1633可以包括第一金属或者可以由第一金属形成。例如，第三导电部1633可以包括与第一导电部1631的金属相同的金属。根据一些示例实施例，由于导电图案163包括第一导电部1631、第二导电部1632和第三导电部1633，因此对调节导电图案163的特性可以是有益的。
图2B例示了沿着图1B的线II-III截取并且与图1A的部分I对应的放大剖视图，该放大剖视图示出了根据一些示例实施例的半导体装置的凸块结构。以下将参照图1A和图1B以及图2B，并且将进行省略以避免重复的描述。
参照图2B，半导体装置可以包括基底110、电路层120、导电垫130、钝化层140、有机介电层150、包含种子图案162和导电图案163的柱图案161以及焊料图案165。柱图案161和焊料图案165可以与上面在图1A至图1C中讨论的柱图案161和焊料图案165基本上相同。然而，在图2B中所示的实施例中，种子图案162可以延伸到导电图案163的上侧壁163c上并且覆盖导电图案163的上侧壁163c。种子图案162可以具有在与导电图案163的顶表面的水平基本上相同的水平处的最上面的表面。可选地，导电图案163可以包括如图2A中所讨论的第一导电部1631、第二导电部1632和第三导电部1633。
在图2A和图2B的实施例中，基底110、电路层120、有机介电层150可以与上面在图1A至图1C中讨论的基底110、电路层120、有机介电层150基本上相同。
图2C例示了沿着图1B的线II-III截取并且与图1A的部分I对应的放大剖视图，该放大剖视图示出了根据一些示例实施例的半导体装置的钝化层。以下将参照图1A和图1B以及图2C，并且将进行省略以避免重复的描述。
参照图2C，半导体装置可以包括基底110、电路层120、导电垫130、钝化层140、有机介电层150和凸块结构160。钝化层140可以由单层形成。例如，钝化层140可以包括第二钝化层142，但是可以不包括图1C中讨论的第一钝化层141。第二钝化层142可以与电路层120的顶表面和有机介电层150的底表面物理接触。第二钝化层142可以与导电垫130接触。例如，第二钝化层142可以在导电垫130的边缘部处与导电垫130的侧壁物理接触并且与顶表面物理接触。导电垫130可以设置在第二钝化层142中。如上面所讨论的，第二钝化层142可以是含硅层。第二钝化层142可以包括硅和氮。第二钝化层142可以包括例如氮化硅、氮氧化硅、碳氮化硅和/或碳氮氧化硅。根据一些示例实施例，柱图案161和第二钝化层142可以具有在柱图案161和第二钝化层142之间增大的接触面积，使得柱图案161可以稳定地附着到导电垫130/介电层121/半导体装置100。例如，第一开口149和第二开口159的倾斜的侧壁、钝化层140的暴露的顶表面、柱图案161的在有机介电层150的顶表面150a的部分上的接触件和/或层和图案的相应材料可以有益于凸块结构160可靠附着在导电垫130上并且可靠附着到半导体装置100。
图2D例示了沿着图1B的线II-III截取并且与图1A的部分I对应的放大剖视图，该放大剖视图示出了根据一些示例实施例的半导体装置的钝化层。以下将参照图1A和图1B以及图2D，并且将进行省略以避免重复的描述。
参照图2D，半导体装置可以包括基底110、电路层120、导电垫130、第一钝化层141、第二钝化层142、有机介电层150和凸块结构160。第一钝化层141和第二钝化层142可以类似于上面参照图1A至图1C讨论的第一钝化层141和第二钝化层142。然而，在图2D中所示的实施例中，第二钝化层142可以设置在第一钝化层141的顶表面上，并且可以覆盖第一钝化层141的内壁141c。第二钝化层142可以与导电垫130的顶表面的部分接触。第一开口149可以暴露第二钝化层142的内壁142c，但是可以不暴露第一钝化层141。
柱图案161可以设置在第一开口149和第二开口159中，并且可以与第二钝化层142的内壁142c接触且与有机介电层150的内壁150c和顶表面150a接触。在第二钝化层142延伸到第一钝化层141的内壁141c上时，柱图案161和第二钝化层142可以具有在柱图案161和第二钝化层142之间增大的接触面积。因此，第二钝化层142可以有助于柱图案161稳定地固定到第一钝化层141。例如，第一钝化层141和第二钝化层142以及柱图案可以分别由这样的材料制成，使得第二钝化层142与柱图案161之间的粘附力可以比第一钝化层141与柱图案161之间的粘附力强，第一钝化层141与第二钝化层142之间的粘附力可以比第一钝化层141与柱图案161之间的粘附力强。柱图案161可以例如由于第二钝化层142置于柱图案161和第一钝化层141的内壁141c之间而与第一钝化层141的内壁141c间隔开。
在图2C和图2D的实施例中，基底110、电路层120、有机介电层150和凸块结构160可以与上面参照图1A至图1C讨论的基底110、电路层120、有机介电层150和凸块结构160基本上相同。可选地，凸块结构160可以与参照图2A或图2B讨论的凸块结构160基本上相同。
以下将描述包括根据本发明构思的半导体装置的半导体封装件。为了简洁起见，下面将省略重复的描述。
图3例示了示出根据一些示例实施例的半导体封装件的剖视图。
参照图3，半导体封装件1可以包括封装基底900、半导体装置100和成型层200。封装基底900可以具有彼此背对的顶表面和底表面。封装基底900可以包括介电基体层910、基底垫920和内部线930。介电基体层910可以包括单层或多个层。基底垫920可以在封装基底900的顶表面上被暴露。内部线930可以设置在介电基体层910中并且结合到基底垫920。介电基体层910中的实线被示意性地示出以指示内部线930。在本描述中，当元件被描述为电连接到封装基底900时，元件可以电连接到内部线930。这可以类似地应用于其它元件。基底垫920和内部线930可以包括金属(诸如铜、铝、钨和/或钛)。例如，封装基底900可以是具有电路图案的印刷电路板(PCB)。在某些实施例中，再分布层可以用作封装基底900。当再分布基底用作封装基底900时，介电基体层910可以包括光敏聚合物。当再分布基底用作封装基底900时，内部线930可以包括种子层和种子层上的金属层。例如，种子层可以是有助于金属的成核现象以形成金属层的层。
外部端子950可以设置在封装基底900的底表面上并且结合到内部线930。外部电信号可以通过外部端子950传输到内部线930。外部端子950可以包括焊球。外部端子950可以包括诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属或可以由诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属形成。
半导体装置100可以安装在封装基底900上。半导体装置100可以设置在封装基底900上以使半导体装置100的凸块结构160面对封装基底900。凸块结构160可以与基底垫920对准。凸块结构160可以与基底垫920接触。将半导体装置100安装在封装基底900上的步骤可以包括对凸块结构160执行接合工艺。接合工艺可以是焊接工艺。例如，焊接工艺可以包括对凸块结构160执行退火工艺。可以在比焊料图案165的熔点高的温度下执行退火工艺。在该步骤中，凸块结构160还可以被供应有外力(诸如压力)。在柱图案161与有机介电层150接触时，有机介电层150可以减轻在接合工艺中施加到柱图案161的应力。因此，在焊接工艺期间，可以防止/保护柱图案161被损坏。焊料图案165可以在接合工艺期间接合到基底垫920，因此半导体装置100的集成电路可以通过凸块结构160电连接到封装基底900。
成型层200可以设置在封装基底900的顶表面上。成型层200可以覆盖半导体装置100的顶表面和侧壁(例如，每个侧壁)。在某些实施例中，成型层200可以覆盖半导体装置100的侧壁，但是可以暴露半导体装置100的顶表面。成型层200可以延伸到封装基底900与半导体装置100之间的间隙中，从而封装凸块结构160。可选地，底部填充层(未示出)可以设置在封装基底900与半导体装置100之间。成型层200可以包括介电聚合物(诸如环氧类模塑料)。
图4A例示了示出根据一些示例实施例的半导体封装件的剖视图。图4B例示了示出图4A的部分IV的放大图。为了简洁起见，下面将省略重复的描述。
参照图4A和图4B，半导体封装件1A可以包括封装基底900、中介层基底800和芯片堆叠件1000。封装基底900可以与参照图3所讨论的封装基底900基本上相同。多个外部端子950可以设置在封装基底900的底表面上。
中介层基底800可以设置在封装基底900上。中介层基底800可以包括金属垫820和金属线830。金属垫820可以在中介层基底800的顶表面上被暴露。金属线830可以设置在中介层基底800中并且结合到金属垫820。在本描述中，当元件被描述为电连接到中介层基底800时，该元件可以电连接到金属线830。金属垫820和金属线830可以包括诸如铜、铝、钨和/或钛的金属。中介凸块850可以置于封装基底900与中介层基底800之间并且结合到封装基底900和中介层基底800。例如，中介凸块850可以结合到基底垫920和金属线830。中介凸块850可以是焊球或者另一焊料结构(例如，焊柱)。中介凸块850可以包括诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属或者可以由诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属形成。
芯片堆叠件1000可以安装在中介层基底800的顶表面上。芯片堆叠件1000可以包括第一半导体芯片300和多个半导体装置100。第一半导体芯片300可以安装在中介层基底800的顶表面上。第一半导体芯片300可以是逻辑芯片、缓冲器芯片和片上系统中的一个。例如，第一半导体芯片300的集成电路(未示出)可以包括逻辑电路，第一半导体芯片300可以用作逻辑芯片。例如，逻辑芯片可以是中央处理单元(CPU)、图形处理单元(GPU)或另一处理器。第一半导体芯片300可以包括基体基底310、电路图案330、导电贯穿电极380和上导电垫370。基体基底310可以是半导体基底。电路图案330可以在其中具有集成电路。上导电垫370可以设置在第一半导体芯片300的顶表面上。导电贯穿电极380可以设置在基体基底310中并且结合到上导电垫370。第一接合凸块350可以置于中介层基底800与第一半导体芯片300之间并且电连接到中介层基底800和第一半导体芯片300。在本描述中，短语“电连接到半导体芯片”可以表示“电连接到半导体芯片的集成电路”。例如，第一接合凸块350可以电连接到第一半导体芯片300的集成电路。第一接合凸块350可以包括从焊球和焊柱中选择的至少一种。第一接合凸块350可以包括诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属或可以由诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属形成。多个第一接合凸块350可以设置在中介层基底800与第一半导体芯片300之间，第一接合凸块350中的至少一个可以电连接到导电贯穿电极380。
半导体装置100可以堆叠在第一半导体芯片300上。半导体装置100可以各自是与第一半导体芯片300的类型不同的类型。例如，半导体装置100可以是存储器芯片。存储器芯片可以包括高带宽存储器(HBM)芯片。每个半导体装置100可以包括基底110、电路层120、导电垫130、钝化层140、有机介电层150和凸块结构160。基底110、电路层120、导电垫130、钝化层140、有机介电层150和凸块结构160可以与参照图1A至图1C讨论的基底110、电路层120、导电垫130、钝化层140、有机介电层150和凸块结构160基本上相同。可选地，凸块结构160可以与参照图2A或图2B所论述的凸块结构160基本上相同，和/或钝化层140可以与参照图2C或图2D所论述的钝化层140基本上相同。
每个半导体装置100还可以包括贯穿电极180和上垫170。上垫170可以设置在半导体装置100的顶表面上。贯穿电极180可以设置在基底110中。贯穿电极180的顶端可以结合到上垫170。如图4B中所示，贯穿电极180的底端可以通过互连结构127结合到从导电垫130和集成电路125中选择的至少一个。因此，上垫170可以通过贯穿电极180结合到从导电垫130和集成电路125中选择的至少一个。最上面的半导体装置100可以既不包括贯穿电极180也不包括上垫170。
半导体装置100可以包括彼此相邻的下半导体装置100和上半导体装置100。上半导体装置100可以设置在下半导体装置100的顶表面上。上半导体装置100的凸块结构160可以结合到下半导体装置100的上垫170。因此，多个半导体装置100可以彼此电连接。最下面的半导体装置100的凸块结构160可以结合到第一半导体芯片300的上导电垫370。因此，半导体装置100可以电连接到封装基底900。
如图4A中所示，每个半导体装置100可以包括多个凸块结构160，细节距P1可以设置在多个凸块结构160之间。例如，置于中介层基底800与封装基底900之间的中介凸块850可以具有如图4A中所示的节距P2，凸块结构160的节距P1可以比中介凸块850的节距P2小并且比外部端子950的节距P3小。一些组件的节距可以是一些组件重复设置的周期。
半导体封装件1A还可以包括第二半导体芯片400。第二半导体芯片400可以安装在中介层基底800的顶表面上。第二半导体芯片400可以与第一半导体芯片300横向间隔开。第二半导体芯片400可以具有与第一半导体芯片300的类型和半导体装置100的类型不同的类型。第二半导体芯片400可以包括中央处理单元(CPU)或图形处理单元(GPU)。如图4A中所示，第二接合凸块450可以设置在第二半导体芯片400的芯片垫430与多个金属垫820之中的形成在中介层基底800的顶表面上的对应金属垫820之间。第二接合凸块450可以包括从焊球和焊柱中选择的至少一种。第二接合凸块450可以包括诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属或者可以由诸如焊料材料(例如，锡、铜、银、铋、铟、锌、锑、铅等)的金属形成。多个第二接合凸块450可以设置在第二半导体芯片400与中介层基底800之间，相应的第二接合凸块450可以接触形成在第二半导体芯片400的底表面上的对应的芯片垫430，并且可以接触形成在中介层基底800的顶表面上的对应的金属垫820。多个第二接合凸块450可以具有比外部端子950的节距P3小的节距。第二半导体芯片400可以通过第二接合凸块450和中介层基底800的金属线830电连接到第一半导体芯片300或半导体装置100。例如，第二半导体芯片400可以通过第二接合凸块450和金属线830电连接到第一半导体芯片300和/或一个或更多个半导体装置100。
半导体封装件1A还可以包括从第一底部填充图案710、第二底部填充图案720和第三底部填充图案730中选择的至少一个。第一底部填充图案710可以设置在中介层基底800与第一半导体芯片300之间的间隙中，并且可以封装第一接合凸块350。第一底部填充图案710可以包括介电聚合物(诸如环氧类聚合物)。多个第二底部填充图案720可以设置在半导体装置100之间的间隙中，并且可以封装对应的凸块结构160。第二底部填充图案720可以包括介电聚合物(诸如环氧类聚合物)。第三底部填充图案730可以设置在中介层基底800与第二半导体芯片400之间的间隙中，并且可以封装第二接合凸块450。第三底部填充图案730可以包括介电聚合物(诸如环氧类聚合物)。
半导体封装件1A还可以包括成型层(未示出)。成型层可以设置在中介层基底800的顶表面上，并且可以覆盖芯片堆叠件1000和第二半导体芯片400。
根据本发明构思，凸块结构可以与钝化层和有机介电层物理接触。在凸块结构与有机介电层接触时，有机介电层可以减轻施加到凸块结构的应力。在凸块结构与钝化层接触时，凸块结构可以稳定地固定到电路层。因此，凸块结构和包括该凸块结构的半导体装置可以具有增大的可靠性和耐久性。
虽然已经参照示例实施例描述了发明构思，但是对于本领域技术人员来说将清楚的是，在不脱离发明构思的精神和范围的情况下，可以进行各种改变和修改。因此，应该理解的是，上面的实施例不是限制性的，而是说明性的。因此，发明的范围将由权利要求及其等同物的最宽泛解释来确定，并且不应受前述描述的约束或限制。

Claims (20)

1.一种半导体装置，所述半导体装置包括：
半导体基底；
导电垫，位于半导体基底的第一表面上；
钝化层，位于半导体基底的第一表面上，钝化层具有暴露导电垫的部分的第一开口；
有机介电层，位于钝化层上，有机介电层具有第二开口；以及
凸块结构，位于导电垫上并且位于第一开口和第二开口中，
其中，有机介电层包括与钝化层的材料不同的材料，
其中，第二开口空间地连接到第一开口并且暴露钝化层的部分，并且
其中，凸块结构包括与钝化层和有机介电层接触的柱图案。
2.根据权利要求1所述的半导体装置，其中，凸块结构还包括位于柱图案上的焊料图案。
3.根据权利要求1所述的半导体装置，其中，柱图案接触导电垫并且延伸到有机介电层的顶表面上。
4.根据权利要求1所述的半导体装置，其中，
柱图案的宽度比第二开口的宽度大，并且
第二开口的宽度比第一开口的宽度大。
5.根据权利要求4所述的半导体装置，其中，
柱图案的宽度等于或大于20μm并且等于或小于70μm，
第二开口的宽度等于或大于10μm并且小于20μm，并且
第一开口的宽度等于或大于5μm并且小于10μm。
6.根据权利要求1所述的半导体装置，其中，柱图案的顶表面是平坦的。
7.根据权利要求1所述的半导体装置，其中，柱图案包括种子图案和位于种子图案上的导电图案。
8.根据权利要求7所述的半导体装置，其中，导电图案包括导电层，导电层包括：
第一导电层，位于种子图案上；
第二导电层，位于第一导电层上；以及
第三导电层，位于第二导电层上。
9.根据权利要求8所述的半导体装置，其中，第一导电层的顶表面位于比有机介电层的顶表面的水平高的水平处。
10.根据权利要求8所述的半导体装置，其中，
第三导电层包括与第一导电层的材料相同的材料，并且
第二导电层包括与第一导电层的材料不同并且与第三导电层的材料不同的材料。
11.根据权利要求1所述的半导体装置，其中，钝化层包括含硅层。
12.根据权利要求1所述的半导体装置，其中，钝化层包括：
第一钝化层；以及
第二钝化层，位于第一钝化层上并且包括与第一钝化层的材料不同的材料，
其中，第二钝化层的内壁与第一钝化层的内壁共面并且与柱图案接触。
13.一种半导体装置，所述半导体装置包括：
半导体基底；
导电垫，位于半导体基底的第一表面上；
含硅层，位于半导体基底的第一表面上并且暴露导电垫的部分；
聚合物层，位于含硅层上并且暴露含硅层的部分和导电垫的部分；
柱图案，位于导电垫上并且与含硅层和聚合物层接触；以及
焊料图案，位于柱图案上。
14.根据权利要求13所述的半导体装置，其中，
聚合物层暴露含硅层的顶表面，并且
柱图案与含硅层的暴露的顶表面和聚合物层的顶表面接触。
15.根据权利要求13所述的半导体装置，其中，柱图案与含硅层的内壁和聚合物层的内壁接触，
其中，聚合物层的内壁与含硅层的内壁不对准。
16.根据权利要求13所述的半导体装置，其中，柱图案包括种子图案和位于种子图案上的导电图案，
其中，种子图案覆盖导电垫的暴露的顶表面、含硅层的内壁和顶表面以及聚合物层的内壁和顶表面。
17.根据权利要求13所述的半导体装置，其中，柱图案与聚合物层之间的接触面积比柱图案与含硅层之间的接触面积大。
18.根据权利要求13所述的半导体装置，其中，
含硅层包括硅和氮，并且
聚合物层包括光敏聚酰亚胺。
19.一种半导体装置，所述半导体装置包括：
半导体基底；
电路层，位于半导体基底上；
导电垫，位于电路层上；
含硅层，位于导电垫上，含硅层具有第一开口；
聚合物层，位于含硅层上，聚合物层具有第二开口；以及
凸块结构，设置在导电垫上，
其中，电路层包括：集成电路，位于半导体基底的第一表面上；介电层，位于半导体基底的第一表面上，介电层覆盖集成电路；以及互连结构，位于介电层中，互连结构结合到集成电路，互连结构包括布线图案和过孔图案，
其中，第一开口暴露导电垫的部分和含硅层的内壁，
其中，第二开口空间地连接到第一开口并且暴露含硅层的顶表面，并且
其中，凸块结构包括：柱图案，位于第一开口和第二开口中并且与导电垫、含硅层的内壁和暴露的顶表面以及聚合物层的内壁和顶表面接触；以及焊料图案，位于柱图案上，
其中，柱图案包括：种子图案，与导电垫接触；以及导电图案，位于种子图案上。
20.根据权利要求19所述的半导体装置，其中，导电图案包括：
第一导电部，位于种子图案上，第一导电部包括第一金属；
第二导电部，位于第一导电部上，第二导电部包括第二金属；以及
第三导电部，位于第二导电部上，第三导电部包括第一金属，
其中，第二金属与第一金属不同。
CN202110143214.4A 2020-03-27 2021-02-02 半导体装置 Pending CN113517254A (zh)

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