CN113937068A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

Info

Publication number
CN113937068A
CN113937068A CN202110405250.3A CN202110405250A CN113937068A CN 113937068 A CN113937068 A CN 113937068A CN 202110405250 A CN202110405250 A CN 202110405250A CN 113937068 A CN113937068 A CN 113937068A
Authority
CN
China
Prior art keywords
package substrate
substrate
package
adhesive layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110405250.3A
Other languages
English (en)
Inventor
金泳龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN113937068A publication Critical patent/CN113937068A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

公开一种半导体封装件，其包括：封装基板；基板，所述基板位于所述封装基板上；第一半导体芯片，所述第一半导体芯片安装在所述基板上；和加强件结构，所述加强件结构位于所述封装基板上并且具有孔。所述加强件结构与所述基板横向间隔开。所述孔穿透所述加强件结构的顶表面和所述加强件结构的底表面。当在俯视图中观察时，所述孔与所述封装基板的拐角区域交叠。

Description

半导体封装件
相关申请的交叉引用
本申请要求于2020年7月13日在韩国知识产权局提交的韩国专利申请No.10-2020-0086265的优先权，其公开内容通过引用整体合并于此。
技术领域
本发明构思涉及半导体封装件，更具体地，涉及包括加强件(stiffener)结构的半导体封装件。
背景技术
提供半导体封装件来实现用于电子产品的集成电路芯片。通常，半导体封装件被配置为使得半导体芯片安装在印刷电路板(PCB)上，并且接合线或凸块被用于将半导体芯片电连接到印刷电路板。随着电子工业的发展，已经进行了各种研究来改善半导体封装件的可靠性和耐久性。
发明内容
本发明构思的一些示例实施例提供了具有提高的可靠性的半导体封装件。
根据本发明构思的一些示例实施例，半导体封装件可以包括：封装基板；基板，所述基板位于所述封装基板上；第一半导体芯片，所述第一半导体芯片安装在所述基板上；和加强件结构，所述加强件结构位于所述封装基板上，所述加强件结构具有孔。所述加强件结构可以与所述基板横向间隔开。所述孔可以穿透所述加强件结构的顶表面和所述加强件结构的底表面。当在俯视图中观察时，所述孔可以与所述封装基板的拐角区域交叠。
根据本发明构思的一些示例实施例，半导体封装件可以包括：封装基板，当在俯视图中观察时，所述封装基板具有第一区域和包围所述第一区域的第二区域；第一半导体芯片，所述第一半导体芯片位于所述封装基板的所述第一区域上；加强件结构，所述加强件结构位于所述封装基板的所述第二区域上，所述加强件结构具有孔；和粘合层，所述粘合层位于所述封装基板与所述加强件结构之间。所述孔可以穿透所述加强件结构的顶表面和所述加强件结构的底表面。所述粘合层可以延伸到所述加强件结构的所述孔中。
根据本发明构思的一些示例实施例，半导体封装件可以包括：封装基板，所述封装基板具有中央区域、第一边缘区域和第二边缘区域；中介基板，所述中介基板位于所述封装基板的所述中心区域的顶表面上；多个中介凸块，所述多个中介凸块位于所述封装基板与所述中介基板之间；底部填充层，所述底部填充层位于所述封装基板与所述中介基板之间的间隙中，所述底部填充层包封所述中介凸块；第一半导体芯片，所述第一半导体芯片安装在所述中介基板的顶表面上；多个第一凸块，所述多个第一凸块位于所述中介基板与所述第一半导体芯片之间；芯片堆叠，所述芯片堆叠安装在所述中介基板的所述顶表面上，并且与所述第一半导体芯片间隔开，所述芯片堆叠包括多个堆叠的第二半导体芯片；多个第二凸块，所述多个第二凸块位于所述第二半导体芯片之间；加强件结构，所述加强件结构位于所述封装基板的所述第一边缘区域的顶表面和所述第二边缘区域的顶表面上，所述加强件结构具有孔；和粘合层，所述粘合层位于所述封装基板与所述加强件结构的底表面之间。所述孔可以穿透所述加强件结构的顶表面和所述加强件结构的底表面。所述孔可以位于所述封装基板的所述第一边缘区域上。所述封装基板的所述第一边缘区域可以与所述封装基板的两个相邻的侧表面彼此汇合处的拐角相邻。
附图说明
图1A示出了显示根据示例实施例的半导体封装件的俯视图。
图1B示出了沿着图1A的线I-I'截取的截面图。
图1C示出了显示图1B的部分A的放大图。
图1D示出了沿着图1A的线II-II'截取的截面图。
图2A示出了显示根据示例实施例的粘合层和加强件结构的截面图。
图2B示出了显示根据示例实施例的粘合层和加强件结构的截面图。
图3A示出了显示根据示例实施例的在半导体封装件中包括的加强件结构的孔的俯视图。
图3B示出了显示根据示例实施例的在半导体封装件中包括的加强件结构的孔的俯视图。
图4A示出了显示根据示例实施例的半导体封装件的俯视图。
图4B示出了沿着图4A的线I-I'截取的截面图。
图4C示出了沿着图4A的线II-II'截取的截面图。
图5示出了显示根据示例实施例的制造半导体封装件的方法的截面图。
具体实施方式
在本说明书中，相同的附图标记指示相同的组件。现在将在下面描述根据本发明构思的半导体封装件及其制造方法。
图1A示出了显示根据示例实施例的半导体封装件的俯视图。图1B示出了沿着图1A的线I-I'截取的截面图。图1C示出了显示图1B的部分A的放大图。图1D示出了沿着图1A的线II-II'截取的截面图。
参照图1A、图1B、图1C和图1D，半导体封装件可以包括封装基板100、第一半导体芯片310、加强件结构(stiffener structure)500和粘合层600。半导体封装件还可以包括选自外部端子150、中介基板(interposer substrate)200、中介凸块(interposer bump)250、底部填充层240、第二半导体芯片320、第三半导体芯片330和模制层400中的至少一种。
当在如图1A所示的俯视图中观察时，封装基板100可以包括第一区域R1和第二区域R2。第一区域R1可以是封装基板100的中央区域。第二区域R2可以是封装基板100的边缘区域。第二区域R2可以与第一区域R1间隔开。当在俯视图中观察时，第二区域R2可以包围第一区域R1。第二区域R2可以介于第一区域R1与封装基板100的侧表面100c之间。第二区域R2可以包括第一边缘区域ER1和第二边缘区域ER2。第一边缘区域ER1可以对应于封装基板100的拐角区域。例如，每个第一边缘区域ER1可以与封装基板100的两个相邻侧表面100c彼此汇合的拐角100z相邻。封装基板100的每个第二边缘区域ER2可以设置在两个第一边缘区域ER1之间并且与封装基板100的一个侧表面100c相邻。
如图1B和图1D所示，封装基板100可以包括电介质基体层110、基板焊盘120和内部线130。电介质基体层110可以包括多个堆叠的层。或者，电介质基体层110可以是单个层。基板焊盘120可以暴露在封装基板100的顶表面上。例如，基板焊盘120的顶表面可以与封装基板100的顶表面共面。内部线130可以设置在电介质基体层110中，并且结合到基板焊盘120。短语“两个组件彼此电连接/结合”可以包括两个组件彼此直接连接/结合，或通过不同的导电组件间接连接/结合。在本说明书中，短语“电连接/结合到封装基板100”可以表示“电连接/结合到内部线130”的含义。基板焊盘120和内部线130可以包括金属，例如铜、铝、钨和钛中的一种或更多种。例如，封装基板100可以是具有电路图案的印刷电路板(PCB)。又例如，再分布层可以用作封装基板100。
外部端子150可以设置在封装基板100的底表面上，并且结合到内部线130。外部电信号可以通过外部端子150传输到内部线130。外部端子150可以包括焊料球。外部端子150可以包括金属，例如焊料材料。焊料材料可以包括锡(Sn)、银(Ag)、锌(Zn)或它们的任何合金。
基板可以设置在封装基板100的第一区域R1上。基板可以是中介基板200。中介基板200可以包括金属焊盘220和金属线230。金属焊盘220可以暴露在中介基板200的顶表面上。例如，金属焊盘220的顶表面可以与中介基板200的顶表面共面。金属线230可以设置在中介基板200中，并且结合到金属焊盘220。在本说明书中，短语“电连接/结合到中介基板200”可以表示“电连接/结合到金属线230”的含义。金属焊盘220和金属线230可以包括金属，例如铜、铝、钨和钛中的一种或更多种。
当涉及到方向、布局、位置、形状、尺寸、量或其他度量时，如本文所使用的诸如“相同”、“相等”、“平面”或“共面”的术语不一定表示完全相同的方向、布局、位置、形状、尺寸、量或其他度量，而是旨在包含在例如由于制造工艺而可能发生的可接受的变化内的几乎相同的方向、布局、位置、形状、尺寸、量或其他度量。除非上下文或其他陈述另有指示，否则在本文中可以使用术语“基本上”来强调这种含义。例如，被描述为“基本上相同”、“基本上相等”或“基本上平面”的项可以完全相同、相等或平面，或者可以在例如由于制造工艺而可能发生的可接受的变化内的相同、相等或平面。
中介凸块250可以介于封装基板100与中介基板200之间，并且结合到封装基板100和中介基板200。例如，中介凸块250可以结合到基板焊盘120和金属线230。在示例实施例中，中介凸块250可以直接接触(即，触及)基板焊盘120的顶表面。中介凸块250可以包括焊料球、凸块和柱中的一种或更多种。中介凸块250可以包括金属，例如焊料材料。底部填充层240可以设置在封装基板100的第一区域R1上。底部填充层240可以设置在封装基板100与中介基板200之间的间隙中，从而包封中介凸块250。底部填充层240可以包括介电聚合物，例如环氧基聚合物。
第一半导体芯片310可以设置在封装基板100的第一区域Rl的顶表面上。在本说明书中，短语“某个组件位于其他组件上”可以表示“某个组件直接在形成其他组件上”或“第三组件介于某个组件与其他组件之间”。例如，中介基板200可以介于封装基板100与第一半导体芯片310之间。第一半导体芯片310可以设置在中介基板200的顶表面上。第一半导体芯片310可以包括逻辑芯片、缓冲芯片或片上系统(SOC)。第一半导体芯片310可以是例如专用集成电路(ASIC)芯片或应用处理器(AP)芯片。ASIC芯片可以包括专用集成电路(ASIC)。第一半导体芯片310可以包括中央处理单元(CPU)或图形处理单元(GPU)。
第一凸块315可以介于中介基板200与第一半导体芯片310之间，并且电连接中介基板200和第一半导体芯片310。在本说明书中，短语“电连接到半导体芯片”可以表示“电连接到半导体芯片中的集成电路”。例如，第一凸块315可以结合到第一半导体芯片310的芯片焊盘311并且结合到相应的金属焊盘220。在示例实施例中，第一凸块315可以接触芯片焊盘311的底表面和相应的金属焊盘220的顶表面。第一凸块315可以包括导电材料，例如焊料材料。第一凸块315可以设置为多个。第一凸块315的节距P1可以小于多个中介凸块250的节距P20。第一凸块315的节距P1可以小于多个外部端子150的节距P10。多个中介凸块250的节距P20可以小于多个外部端子150的节距P10。
第一底部填充图案410可以设置在中介基板200与第一半导体芯片310之间的第一间隙中，从而包封第一凸块315。第一底部填充图案410可以包括介电聚合物，例如环氧基聚合物。
第二半导体芯片320可以设置在封装基板100的第一区域Rl的顶表面上。例如，第二半导体芯片320可以设置在中介基板200的顶表面上。第二半导体芯片320可以设置为多个，并且多个第二半导体芯片320可以堆叠在中介基板200的顶表面上。第二半导体芯片320的类型可以不同于第一半导体芯片310的类型。第二半导体芯片320可以是存储芯片。存储芯片可以包括高带宽存储(HBM)芯片。第二半导体芯片320可以包括动态随机存储(DRAM)芯片。
每个第二半导体芯片320可以包括集成电路(未示出)、芯片连接焊盘326和贯穿结构327。集成电路可以设置在第二半导体芯片320中。贯穿结构327可以穿透相应的第二半导体芯片320，并且可以与集成电路电连接。相反，最上面的第二半导体芯片320可以不包括贯穿结构327。
第三半导体芯片330可以介于中介基板200与最下面的第二半导体芯片320之间。第三半导体芯片330的类型可以不同于第一半导体芯片310和第二半导体芯片320的类型。例如，第三半导体芯片330可以是逻辑芯片，并且可以具有与第一半导体芯片310的功能不同的功能。第三半导体芯片330可以具有与第二半导体芯片320的宽度不同的宽度，但是本发明构思不限于此。第三半导体芯片330可以包括集成电路(未示出)、导电芯片焊盘336和通路337。集成电路可以设置在第三半导体芯片330中。通路337可以穿透第三半导体芯片330，并且可以与第三半导体芯片330的集成电路电连接。第二半导体芯片320和第三半导体芯片330可以构成芯片堆叠。与所示的不同，可以省略第三半导体芯片330。
多个第二凸块325可以介于两个相邻的第二半导体芯片320之间。第二凸块325可以与相应的第二半导体芯片320的贯穿结构327和/或集成电路电连接。第二半导体芯片320可以通过第二凸块325彼此电连接。第二凸块325还可以介于第三半导体芯片330与最下面的第二半导体芯片320之间。第二半导体芯片320可以通过第二凸块325电连接到第三半导体芯片330。第二凸块325可以包括导电材料，例如焊料材料。第二凸块325的节距P2可以小于中介凸块250的节距P20。第二凸块325的节距P2可以小于外部端子150的节距P10。多个第二底部填充图案420可以设置在第二半导体芯片320之间的第二间隙中以及第三半导体芯片330与最下面的第二半导体芯片320之间的第三间隙中。每个第二底部填充图案420可以包封相应的第二凸块325。第二底部填充图案420可以包括介电聚合物，例如环氧基聚合物。
第三凸块335可以介于中介基板200与第三半导体芯片330之间，并且可以电连接中介基板200和第三半导体芯片330。第三凸块335可以包括导电材料，例如焊料材料。因此，第二半导体芯片320和第三半导体芯片330可以通过第三凸块335和金属线230电连接到第一半导体芯片310或外部端子150。第三底部填充图案430可以设置在中介基板200与第三半导体芯片330之间的第四间隙中，从而包封第三凸块335。第三底部填充图案430可以包括介电聚合物，例如环氧基聚合物。
模制层400可以设置在封装基板100上，从而覆盖第一半导体芯片310的侧壁、第二半导体芯片320的侧壁和第三半导体芯片330的侧壁。模制层400可以暴露第一半导体芯片310的顶表面和最上面的第二半导体芯片320的顶表面。或者，模制层400还可以覆盖第一半导体芯片310的顶表面和最上面的第二半导体芯片320的顶表面。模制层400可以包括介电聚合物，例如环氧基聚合物。
半导体封装件还可以包括散热板700。散热板700可以设置在选自第一半导体芯片310的顶表面和最上面的第二半导体芯片320的顶表面中的至少一者上。散热板700还可以覆盖模制层400的顶表面。散热板700可以延伸到模制层400的侧壁上。散热板700可以包括散热块(heat slug)或散热器(heat sink)。散热板700可以包括具有高热导率的材料，例如金属。
加强件结构500可以设置在封装基板100的第二区域R2上。加强件结构500可以不设置在封装基板100的第一区域R1上。加强件结构500可以设置为与中介基板200、底部填充层240、第一半导体芯片310、第二半导体芯片320、第三半导体芯片330和模制层400横向间隔开。加强件结构500可以具有彼此相对的内侧壁500c和外侧壁500d。加强件结构500的内侧壁500c可以朝向中介基板200，并且与中介基板200间隔开。加强件结构500可以包括金属。例如，加强件结构500可以包括铜、不锈钢(SUS)、铝碳化硅(AlSiC)和钛中的一种或更多种。
加强件结构500可以具有相对大的刚度。杨氏模量可以用来估计某种材料的刚度。加强件结构500可以具有例如大约100GPa至大约300GPa的杨氏模量。组件之间的热膨胀系数的差异可能导致半导体封装件的翘曲。由于加强件结构500具有相对大的刚度，所以加强件结构500可以固定封装基板100的第二区域R2。因此，可以防止封装基板100翘曲。当加强件结构500的杨氏模量小于大约100GPa时，可能难以充分防止封装基板100的翘曲。
在封装基板100的第一区域R1上，可能发生中介凸块250与封装基板100之间的热膨胀系数差异。根据一些示例实施例，加强件结构500可以设置在封装基板100的第二区域R2上。加强件结构500的热膨胀系数可以不同于封装基板100的热膨胀系数。例如，加强件结构500的热膨胀系数可以大于封装基板100的热膨胀系数。因此，封装基板100的第一区域R1上的封装基板100与中介凸块250之间的热膨胀系数差异可以与封装基板100的第二区域R2上的封装基板100与加强件结构500之间的热膨胀系数差异抵消。因此，可以防止封装基板100或中介基板200pa的翘曲。
根据一些示例实施例，加强件结构500可以具有孔590。孔590可以穿透加强件结构500的顶表面500a和底表面500b。加强件结构500的底表面500b可以面向封装基板100。顶表面500a可以与加强件结构500的底表面500b相对。孔590可以设置在加强件结构500的内侧壁500c与外侧壁500d之间。
当加强件结构500不具有孔590时，加强件结构500可能在半导体封装件的运行期间将应力施加到封装基板100。应力可能由于加强件结构500的高刚度而发生。应力可能集中在封装基板100的第一边缘区域ER1上。当半导体封装件重复地运行时，应力可能在封装基板100与底部填充层240之间产生裂纹。裂纹可以朝向中介凸块250传播。在这种情况下，封装基板100与选自第一半导体芯片310、第二半导体芯片320和第三半导体芯片330中的至少一者之间的电连接会不良。加强件结构500与封装基板100之间的交叠面积的增加可能引起应力诱发的裂纹的发生的增加。根据一些示例实施例，由于加强件结构500具有孔590，因此可以在加强件结构500与封装基板100之间提供减小的交叠面积。当在俯视图中观察时，交叠面积可以指加强件结构500的底表面500b与封装基板100交叠的面积。因此，可以减小施加到封装基板100的应力，并且可以增加半导体封装件的可靠性。
根据一些示例实施例，孔590可以设置在封装基板100的一个第一边缘区域ER1上。例如，加强件结构500可以具有多个孔590，并且多个孔590可以与封装基板100的相应的第一边缘区域ER1交叠。在封装基板100的每个第一边缘区域ER1上，可以在加强件结构500与封装基板100之间提供减小的交叠面积。通过减小交叠面积，可以减小施加到封装基板100的第一边缘区域ER1的应力，并且可以有效地减小或避免在封装基板100与底部填充层240之间出现裂纹。因此，可以提高半导体封装件的可靠性。以下描述将集中在单个孔590上。
粘合层600可以设置在封装基板100的第二区域R2上。粘合层600可以介于封装基板100的顶表面与加强件结构500的底表面500b之间。粘合层600可以将加强件结构500固定到封装基板100。如图1C所示，粘合层600可以部分地暴露加强件结构500的底表面500b。例如，粘合层600可以接触加强件结构500的底表面500b的一部分。或者，粘合层600可以完全覆盖加强件结构500的底表面500b。粘合层600可以设置在加强件结构500的孔590中。例如，粘合层600可以延伸到孔590的侧壁590c上，以与孔590的侧壁590c接触。粘合层600可以填充孔590的至少一部分。例如，粘合层600可以填充孔590的下部。粘合层600可以具有位于比加强件结构500的顶表面500a低的水平高度处的最上表面600a。粘合层600的最上表面600a可以位于比加强件结构500的底表面500b高的水平高度处。
粘合层600可以是相对柔性的。例如，粘合层600可以比加强件结构500柔性。粘合层600可以具有相对低的刚度。例如，粘合层600的刚度可以低于加强件结构500的刚度。粘合层600的杨氏模量可以是加强件结构500的杨氏模量的大约1/3000至大约1/10。例如，粘合层600可以具有大约0.01GPa至大约1GPa的杨氏模量。由于粘合层600具有低刚度并且延伸到孔590中，所以施加到封装基板100的应力可以减小。因此，半导体封装件的可靠性可以提高。
如图1A和图1B所示，粘合层600可以不设置在封装基板100的第一区域R1上。粘合层600可以与底部填充层240和中介基板200间隔开，并且可以包围底部填充层240和中介基板200。粘合层600可以包括与底部填充层240的材料不同的材料。粘合层600可以包括与第一底部填充图案410、第二底部填充图案420和第三底部填充图案430的材料不同的材料。因此，粘合层600可以具有与底部填充层240的刚度不同的刚度。如图1C所示，粘合层600可以包括基体层601，并且基体层601可以包括有机硅类(silicone-based)介电材料。有机硅类介电材料可以包括例如有机硅类聚合物或有机硅类橡胶。粘合层600还可以包括填料602。填料602可以设置在基体层601中。例如，填料602可以分布在基体层601中。由于粘合层600还包括填料602，所以粘合层600的机械强度可以提高。例如，填料602的机械强度可以大于基体层601的机械强度。填料602可以包括与基体层601的材料不同的材料。填料602可以包括无机材料。例如，填料602可以包括氧化硅(SiOx)或氧化铝(AlOx)，其中x是正实数。
当孔590的宽度W2小于加强件结构500的宽度W1的大约50％时，在封装基板100与底部填充层240之间可能出现应力诱发的裂纹。当孔590的宽度W2大于加强件结构500的宽度W1的大约95％时，加强件结构500的机械稳定性会降低。根据一些示例实施例，孔590的宽度W2可以是加强件结构500的宽度W1的大约50％至大约95％。因此，可以减少裂纹的出现，并且可以确保加强件结构500的稳定性。可以在加强件结构500的底表面500b处测量孔590的宽度W2和加强件结构500的宽度W1。加强件结构500的宽度W1可以对应于加强件结构500的内侧壁500c和外侧壁500d之间的间隔。可以在与加强件结构500的相应宽度W1所测量的方向相同的方向上测量孔590的宽度W2。
加强件结构500可以具有大约0.2mm至大约3.0mm的高度H。加强件结构500的高度H可以指加强件结构500的顶表面500a与底表面500b之间的间隔。当加强件结构500的高度H小于大约0.2mm时，加强件结构500可能不足以防止封装基板100的翘曲。当加强件结构500的高度H大于大约3.0mm时，可能难以制造半导体封装件并且难以实现半导体封装件的紧凑性。
与所示出的不同，可以省略选自中介基板200、中介凸块250、底部填充层240、第一半导体芯片310、第二半导体芯片320、第三半导体芯片330、第一底部填充图案410、第二底部填充图案420、第三底部填充图案430、模制层400、第一凸块315、第二凸块325和第三凸块335中的至少一者。例如，可以省略中介基板200、中介凸块250和底部填充层240，并且第一半导体芯片310和第三半导体芯片330可以直接安装在封装基板100上。例如，当第一半导体芯片310直接安装在封装基板100上时，第一凸块315可以直接结合到相应的基板焊盘120。当第三半导体芯片330直接安装在封装基板100上时，第三凸块335可以直接结合到相应的基板焊盘120。
作为另一示例，可以省略中介基板200、中介凸块250、底部填充层240以及第二半导体芯片320和第三半导体芯片330，并且第一半导体芯片310可以直接安装在封装基板100上。作为另一示例，可以省略第一半导体芯片310、第一凸块315和第一底部填充图案410。作为另一示例，可以省略第一半导体芯片310和中介基板200，并且第三半导体芯片330可以直接安装在封装基板100上。作为另一示例，可以省略散热板700。第一半导体芯片310和第二半导体芯片320的芯片堆叠的数目可以不同地改变。
下面将描述根据一些示例实施例的粘合层和加强件结构。下面将省略上面讨论的重复描述。
图2A示出了在图1B中描绘的部分A的放大截面图，示出了根据一些示例实施例的粘合层和加强件结构。图2B示出了在图1B中描绘的部分A的放大截面图，示出了根据一些示例实施例的粘合层和加强件结构。在说明图2A和图2B时还将参照图1A、图1B和图1D。
参照图2A和图2B，半导体封装件可以包括加强件结构500和粘合层600。加强件结构500和粘合层600可以与上面参照图1A至图1D讨论的基本上相同。例如，加强件结构500可以具有孔590，孔590穿透加强件结构500的顶表面500a和底表面500b。粘合层600可以延伸到加强件结构500的孔590中，并且可以接触孔590的侧壁590c。粘合层600的高度和形状可以不同地改变。
如图2A所示，粘合层600可以填充孔590的上部和下部。粘合层600的最上表面600a可以位于与加强件结构500的顶表面500a的水平高度基本上相同的水平高度处。例如，粘合层600的最上表面600a可以与加强件结构500的顶表面500a共面。粘合层600可以完全覆盖加强件结构500的底表面500b，但是本发明构思不限于此。
如图2B所示，粘合层600可以填充加强件结构500的孔590，并且可以延伸到加强件结构500的顶表面500a上。粘合层600还可以覆盖加强件结构500的顶表面500a的至少一部分。例如，粘合层600可以接触加强件结构500的顶表面500a的至少一部分。粘合层600的最上表面600a可以位于比加强件结构500的顶表面500a的水平高度高的水平高度处。粘合层600可以覆盖加强件结构500的底表面500b。粘合层600还可以覆盖外侧壁500d的下部和内侧壁500c的下部。
在除了图1C、图2A和图2B之外的图中，为了方便绘制，未示出基体层601和填料602。然而，这些图示不排除基体层601或填料602。
下面将描述加强件结构的孔。
图3A示出了显示根据一些示例实施例的在半导体封装件中包括的加强件结构的孔的俯视图。图3B示出了显示根据一些示例实施例的在半导体封装件中包括的加强件结构的孔的俯视图。在说明图3A和图3B时还将参照图1B至图1D。
参照图3A和图3B，加强件结构500可以具有孔590。孔590可以具有与图1B至图1D的实施例中讨论的截面基本上相同的截面。例如，孔590可以穿透加强件结构500。相反，孔590可以设置在封装基板100的第一边缘区域ER1和第二边缘区域ER2上。
如图3A所示，加强件结构500可以具有单个孔590。当在俯视图中观察时，孔590可以包括第一孔部分591和第二孔部分592。第一孔部分591可以平行于第一方向D1。第一孔部分591可以在第二方向D2上彼此间隔开。第一方向D1可以平行于封装基板100的顶表面。第二方向D2可以平行于封装基板100的顶表面，并且可以与第一方向D1相交。第二孔部分592可以平行于第二方向D2。第二孔部分592可以在第一方向D1上彼此间隔开。第二孔部分592可以在空间上连接到相应的第一孔部分591。孔590可以是第一孔部分591连接到第二孔部分592的单个孔。孔590可以具有例如封闭的多边形形状。
参照图3B，加强件结构500可以具有多个孔590。孔590可以彼此间隔开。每个孔590可以具有圆形形状。然而，孔590的形状可以不同地改变。例如，每个孔590可以具有四边形、六边形、八边形或任何合适的多边形。孔590的存在可以减轻施加到封装基板100的第一边缘区域ER1和第二边缘区域ER2的应力。
图4A示出了显示根据一些示例实施例的半导体封装件的俯视图。图4B示出了沿着图4A的线I-I'截取的截面图。图4C示出了沿着图4A的线II-II'截取的截面图。下面将省略上面讨论的重复描述。
参照图4A至图4C，半导体封装件可以包括封装基板100、第一半导体芯片310、加强件结构500和粘合层600。半导体封装件还可以包括选自外部端子150、中介基板200、中介凸块250、底部填充层240、第二半导体芯片320、第三半导体芯片330、第一凸块315、第二凸块325、第三凸块335、第一底部填充图案410、第二底部填充图案420、第三底部填充图案430、模制层400和散热板700中的至少一种。
加强件结构500可以设置在封装基板100的第一边缘区域ER1和第二边缘区域ER2上。加强件结构500可以具有孔590。当在俯视图中观察时，孔590可以设置封装基板100的相应的第一边缘区域ER1上。
粘合层600可以介于封装基板100与加强件结构500之间。粘合层600可以包括第一粘合层610和第二粘合层620。当在如图4A所示的俯视图中观察时，第一粘合层610可以与封装基板100的相应的第一边缘区域ER1交叠。当在俯视图中观察时，第一粘合层610可以与相应的孔590交叠。如图4B所示，每个第一粘合层610可以延伸到相应的孔590中。每个第一粘合层610可以覆盖相应的孔590的侧壁590c。如图4B所示，第一粘合层610可以填充孔590的下部。第一粘合层610的最上表面可以位于比加强件结构500的顶表面500a的水平高度低的水平高度处。或者，如在图2A所示的粘合层600的示例中所讨论的，第一粘合层610的最上表面可以位于与加强件结构500的顶表面500a的水平高度相同的水平高度处。或者，如在图2B所示的粘合层600的示例中所讨论的，第一粘合层610可以覆盖加强件结构500的顶表面500a。
每个第一粘合层610可以包括与在图1A至图1D所示的粘合层600的示例中所讨论的材料基本上相同的材料。例如，每个第一粘合层610可以包括如图1C所示的基体层601，并且基体层601可以包括有机硅类聚合物或有机硅类橡胶。每个第一粘合层610还可以包括填料602，并且填料602可以包括诸如氧化硅或氧化铝的无机材料。
如图4A和图4C所示，第二粘合层620可以与封装基板100的相应的第二边缘区域ER2交叠。每个第二粘合层620可以设置在第一粘合层610之间。第二粘合层620可以具有比第一粘合层610的粘合力大的粘合力。因此，第二粘合层620可以将加强件结构500稳定地固定到封装基板100。第二粘合层620可以具有与第一粘合层610的材料不同的材料。第二粘合层620可以包括例如环氧基聚合物。
当从加强件结构500省略孔590时，并且当省略粘合层600时，应力可能集中在封装基板100的第一边缘区域ER1上。第二粘合层620可以不设置在封装基板100的第一边缘区域ER1上。粘合层600可以与加强件结构500的孔590间隔开。第一粘合层610可以具有低的刚度和小的杨氏模量。第一粘合层610的杨氏模量可以小于第二粘合层620的杨氏模量。例如，第一粘合层610的杨氏模量可以为加强件结构500的杨氏模量的大约1/3000至大约1/100。例如，第一粘合层610可以具有大约0.01GPa至大约1GPa的杨氏模量。由于第一粘合层610延伸到封装基板100的第一边缘区域ER1上的孔590中，所以可以减小施加到封装基板100的第一边缘区域ER1上的应力，并且可以有效地减小或避免在封装基板100与底部填充层240之间产生裂纹。因此，半导体封装件的可靠性可以提高。
封装基板100、第一半导体芯片310、第二半导体芯片320、第三半导体芯片330、外部端子150、中介基板200、底部填充层240、第一凸块315、第二凸块325、第三凸块335、第一底部填充图案410、第二底部填充图案420、第三底部填充图案430、模制层400和散热板700可以与上面在图1A至图1D的实施例中讨论的基本上相同。
图5示出了沿着图1A的线I-I'截取的截面图，示出了根据一些示例实施例的制造半导体封装件的方法。下面将省略上面讨论的重复描述。
参照图5，可以准备初始封装件1000。初始封装件1000可以包括中介基板200、中介凸块250、第一半导体芯片310、第二半导体芯片320和第三半导体芯片330。中介凸块250可以设置在中介基板200的底表面上。初始封装件1000还可以包括第一凸块315、第二凸块325、第三凸块335、第一底部填充图案410、第二底部填充图案420、第三底部填充图案430、模制层400和散热板700。
可以将初始封装件1000安装在封装基板100上。初始封装件1000的安装可以包括将初始封装件1000布设在封装基板100的第一区域Rl上以及将中介凸块250结合到基板焊盘120。之后，可以在封装基板100与中介基板200之间形成底部填充层240，从而包封中介凸块250。
可以在封装基板100的第二区域R2上形成初始粘合层600P。初始粘合层600P的形成可以通过粘合材料的滴涂工艺来执行。初始粘合层600P可以不涂覆在封装基板100的第一区域R1上。在形成初始粘合层600P之后可以形成底部填充层240。
可以准备具有孔590的加强件结构500。可以将加强件结构500设置在封装基板100的第二区域R2的顶表面上，以使加强件结构500的底表面500b面向初始粘合层600P。在这种情况下，加强件结构500的孔590可以与初始粘合层600P竖直交叠。
参照图5和图1B，加强件结构500可以下降以使其底表面500b接触初始粘合层600P。可以将诸如压力的物理力施加到加强件结构500。加强件结构500可以压缩初始粘合层600P。初始粘合层600P可以与加强件结构500的底表面500b接触，并且初始粘合层600P的至少一部分可以被引入到孔590中，从而形成粘合层600。粘合层600可以覆盖孔590的侧壁590c，并且可以接触加强件结构500的底表面500b的至少一部分和封装基板100的顶表面。粘合层600可以将加强件结构500固定到封装基板100的第二区域R2的顶表面上。因此，可以最终制造如图1A至图1D所示的半导体封装件。
可以根据设置的初始粘合层600P的体积、加强件结构500的高度和孔590的宽度来不同地改变加强件结构500与粘合层600之间的布置关系。例如，加强件结构500和粘合层600可以与在图2A或图2B的实施例中讨论的基本上相同。
图1A至图1D的实施例、图2A的实施例、图3A的实施例和图3B的实施例可以彼此组合。例如，当孔590具有如在图3A或图3B的实施例中讨论的平面形状时，孔590中可以设置有如在图1C、图2A或图2B的实施例中所讨论的那样设置的粘合层600。
根据本发明构思，加强件结构可以设置在封装基板的边缘区域上，因此可以减少或避免封装基板的翘曲。由于加强件结构具有孔，所以可以减小加强件结构与封装基板之间的交叠面积。因此，可以减小施加到封装基板的应力。粘合层可以设置在孔中并且可以具有低的刚度。因此，可以进一步减小施加到封装基板的应力。结果，半导体封装件的可靠性可以提高。
本发明构思的这种详细描述不应当被解释为限于本文阐述的实施例，而是意图是，在不脱离本发明构思的精神和范围的情况下，本发明构思覆盖本发明的各种组合、修改和变化。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
封装基板；
基板，所述基板位于所述封装基板上；
第一半导体芯片，所述第一半导体芯片安装在所述基板上；和
加强件结构，所述加强件结构位于所述封装基板上，所述加强件结构具有孔，
其中，所述加强件结构与所述基板横向间隔开，
其中，所述孔穿透所述加强件结构的顶表面和所述加强件结构的底表面，并且
其中，当在俯视图中观察时，所述孔与所述封装基板的拐角区域交叠。
2.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
粘合层，所述粘合层位于所述封装基板与所述加强件结构之间，
其中，所述粘合层延伸到所述加强件结构的所述孔中，并且覆盖所述孔的侧壁的至少一部分。
3.根据权利要求2所述的半导体封装件，其中，所述粘合层的刚度小于所述加强件结构的刚度。
4.根据权利要求3所述的半导体封装件，其中，所述粘合层的杨氏模量是所述加强件结构的杨氏模量的1/3000至1/100。
5.根据权利要求4所述的半导体封装件，
其中，所述粘合层的杨氏模量在0.01GPa至1GPa的范围内，并且
其中，所述加强件结构的杨氏模量在100GPa至300GPa的范围内。
6.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
多个第二半导体芯片，所述多个第二半导体芯片堆叠在所述基板上，
其中，所述第一半导体芯片的类型不同于所述第二半导体芯片的类型。
7.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
粘合层，所述粘合层位于所述封装基板与所述加强件结构之间，
其中，所述粘合层包括基体层，并且
其中，所述基体层包括有机硅类聚合物或有机硅类橡胶。
8.根据权利要求7所述的半导体封装件，
其中，所述粘合层还包括在所述基体层中的填料，
其中，所述填料包括与所述基体层的材料不同的材料。
9.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
多个中介凸块，所述多个中介凸块介于所述封装基板与所述基板之间，并且电连接到所述封装基板和所述基板；
底部填充层，所述底部填充层位于所述封装基板与所述基板之间的间隙中，所述底部填充层包封所述中介凸块；和
粘合层，所述粘合层位于所述封装基板与所述加强件结构之间，
其中，所述粘合层与所述底部填充层间隔开，并且包括与所述底部填充层的材料不同的材料。
10.根据权利要求1所述的半导体封装件，
其中，当在俯视图中观察时，所述封装基板具有中央区域和包围所述中央区域的边缘区域，
其中，所述基板位于所述封装基板的所述中央区域上，
其中，所述加强件结构位于所述封装基板的所述边缘区域上，并且
其中，所述封装基板的所述边缘区域包括所述拐角区域。
11.根据权利要求1所述的半导体封装件，其中，所述封装基板的所述拐角区域与所述封装基板的两个相邻的侧表面彼此汇合处的拐角相邻。
12.一种半导体封装件，所述半导体封装件包括：
封装基板，当在俯视图中观察时，所述封装基板具有第一区域和包围所述第一区域的第二区域；
第一半导体芯片，所述第一半导体芯片位于所述封装基板的所述第一区域上；
加强件结构，所述加强件结构位于所述封装基板的所述第二区域上，所述加强件结构具有孔；和
粘合层，所述粘合层位于所述封装基板与所述加强件结构之间，
其中，所述孔穿透所述加强件结构的顶表面和所述加强件结构的底表面，并且
其中，所述粘合层延伸到所述加强件结构的所述孔中。
13.根据权利要求12所述的半导体封装件，其中，所述粘合层的杨氏模量小于所述加强件结构的杨氏模量。
14.根据权利要求12所述的半导体封装件，
其中，所述封装基板的所述第二区域包括拐角区域，
其中，所述拐角区域与所述封装基板的两个相邻的侧表面彼此汇合处的拐角相邻，并且
其中，当在俯视图中观察时，所述孔与所述封装基板的所述拐角区域交叠。
15.根据权利要求12所述的半导体封装件，其中，所述孔的宽度是所述加强件结构的宽度的50％至95％。
16.根据权利要求12所述的半导体封装件，所述半导体封装件还包括：
中介基板，所述中介基板位于所述封装基板与所述第一半导体芯片之间；和
第二半导体芯片，所述第二半导体芯片安装在所述中介基板上，并且与所述第一半导体芯片横向间隔开。
17.一种半导体封装件，所述半导体封装件包括：
封装基板，所述封装基板具有中央区域、第一边缘区域和第二边缘区域；
中介基板，所述中介基板位于所述封装基板的所述中心区域的顶表面上；
多个中介凸块，所述多个中介凸块位于所述封装基板与所述中介基板之间；
底部填充层，所述底部填充层位于所述封装基板与所述中介基板之间的间隙中，所述底部填充层包封所述中介凸块；
第一半导体芯片，所述第一半导体芯片安装在所述中介基板的顶表面上；
多个第一凸块，所述多个第一凸块位于所述中介基板与所述第一半导体芯片之间；
芯片堆叠，所述芯片堆叠安装在所述中介基板的顶表面上，并且与所述第一半导体芯片间隔开，所述芯片堆叠包括多个堆叠的第二半导体芯片；
多个第二凸块，所述多个第二凸块位于所述第二半导体芯片之间；
加强件结构，所述加强件结构位于所述封装基板的所述第一边缘区域的顶表面上和所述第二边缘区域的顶表面上，所述加强件结构具有孔；和
粘合层，所述粘合层位于所述封装基板与所述加强件结构的底表面之间，
其中，所述孔穿透所述加强件结构的顶表面和所述加强件结构的底表面，所述孔位于所述封装基板的所述第一边缘区域上，并且
其中，所述封装基板的所述第一边缘区域与所述封装基板的两个相邻的侧表面彼此汇合处的拐角相邻。
18.根据权利要求17所述的半导体封装件，其中，所述粘合层位于所述加强件结构的所述孔中，并且覆盖所述孔的侧壁的至少一部分。
19.根据权利要求17所述的半导体封装件，
其中，所述粘合层与所述底部填充层间隔开，并且包括与所述底部填充层的材料不同的材料，并且
其中，所述第一半导体芯片的类型不同于所述第二半导体芯片的类型。
20.根据权利要求17所述的半导体封装件，
其中，所述粘合层的杨氏模量为所述加强件结构的杨氏模量的1/3000至1/100，
其中，所述孔的宽度为所述封装基板的宽度的50％至95％，并且
其中，所述加强件结构的高度为0.2mm至3.0mm。
CN202110405250.3A 2020-07-13 2021-04-15 半导体封装件 Pending CN113937068A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200086265A KR20220008097A (ko) 2020-07-13 2020-07-13 반도체 패키지
KR10-2020-0086265 2020-07-13

Publications (1)

Publication Number Publication Date
CN113937068A true CN113937068A (zh) 2022-01-14

Family

ID=79173003

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110405250.3A Pending CN113937068A (zh) 2020-07-13 2021-04-15 半导体封装件

Country Status (4)

Country Link
US (1) US20220013487A1 (zh)
KR (1) KR20220008097A (zh)
CN (1) CN113937068A (zh)
TW (1) TW202203394A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450622B2 (en) * 2021-01-20 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
TWI790916B (zh) * 2022-02-09 2023-01-21 矽品精密工業股份有限公司 電子封裝件及其製法
CN117712194B (zh) * 2024-02-06 2024-05-28 浙江晶科能源有限公司 太阳能电池及光伏组件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394809B1 (ko) * 2001-08-09 2003-08-14 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9832860B2 (en) * 2014-09-26 2017-11-28 Intel Corporation Panel level fabrication of package substrates with integrated stiffeners
MY198980A (en) * 2017-06-30 2023-10-05 Tahoe Res Ltd Capacitors embedded in stiffeners for small form-factor and methods of assembling same
US10403581B2 (en) * 2017-09-29 2019-09-03 Intel Corporation Electronic device packages with attenuated electromagnetic interference signals
US11282825B2 (en) * 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure

Also Published As

Publication number Publication date
KR20220008097A (ko) 2022-01-20
TW202203394A (zh) 2022-01-16
US20220013487A1 (en) 2022-01-13

Similar Documents

Publication Publication Date Title
CN113937068A (zh) 半导体封装件
KR20190008723A (ko) 반도체 패키지
US11670565B2 (en) Semiconductor package with heat dissipation member
US11587897B2 (en) Semiconductor device
CN115206897A (zh) 包括模制层的半导体封装件
US20220319944A1 (en) Semiconductor package and method of manufacturing semiconductor package
US20220320043A1 (en) Semiconductor package and method of fabricating the same
US20220352138A1 (en) Semiconductor package
KR20240026722A (ko) 반도체 패키지
US11482507B2 (en) Semiconductor package having molding member and heat dissipation member
KR20230041250A (ko) 반도체 소자 및 이를 포함하는 반도체 패키지
KR20220126320A (ko) 반도체 패키지
US20240153886A1 (en) Semiconductor package
US11626385B2 (en) Semiconductor package
US20240203942A1 (en) Semiconductor package
KR20220009534A (ko) 반도체 패키지 및 이의 제조 방법
US20230170290A1 (en) Semiconductor package
KR20080105242A (ko) 칩 스케일 반도체 패키지
US20240055405A1 (en) Semiconductor package
KR20230063230A (ko) 반도체 패키지
KR20240031825A (ko) 반도체 패키지 및 그 제조 방법
CN117476565A (zh) 半导体封装件
TW202420527A (zh) 半導體封裝
KR20230041860A (ko) 반도체 패키지
KR20240022223A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination