TW202203394A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202203394A
TW202203394A TW110106081A TW110106081A TW202203394A TW 202203394 A TW202203394 A TW 202203394A TW 110106081 A TW110106081 A TW 110106081A TW 110106081 A TW110106081 A TW 110106081A TW 202203394 A TW202203394 A TW 202203394A
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Taiwan
Prior art keywords
substrate
stiffener structure
package
package substrate
semiconductor
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TW110106081A
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English (en)
Inventor
金泳龍
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南韓商三星電子股份有限公司
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Publication of TW202203394A publication Critical patent/TW202203394A/zh

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Abstract

本發明揭露一種半導體封裝，包括：封裝基板；基板，位於所述封裝基板上；第一半導體晶片，安裝於所述基板上；以及加勁件結構，位於所述封裝基板上且具有孔。所述加勁件結構與所述基板橫向間隔開。所述孔穿透所述加勁件結構的頂表面及所述加勁件結構的底表面。當以平面圖觀看時，所述孔與所述封裝基板的拐角區交疊。

Description

半導體封裝
本發明概念是有關於一種半導體封裝，且更具體而言，是有關於一種包括加勁件結構的半導體封裝。
提供半導體封裝來實施積體電路晶片以供在電子產品中使用。通常，半導體封裝被配置成使得半導體晶片安裝於印刷電路板（printed circuit board，PCB）上，且接合導線或凸塊用於將半導體晶片電性連接至印刷電路板。隨著電子行業的發展，已進行各種研究來改良半導體封裝的可靠性及耐久性。
本發明概念的一些示例性實施例提供一種可靠性得以提高的半導體封裝。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：封裝基板；基板，位於所述封裝基板上；第一半導體晶片，安裝於所述基板上；以及加勁件結構，位於所述封裝基板上，所述加勁件結構具有孔。所述加勁件結構可與所述基板橫向間隔開。所述孔可穿透所述加勁件結構的頂表面及所述加勁件結構的底表面。當以平面圖觀看時，所述孔可與所述封裝基板的拐角區交疊。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：封裝基板，具有第一區及第二區，當以平面圖觀看時，所述第二區環繞所述第一區；第一半導體晶片，位於所述封裝基板的所述第一區上；加勁件結構，位於所述封裝基板的所述第二區上，所述加勁件結構具有孔；以及黏合層，位於所述封裝基板與所述加勁件結構之間。所述孔可穿透所述加勁件結構的頂表面及所述加勁件結構的底表面。所述黏合層可延伸至所述加勁件結構的所述孔中。
根據本發明概念的一些示例性實施例，一種半導體封裝可包括：封裝基板，具有中心區、第一邊緣區及第二邊緣區；中介層基板，位於所述封裝基板的所述中心區的頂表面上；多個中介層凸塊，位於所述封裝基板與所述中介層基板之間；底部填充層，位於所述封裝基板與所述中介層基板之間的間隙中，所述底部填充層包封所述中介層凸塊；第一半導體晶片，安裝於所述中介層基板的頂表面上；多個第一凸塊，位於所述中介層基板與所述第一半導體晶片之間；晶片堆疊，安裝於所述中介層基板的所述頂表面上且與所述第一半導體晶片間隔開，所述晶片堆疊包括多個經堆疊的第二半導體晶片；多個第二凸塊，位於所述第二半導體晶片之間；加勁件結構，位於所述封裝基板的所述第一邊緣區及所述第二邊緣區的頂表面上，所述加勁件結構具有孔；以及黏合層，位於所述封裝基板與所述加勁件結構的底表面之間。所述孔可穿透所述加勁件結構的頂表面及所述加勁件結構的所述底表面。所述孔可位於所述封裝基板的所述第一邊緣區上。所述封裝基板的所述第一邊緣區可鄰近於其中所述封裝基板的二個相鄰側表面彼此交會的拐角。
在本說明中，相同的參考編號指示相同的組件。現在，以下將闡述根據本發明概念的半導體封裝及其製作方法。
圖1A例示示出根據示例性實施例的半導體封裝的平面圖。圖1B例示沿著圖1A所示線I-I’截取的剖視圖。圖1C例示示出圖1B所示剖面A的放大圖。圖1D例示沿著圖1A所示線II-II’截取的剖視圖。
參照圖1A、圖1B、圖1C及圖1C，半導體封裝可包括封裝基板100、第一半導體晶片310、加勁件結構500及黏合層600。半導體封裝可更包括選自以下的至少一者：外部端子150、中介層基板200、中介層凸塊250、底部填充層240、第二半導體晶片320、第三半導體晶片330及模塑層400。
當如圖1A所示以平面圖觀看時，封裝基板100可包括第一區R1及第二區R2。第一區R1可為封裝基板100的中心區。第二區R2可為封裝基板100的邊緣區。第二區R2可與第一區R1間隔開。當以平面圖觀看時，第二區R2可環繞第一區R1。第二區R2可夾置於第一區R1與封裝基板100的側表面100c之間。第二區R2可包括第一邊緣區ER1及第二邊緣區ER2。第一邊緣區ER1可對應於封裝基板100的拐角區。例如，第一邊緣區ER1中的每一者可鄰近於其中封裝基板100的二個鄰近側表面100c彼此交會的拐角100z。封裝基板100的第二邊緣區ER2中的每一者可設置於第一邊緣區ER1中的二者之間且鄰近於封裝基板100的側表面100c之一。
如圖1B及圖1D所示，封裝基板100可包括介電基底層110、基板接墊120及內部線130。介電基底層110可包括多個經堆疊層。作為另一選擇，介電基底層110可為單個層。基板接墊120可在封裝基板100的頂表面上暴露出。例如，基板接墊120的頂表面可與封裝基板100的頂表面共面。內部線130可設置於介電基底層110中且耦合至基板接墊120。片語「二個組件彼此電性連接/耦合」可包括所述二個組件彼此直接地或者藉由不同的導電組件彼此間接地連接/耦合。在本說明中，片語「電性連接/耦合至封裝基板100」可指示「電性連接/耦合至內部線130」的含義。基板接墊120及內部線130可包含金屬，例如銅、鋁、鎢及鈦中的一或多者。例如，封裝基板100可為具有電路圖案的印刷電路板（PCB）。對於另一實例，重佈線層可用作封裝基板100。
外部端子150可設置於封裝基板100的底表面上且耦合至內部線130。外部電性訊號可藉由外部端子150傳送至內部線130。外部端子150可包括焊料球。外部端子150可包含金屬，例如焊料材料。焊料材料可包括錫（Sn）、銀（Ag）、鋅（Zn）或其任何合金。
在封裝基板100的第一區R1上可設置有基板。所述基板可為中介層基板200。中介層基板200可包括金屬接墊220及金屬線230。金屬接墊220可在中介層基板200的頂表面上暴露出。例如，金屬接墊220的頂表面可與中介層基板200的頂表面共面。金屬線230可設置於中介層基板200中且耦合至金屬接墊220。在本說明中，片語「電性連接/耦合至中介層基板200」可指示「電性連接/耦合至金屬線230」的含義。金屬接墊220及金屬線230可包含金屬，例如銅、鋁、鎢及鈦中的一或多者。
本文中在提及定向、佈局、位置、形狀、尺寸、量或其他度量時所使用的例如「相同」、「相等」、「平面」或「共面」等用語未必意指完全相同的定向、佈局、位置、形狀、尺寸、量或其他度量，而是旨在囊括可例如由於製造製程而出現的可接受變動內幾乎相同的定向、佈局、位置、形狀、尺寸、量或其他度量。除非上下文或其他陳述另有指示，否則本文中可使用用語「實質上」來強調此種含義。例如，被闡述為「實質上相同」、「實質上相等」或「實質上平面」的用語可為完全相同、相等或平面的，或者可在可例如由於製造製程而出現的可接受變動內為相同、相等或平面的。
中介層凸塊250可夾置於封裝基板100與中介層基板200之間且耦合至封裝基板100及中介層基板200。例如，中介層凸塊250可耦合至基板接墊120及金屬線230。在示例性實施例中，中介層凸塊250可直接接觸（即，觸碰）基板接墊120的頂表面。中介層凸塊250可包括焊料球、凸塊及柱中的一或多者。中介層凸塊250可包含金屬，例如焊料材料。底部填充層240可設置於封裝基板100的第一區R1上。底部填充層240可設置於封裝基板100與中介層基板200之間的間隙中，藉此包封中介層凸塊250。底部填充層240可包含介電聚合物，例如環氧系聚合物。
第一半導體晶片310可設置於封裝基板100的第一區R1的頂表面上。在本說明中，片語「某一組件位於另一組件上」可意指「所述某一組件直接形成於另一組件上」或者「第三組件夾置於所述某一組件與另一組件之間」。例如，中介層基板200可夾置於封裝基板100與第一半導體晶片310之間。第一半導體晶片310可設置於中介層基板200的頂表面上。第一半導體晶片310可包括邏輯晶片、緩衝器晶片或系統晶片（system-on-chip，SOC）。第一半導體晶片310可例如為特殊應用積體電路（application specific integrated circuit，ASIC）晶片或應用處理器（application processor，AP）晶片。所述ASIC晶片可包括特殊應用積體電路（ASIC）。第一半導體晶片310可包括中央處理單元（central processing unit，CPU）或圖形處理單元（graphic processing unit，GPU）。
第一凸塊315可夾置於中介層基板200與第一半導體晶片310之間且電性連接中介層基板200與第一半導體晶片310。在本說明中，片語「電性連接至半導體晶片」可意指「電性連接至半導體晶片中的積體電路」。例如，第一凸塊315可耦合至第一半導體晶片310的晶片接墊311且耦合至對應金屬接墊220。在示例性實施例中，第一凸塊315可接觸晶片接墊311的底表面及對應金屬接墊220的頂表面。第一凸塊315可包含導電材料，例如焊料材料。第一凸塊315可設置成多個。第一凸塊315的間距P1可小於多個中介層凸塊250的間距P20。第一凸塊315的間距P1可小於多個外部端子150的間距P10。所述多個中介層凸塊250的間距P20可小於所述多個外部端子150的間距P10。
第一底部填充圖案410可設置於中介層基板200與第一半導體晶片310之間的第一間隙中，藉此包封第一凸塊315。第一底部填充圖案410可包含介電聚合物，例如環氧系聚合物。
第二半導體晶片320可設置於封裝基板100的第一區R1的頂表面上。例如，第二半導體晶片320可設置於中介層基板200的頂表面上。第二半導體晶片320可設置成多個，且所述多個第二半導體晶片320可堆疊於中介層基板200的頂表面上。第二半導體晶片320可為與第一半導體晶片310不同的類型。第二半導體晶片320可為記憶體晶片。記憶體晶片可包括高頻寬記憶體（high bandwidth memory，HBM）晶片。第二半導體晶片320可包括動態隨機記憶體（dynamic random memory，DRAM）晶片。
第二半導體晶片320中的每一者可包括積體電路（圖中未示出）、晶片連接接墊326及貫通結構（through structure）327。積體電路可設置於第二半導體晶片320中。貫通結構327可穿透對應第二半導體晶片320且可與積體電路電性連接。對比之下，最上第二半導體晶片320可不包括貫通結構327。
第三半導體晶片330可夾置於中介層基板200與最下第二半導體晶片320之間。第三半導體晶片330可為與第一半導體晶片310及第二半導體晶片320不同的類型。例如，第三半導體晶片330可為邏輯晶片，且可具有與第一半導體晶片310的功能不同的功能。第三半導體晶片330可具有與第二半導體晶片320的寬度不同的寬度，但本發明概念並非僅限於此。第三半導體晶片330可包括積體電路（圖中未示出）、導電晶片接墊336及穿孔（through via）337。積體電路可設置於第三半導體晶片330中。穿孔337可穿透第三半導體晶片330且可與第三半導體晶片330的積體電路電性連接。第二半導體晶片320及第三半導體晶片330可構成晶片堆疊。不同於所示者，可省略第三半導體晶片330。
多個第二凸塊325可夾置於二個相鄰的第二半導體晶片320之間。第二凸塊325可與對應第二半導體晶片320的貫通結構327及/或積體電路電性連接。第二半導體晶片320可藉由第二凸塊325彼此電性連接。第二凸塊325可更夾置於第三半導體晶片330與最下第二半導體晶片320之間。第二半導體晶片320可藉由第二凸塊325電性連接至第三半導體晶片330。第二凸塊325可包含導電材料，例如焊料材料。第二凸塊325的間距P2可小於中介層凸塊250的間距P20。第二凸塊325的間距P2可小於外部端子150的間距P10。多個第二底部填充圖案420可設置於第二半導體晶片320之間的第二間隙中以及第三半導體晶片330與最下第二半導體晶片320之間的第三間隙中。第二底部填充圖案420中的每一者可包封對應第二凸塊325。第二底部填充圖案420可包含介電聚合物，例如環氧系聚合物。
第三凸塊335可夾置於中介層基板200與第三半導體晶片330之間且電性連接中介層基板200與第三半導體晶片330。第三凸塊335可包含導電材料，例如焊料材料。因此，第二半導體晶片320及第三半導體晶片330可藉由第三凸塊335及金屬線230電性連接至第一半導體晶片310或外部端子150。第三底部填充圖案430可設置於中介層基板200與第三半導體晶片330之間的第四間隙中，藉此包封第三凸塊335。第三底部填充圖案430可包含介電聚合物，例如環氧系聚合物。
模塑層400可設置於封裝基板100上，藉此覆蓋第一半導體晶片310的側壁、第二半導體晶片320的側壁及第三半導體晶片330的側壁。模塑層400可暴露出第一半導體晶片310的頂表面及最上第二半導體晶片320的頂表面。作為另一選擇，模塑層400可更覆蓋第一半導體晶片310的頂表面及最上第二半導體晶片320的頂表面。模塑層400可包含介電聚合物，例如環氧系聚合物。
半導體封裝可更包括散熱板700。散熱板700可設置於選自第一半導體晶片310的頂表面及最上第二半導體晶片320的頂表面的至少一者上。散熱板700可更覆蓋模塑層400的頂表面。散熱板700可延伸至模塑層400的側壁上。散熱板700可包括散熱塊（heat slug）或散熱片（heat sink）。散熱板700可包含具有高導熱性的材料，例如金屬。
加勁件結構500可設置於封裝基板100的第二區R2上。加勁件結構500可不設置於封裝基板100的第一區R1上。加勁件結構500可被設置成與中介層基板200、底部填充層240、第一半導體晶片310、第二半導體晶片320、第三半導體晶片330及模塑層400橫向間隔開。加勁件結構500可具有彼此相對的內側壁500c及外側壁500d。加勁件結構500的內側壁500c可朝向中介層基板200且與中介層基板200間隔開。加勁件結構500可包含金屬。例如，加勁件結構500可包含銅、不銹鋼（stainless steel，SUS）、鋁碳化矽（aluminum silicon carbide，AlSiC）及鈦中的一或多者。
加勁件結構500可具有相對大的勁度。可採用楊氏模數（Young's modulus）來估計某一材料的勁度。加勁件結構500可具有例如約100十億帕（GPa）至約300十億帕的楊氏模數。組件的熱膨脹係數之差可引發半導體封裝的翹曲。由於加勁件結構500具有相對大的勁度，因此加勁件結構500可固定封裝基板100的第二區R2。因此，可防止封裝基板100翹曲。當加勁件結構500的楊氏模數小於約100十億帕時，可難以充分防止封裝基板100翹曲。
在封裝基板100的第一區R1上，中介層凸塊250與封裝基板100之間可能會出現熱膨脹係數之差。根據一些示例性實施例，加勁件結構500可設置於封裝基板100的第二區R2上。加勁件結構500可具有與封裝基板100的熱膨脹係數不同的熱膨脹係數。例如，加勁件結構500可具有較封裝基板100的熱膨脹係數大的熱膨脹係數。因此，在封裝基板100的第一區R1上封裝基板100與中介層凸塊250的熱膨脹係數之差可與在封裝基板100的第二區R2上封裝基板100與加勁件結構500的熱膨脹係數之差相抵消。因此，可防止封裝基板100或中介層基板200翹曲。
根據一些示例性實施例，加勁件結構500可具有孔590。孔590可穿透加勁件結構500的頂表面500a及底表面500b。加勁件結構500的底表面500b可面對封裝基板100。頂表面500a可與加勁件結構500的底表面500b相對。孔590可設置於加勁件結構500的內側壁500c與外側壁500d之間。
當加勁件結構500不具有孔590時，加勁件結構500可在半導體封裝的操作期間對封裝基板100施加應力。所述應力可由於加勁件結構500的高勁度而出現。所述應力可集中於封裝基板100的第一邊緣區ER1上。當半導體封裝反覆地操作時，應力可在封裝基板100與底部填充層240之間產生裂縫。裂縫可朝向中介層凸塊250傳播。在此種情形中，封裝基板100與選自第一半導體晶片310、第二半導體晶片320及第三半導體晶片330的至少一者之間可設置有不良的電性連接。加勁件結構500與封裝基板100之間的交疊區域的增加可引發應力引發裂縫的出現的增加。根據一些示例性實施例，由於加勁件結構500具有孔590，因此加勁件結構500與封裝基板100之間可設置有減小的交疊區域。當以平面圖觀看時，交疊區域可指示其中加勁件結構500的底表面500b與封裝基板100交疊的區域。因此，可減小對封裝基板100施加的應力並提高半導體封裝的可靠性。
根據一些示例性實施例，孔590可設置於封裝基板100的第一邊緣區ER1之一上。例如，加勁件結構500可具有多個孔590，且所述多個孔590可與封裝基板100的對應第一邊緣區ER1交疊。在封裝基板100的第一邊緣區ER1中的每一者上，加勁件結構500與封裝基板100之間可設置有減小的交疊區域。藉由減小交疊區域，可減小對封裝基板100的第一邊緣區ER1施加的應力且有效減少或避免封裝基板100與底部填充層240之間的裂縫的出現。因此，半導體封裝可提高可靠性。以下說明將著重於單個孔590。
黏合層600可設置於封裝基板100的第二區R2上。黏合層600可夾置於封裝基板100的頂表面與加勁件結構500的底表面500b之間。黏合層600可將加勁件結構500固定至封裝基板100。如圖1C所示，黏合層600可部分地暴露出加勁件結構500的底表面500b。例如，黏合層600可接觸加勁件結構500的底表面500b的一部分。作為另一選擇，黏合層600可完全覆蓋加勁件結構500的底表面500b。黏合層600可設置於加勁件結構500的孔590中。例如，黏合層600可延伸至孔590的側壁590c上，進而接觸孔590的側壁590c。黏合層600可填充孔590的至少一部。例如，黏合層600可填充孔590的下部分。黏合層600可具有最上表面600a，最上表面600a位於較加勁件結構500的頂表面500a的水平高度低的水平高度處。黏合層600的最上表面600a可位於較加勁件結構500的底表面500b高的水平高度處。
黏合層600可為相對撓性的。例如，黏合層600可較加勁件結構500更具撓性。黏合層600可具有相對低的勁度。例如，黏合層600可具有較加勁件結構500的勁度低的勁度。黏合層600的楊氏模數可為加勁件結構500的楊氏模數的約1/3000至約1/10。例如，黏合層600可具有約0.01十億帕至約1十億帕的楊氏模數。由於黏合層600具有低勁度且延伸至孔590中，因此對封裝基板100施加的應力可降低。因此，半導體封裝可提高可靠性。
如圖1A及圖1B所示，黏合層600可不設置於封裝基板100的第一區R1上。黏合層600可與底部填充層240及中介層基板200間隔開，且可環繞底部填充層240及中介層基板200。黏合層600可包含與底部填充層240的材料不同的材料。黏合層600可包含與第一底部填充圖案410、第二底部填充圖案420及第三底部填充圖案430的材料不同的材料。因此，黏合層600可具有與底部填充層240的勁度不同的勁度。如圖1C所示，黏合層600可包括基底層601，且基底層601可包含聚矽氧系介電材料。聚矽氧系介電材料可例如包括聚矽氧系聚合物或聚矽氧系橡膠。黏合層600可更包括填充劑602。填充劑602可設置於基底層601中。例如，填充劑602可分佈於基底層601中。由於黏合層600更包括填充劑602，因此黏合層600可提高機械強度。例如，填充劑602的機械強度可大於基底層601的機械強度。填充劑602可包含與基底層601的材料不同的材料。填充劑602可包含無機材料。例如，填充劑602可包含氧化矽（SiOx）或氧化鋁（AlOx），其中x是正實數。
當孔590具有較加勁件結構500的寬度W1的約50%小的寬度W2時，在封裝基板100與底部填充層240之間可出現應力引發裂縫。當孔590的寬度W2大於加勁件結構500的寬度W1的約95%時，加勁件結構500可降低機械穩定性。根據一些示例性實施例，孔590的寬度W2可為加勁件結構500的寬度W1的約50%至約95%。因此，裂縫的出現可減少，且加勁件結構500的穩定性可得以保全。可在加勁件結構500的底表面500b處量測孔590的寬度W2及加勁件結構500的寬度W1。加勁件結構500的寬度W1可對應於加勁件結構500的內側壁500c與外側壁500d之間的間隔。可在與量測加勁件結構500的對應寬度W1相同的方向上量測孔590的寬度W2。
加勁件結構500可具有約0.2毫米（mm）至約3.0毫米的高度H。加勁件結構500的高度H可指示加勁件結構500的頂表面500a與底表面500b之間的間隔。當加勁件結構500的高度H小於約0.2毫米時，可能不足以使加勁件結構500防止封裝基板100翹曲。當加勁件結構500的高度H大於約3.0毫米時，可難以製作半導體封裝且難以達成半導體封裝的緊湊度。
不同於所示者，可省略選自以下的至少一者：中介層基板200、中介層凸塊250、底部填充層240、第一半導體晶片310、第二半導體晶片320、第三半導體晶片330、第一底部填充圖案410、第二底部填充圖案420、第三底部填充圖案430、模塑層400、第一凸塊315、第二凸塊325及第三凸塊335。例如，可省略中介層基板200、中介層凸塊250及底部填充層240，且第一半導體晶片310及第三半導體晶片330可直接安裝於封裝基板100上。例如，當第一半導體晶片310直接安裝於封裝基板100上時，第一凸塊315可直接耦合至對應基板接墊120。當第三半導體晶片330直接安裝於封裝基板100上時，第三凸塊335可直接耦合至對應基板接墊120。
作為另一實例，可省略中介層基板200、中介層凸塊250、底部填充層240以及第二半導體晶片320及第三半導體晶片330，且第一半導體晶片310可直接安裝於封裝基板100上。作為另一實例，可省略第一半導體晶片310、第一凸塊315及第一底部填充圖案410。作為另一實例，可省略第一半導體晶片310及中介層基板200，且第三半導體晶片330可直接安裝於封裝基板100上。作為另一實例，可省略散熱板700。可以各種方式改變由第一半導體晶片310而成的晶片堆疊及由第二半導體晶片320而成的晶片堆疊的數目。
以下將闡述根據一些示例性實施例的黏合層及加勁件結構。以下將不再對以上所論述的說明予以贅述。
圖2A例示圖1A所示剖面A的放大剖視圖，其示出根據一些示例性實施例的黏合層及加勁件結構。圖2B例示圖1A所示剖面A的放大剖視圖，其示出根據一些示例性實施例的黏合層及加勁件結構。在闡釋圖2A及圖2B時亦將參照圖1A、圖1B及圖1D。
參照圖2A及圖2B，半導體封裝可包括加勁件結構500及黏合層600。加勁件結構500及黏合層600可與以上參照圖1A至圖1D所論述的那些實質上相同。例如，加勁件結構500可具有孔590，孔590穿透加勁件結構500的頂表面500a及底表面500b。黏合層600可延伸至加勁件結構500的孔590中，且可接觸孔590的側壁590c。可以各種方式改變黏合層600的高度及形狀。
如圖2A所示，黏合層600可填充孔590的上部分及下部分。黏合層600的最上表面600a可位於與加勁件結構500的頂表面500a的水平高度實質上相同的水平高度處。例如，黏合層600的最上表面600a可與加勁件結構500的頂表面500a共面。黏合層600可完全覆蓋加勁件結構500的底表面500b，但本發明概念並非僅限於此。
如圖2B所示，黏合層600可填充加勁件結構500的孔590，且可延伸至加勁件結構500的頂表面500a上。黏合層600可更覆蓋加勁件結構500的頂表面500a的至少一部分。例如，黏合層600可接觸加勁件結構500的頂表面500a的至少一部分。黏合層600的最上表面600a可位於較加勁件結構500的頂表面500a的水平高度高的水平高度處。黏合層600可覆蓋加勁件結構500的底表面500b。黏合層600可更覆蓋外側壁500d的下部分及內側壁500c的下部分。
在除圖1C、圖2A及圖2B之外的圖中，為方便繪製未例示基底層601及填充劑602。然而，此種例示並非將基底層601或填充劑602排除。
以下將闡述加勁件結構的孔。
圖3A例示示出根據一些示例性實施例的半導體封裝中所包括的加勁件結構的孔的平面圖。圖3B例示示出根據一些示例性實施例的半導體封裝中所包括的加勁件結構的孔的平面圖。在闡釋圖3A及圖3B時亦將參照圖1B至圖1D。
參照圖3A及圖3B，加勁件結構500可具有孔590。孔590可具有與在圖1B至圖1D所示實施例中所論述的橫截面實質上相同的橫截面。例如，孔590可穿透加勁件結構500。對比之下，孔590可設置於封裝基板100的第一邊緣區ER1及第二邊緣區ER2上。
如圖3A所示，加勁件結構500可具有單個孔590。當以平面圖觀看時，孔590可包括第一孔部分591及第二孔部分592。第一孔部分591可平行於第一方向D1。第一孔部分591可在第二方向D2上彼此間隔開。第一方向D1可平行於封裝基板100的頂表面。第二方向D2可平行於封裝基板100的頂表面且可與第一方向D1相交。第二孔部分592可平行於第二方向D2。第二孔部分592可在第一方向D1上彼此間隔開。第二孔部分592可在空間上與對應第一孔部分591相連接。孔590可為其中第一孔部分591與第二孔部分592相連接的單個孔。孔590可例如具有閉合多邊形形狀。
參照圖3B，加勁件結構500可具有多個孔590。孔590可彼此間隔開。孔590中的每一者可具有圓形形狀。然而，可以各種方式改變孔590的形狀。例如，孔590中的每一者可具有四邊形形狀、六邊形形狀、八邊形形狀或任何適合的多邊形形狀。孔590的存在可緩解對封裝基板100的第一邊緣區ER1及第二邊緣區ER2施加的應力。
圖4A例示示出根據一些示例性實施例的半導體封裝的平面圖。圖4B例示沿著圖4A所示線I-I’截取的剖視圖。圖4C例示沿著圖4A所示線II-II’截取的剖視圖。以下將不再對以上所論述的說明予以贅述。
參照圖4A至圖4C，半導體封裝可包括封裝基板100、第一半導體晶片310、加勁件結構500及黏合層600。半導體封裝可更包括選自以下的至少一者：外部端子150、中介層基板200、中介層凸塊250、底部填充層240、第二半導體晶片320、第三半導體晶片330、第一凸塊至第三凸塊315、325及335、第一底部填充圖案至第三底部填充圖案410、420及430、模塑層400及散熱板700。
加勁件結構500可設置於封裝基板100的第一邊緣區ER1及第二邊緣區ER2上。加勁件結構500可具有孔590。當以平面圖觀看時，孔590可設置於封裝基板100的對應第一邊緣區ER1上。
黏合層600可夾置於封裝基板100與加勁件結構500之間。黏合層600可包括第一黏合層610及第二黏合層620。當如圖4A所示以平面圖觀看時，第一黏合層610可與封裝基板100的對應第一邊緣區ER1交疊。當以平面圖觀看時，第一黏合層610可與對應孔590交疊。如圖4B所示，第一黏合層610中的每一者可延伸至對應孔590中。第一黏合層610中的每一者可覆蓋對應孔590的側壁590c。如圖4B所示，第一黏合層610可填充孔590的下部分。第一黏合層610的最上表面可位於較加勁件結構500的頂表面500a的水平高度低的水平高度處。作為另一選擇，如在圖2A所示黏合層600的實例中所論述，第一黏合層610的最上表面可位於與加勁件結構500的頂表面500a的水平高度相同的水平高度處。作為另一選擇，如在圖2B所示黏合層600的實例中所論述，第一黏合層610可覆蓋加勁件結構500的頂表面500a。
第一黏合層610中的每一者可包含與在圖1A至圖1D所示黏合層600的實例中所論述的材料實質上相同的材料。例如，第一黏合層610中的每一者可如圖1C所示包括基底層601，且基底層601可包含聚矽氧系聚合物或聚矽氧系橡膠。第一黏合層610中的每一者可更包括填充劑602，且填充劑602可包含無機材料，例如氧化矽或氧化鋁。
如圖4A及圖4C所示，第二黏合層620可與封裝基板100的對應第二邊緣區ER2交疊。第二黏合層620中的每一者可設置於第一黏合層610之間。第二黏合層620的黏合力可大於第一黏合層610的黏合力。因此，第二黏合層620可將加勁件結構500穩定地固定至封裝基板100。第二黏合層620可具有與第一黏合層610的材料不同的材料。第二黏合層620可例如包含環氧系聚合物。
當自加勁件結構500省略孔590時，且當省略黏合層600時，應力可集中於封裝基板100的第一邊緣區ER1上。第二黏合層620可不設置於封裝基板100的第一邊緣區ER1上。黏合層600可與加勁件結構500的孔590間隔開。第一黏合層610可具有低勁度及小楊氏模數。第一黏合層610的楊氏模數可小於第二黏合層620的楊氏模數。例如，第一黏合層610的楊氏模數可為加勁件結構500的楊氏模數的約1/3000至約1/100。例如，第一黏合層610可具有約0.01十億帕至約1十億帕的楊氏模數。由於第一黏合層610延伸至封裝基板100的第一邊緣區ER1上的孔590中，因此可減小對封裝基板100的第一邊緣區ER1施加的應力且有效地減少或避免封裝基板100與底部填充層240之間的裂縫的出現。因此，半導體封裝可提高可靠性。
封裝基板100、第一半導體晶片至第三半導體晶片310、320及330、外部端子150、中介層基板200、底部填充層240、第一凸塊至第三凸塊315、325及335、第一底部填充圖案至第三底部填充圖案410、420及430、模塑層400及散熱板700可與以上在圖1A至圖1D所示實施例中所論述的那些實質上相同。
圖5例示沿著圖1A所示線I-I’截取的剖視圖，其示出根據一些示例性實施例製作半導體封裝的方法。以下將不再對以上所論述的說明予以贅述。
參照圖5，可製備初步封裝1000。初步封裝1000可包括中介層基板200、中介層凸塊250、第一半導體晶片310、第二半導體晶片320及第三半導體晶片330。中介層凸塊250可設置於中介層基板200的底表面上。初步封裝1000可更包括第一凸塊至第三凸塊315、325及335、第一底部填充圖案至第三底部填充圖案410、420及430、模塑層400及散熱板700。
可將初步封裝1000安裝於封裝基板100上。初步封裝1000的安裝可包括將初步封裝1000放置於封裝基板100的第一區R1上並將中介層凸塊250耦合至多個基板接墊120。然後，可在封裝基板100與中介層基板200之間形成底部填充層240，藉此包封中介層凸塊250。
可在封裝基板100的第二區R2上形成初步黏合層600P。可藉由黏合材料的施配製程來執行初步黏合層600P的形成。初步黏合層600P可不塗佈於封裝基板100的第一區R1上。可在形成底部填充層240之後形成初步黏合層600P。
可製備具有孔590的加勁件結構500。可將加勁件結構500設置於封裝基板100的第二區R2的頂表面上，以使得加勁件結構500的底表面500b能夠面對初步黏合層600P。在此種情形中，加勁件結構500的孔590可與初步黏合層600P垂直交疊。
參照圖5及圖1B，加勁件結構500可下降以使得其底表面500b能夠接觸初步黏合層600P。可對加勁件結構500施加物理力（例如壓力）。加勁件結構500可使初步黏合層600P壓縮。初步黏合層600P可與加勁件結構500的底表面500b接觸，且初步黏合層600P的至少一部分可被引入至孔590中，以藉此形成黏合層600。黏合層600可覆蓋孔590的側壁590c，且可接觸加勁件結構500的底表面500b及封裝基板100的頂表面的至少一部分。黏合層600可將加勁件結構500固定至封裝基板100的第二區R2的頂表面上。因此，最終可如圖1A至圖1D所示製作出半導體封裝。
視所沈積初步黏合層600P的體積、加勁件結構500的高度及孔590的寬度而定，可以各種方式改變加勁件結構500與黏合層600之間的佈置關係。例如，加勁件結構500及黏合層600可與圖2A或圖2B所示實施例中所論述的那些實質上相同。
圖1A至圖1D所示實施例、圖2A所示實施例、圖3A所示實施例及圖3B所示實施例可彼此組合。例如，當孔590如在圖3A或圖3B所示實施例中所論述具有平面形狀時，孔590可在其中設置有如在圖1C、圖2A或圖2B所示實施例中所論述而設置的黏合層600。
根據本發明概念，加勁件結構可設置於封裝基板的邊緣區上，且因此，可減少或避免封裝基板的翹曲。由於加勁件結構具有孔，因此，可減小加勁件結構與封裝基板之間的交疊區域。因此，對封裝基板施加的應力可降低。黏合層可設置於孔中且可具有低勁度。因此，對封裝基板施加的應力可更降低。因此，半導體封裝可提高可靠性。
對本發明概念的此詳細說明不應被理解為僅限於本文中所陳述的實施例，且在不背離本發明概念的精神及範圍的條件下，本發明概念旨在涵蓋本發明的各種組合、潤飾及變化。
100:封裝基板 100c:側表面 100z:拐角 110:介電基底層 120:基板接墊 130:內部線 150:外部端子 200:中介層基板 220:金屬接墊 230:金屬線 240:底部填充層 250:中介層凸塊 310:第一半導體晶片 311:晶片接墊 315:第一凸塊 320:第二半導體晶片 325:第二凸塊 326:晶片連接接墊 327:貫通結構 330:第三半導體晶片 335:第三凸塊 336:導電晶片接墊 337:穿孔 400:模塑層 410:第一底部填充圖案 420:第二底部填充圖案 430:第三底部填充圖案 500:加勁件結構 500a:頂表面 500b:底表面 500c:內側壁 500d:外側壁 590:孔 590c:側壁 591:第一孔部分 592:第二孔部分 600:黏合層 600a:最上表面 600P:初步黏合層 601:基底層 602:填充劑 610:第一黏合層 620:第二黏合層 700:散熱板 1000:初步封裝 A:剖面 D1:第一方向 D2:第二方向 ER1:第一邊緣區 ER2:第二邊緣區 H:高度 P1、P2、P10、P20:間距 R1:第一區 R2:第二區 W1、W2:寬度 I-I’、II-II’:線
圖1A例示示出根據示例性實施例的半導體封裝的平面圖。
圖1B例示沿著圖1A所示線I-I’截取的剖視圖。
圖1C例示示出圖1B所示剖面A的放大圖。
圖1D例示沿著圖1A所示線II-II’截取的剖視圖。
圖2A例示示出根據示例性實施例的黏合層及加勁件結構的剖視圖。
圖2B例示示出根據示例性實施例的黏合層及加勁件結構的剖視圖。
圖3A例示示出根據示例性實施例的半導體封裝中所包括的加勁件結構的孔的平面圖。
圖3B例示示出根據示例性實施例的半導體封裝中所包括的加勁件結構的孔的平面圖。
圖4A例示示出根據示例性實施例的半導體封裝的平面圖。
圖4B例示沿著圖4A所示線I-I’截取的剖視圖。
圖4C例示沿著圖4A所示線II-II’截取的剖視圖。
圖5例示示出根據示例性實施例製作半導體封裝的方法的剖視圖。
100:封裝基板
100z:拐角
110:介電基底層
120:基板接墊
130:內部線
150:外部端子
200:中介層基板
220:金屬接墊
230:金屬線
240:底部填充層
250:中介層凸塊
310:第一半導體晶片
311:晶片接墊
315:第一凸塊
320:第二半導體晶片
325:第二凸塊
326:晶片連接接墊
327:貫通結構
330:第三半導體晶片
335:第三凸塊
336:導電晶片接墊
337:穿孔
400:模塑層
410:第一底部填充圖案
420:第二底部填充圖案
430:第三底部填充圖案
500:加勁件結構
500a:頂表面
500b:底表面
500c:內側壁
500d:外側壁
590:孔
590c:側壁
600:黏合層
700:散熱板
A:剖面
ER1:第一邊緣區
P1、P2、P10、P20:間距
R1:第一區
R2:第二區
I-I’:線

Claims (20)

  1. 一種半導體封裝，包括： 封裝基板； 基板，位於所述封裝基板上； 第一半導體晶片，安裝於所述基板上；以及 加勁件結構，位於所述封裝基板上，所述加勁件結構具有孔， 其中所述加勁件結構與所述基板橫向間隔開， 其中所述孔穿透所述加勁件結構的頂表面及所述加勁件結構的底表面，且 其中當以平面圖觀看時，所述孔與所述封裝基板的拐角區交疊。
  2. 如請求項1所述的半導體封裝，更包括： 黏合層，位於所述封裝基板與所述加勁件結構之間， 其中所述黏合層延伸至所述加勁件結構的所述孔中且覆蓋所述孔的側壁的至少一部分。
  3. 如請求項2所述的半導體封裝，其中所述黏合層具有較所述加勁件結構的勁度小的勁度。
  4. 如請求項3所述的半導體封裝，其中所述黏合層的楊氏模數為所述加勁件結構的楊氏模數的約1/3000至約1/100。
  5. 如請求項4所述的半導體封裝， 其中所述黏合層的所述楊氏模數介於約0.01十億帕至約1十億帕的範圍內，且 其中所述加勁件結構的所述楊氏模數介於約100十億帕至約300十億帕的範圍內。
  6. 如請求項1所述的半導體封裝，更包括： 多個第二半導體晶片，堆疊於所述基板上， 其中所述第一半導體晶片為與所述第二半導體晶片不同的類型。
  7. 如請求項1所述的半導體封裝，更包括： 黏合層，位於所述封裝基板與所述加勁件結構之間， 其中所述黏合層包括基底層，且 其中所述基底層包含聚矽氧系聚合物或聚矽氧系橡膠。
  8. 如請求項7所述的半導體封裝， 其中所述黏合層更包括位於所述基底層中的多個填充劑， 其中所述填充劑包含與所述基底層的材料不同的材料。
  9. 如請求項1所述的半導體封裝，更包括： 多個中介層凸塊，夾置於所述封裝基板與所述基板之間且電性連接至所述封裝基板及所述基板； 底部填充層，位於所述封裝基板與所述基板之間的間隙中，所述底部填充層包封所述中介層凸塊；以及 黏合層，位於所述封裝基板與所述加勁件結構之間， 其中所述黏合層與所述底部填充層間隔開，且包含與所述底部填充層的材料不同的材料。
  10. 如請求項1所述的半導體封裝， 其中所述封裝基板具有中心區及邊緣區，當以平面圖觀看時，所述邊緣區環繞所述中心區， 其中所述基板位於所述封裝基板的所述中心區上， 其中所述加勁件結構位於所述封裝基板的所述邊緣區上，且 其中所述封裝基板的所述邊緣區包括所述拐角區。
  11. 如請求項1所述的半導體封裝，其中所述封裝基板的所述拐角區鄰近於其中所述封裝基板的二個相鄰側表面彼此交會的拐角。
  12. 一種半導體封裝，包括： 封裝基板，具有第一區及第二區，當以平面圖觀看時，所述第二區環繞所述第一區； 第一半導體晶片，位於所述封裝基板的所述第一區上； 加勁件結構，位於所述封裝基板的所述第二區上，所述加勁件結構具有孔；以及 黏合層，位於所述封裝基板與所述加勁件結構之間， 其中所述孔穿透所述加勁件結構的頂表面及所述加勁件結構的底表面，且 其中所述黏合層延伸至所述加勁件結構的所述孔中。
  13. 如請求項12所述的半導體封裝，其中所述黏合層的楊氏模數小於所述加勁件結構的楊氏模數。
  14. 如請求項12所述的半導體封裝， 其中所述封裝基板的所述第二區包括拐角區， 其中所述拐角區鄰近於其中所述封裝基板的二個相鄰側表面彼此交會的拐角，且 其中當以平面圖觀看時，所述孔與所述封裝基板的所述拐角區交疊。
  15. 如請求項12所述的半導體封裝，其中所述孔的寬度為所述加勁件結構的寬度的約50%至約95%。
  16. 如請求項12所述的半導體封裝，更包括： 中介層基板，位於所述封裝基板與所述第一半導體晶片之間；以及 第二半導體晶片，安裝於所述中介層基板上且與所述第一半導體晶片橫向間隔開。
  17. 一種半導體封裝，包括： 封裝基板，具有中心區、第一邊緣區及第二邊緣區； 中介層基板，位於所述封裝基板的所述中心區的頂表面上； 多個中介層凸塊，位於所述封裝基板與所述中介層基板之間； 底部填充層，位於所述封裝基板與所述中介層基板之間的間隙中，所述底部填充層包封所述中介層凸塊； 第一半導體晶片，安裝於所述中介層基板的頂表面上； 多個第一凸塊，位於所述中介層基板與所述第一半導體晶片之間； 晶片堆疊，安裝於所述中介層基板的所述頂表面上且與所述第一半導體晶片間隔開，所述晶片堆疊包括多個經堆疊的第二半導體晶片； 多個第二凸塊，位於所述第二半導體晶片之間； 加勁件結構，位於所述封裝基板的所述第一邊緣區及所述第二邊緣區的頂表面上，所述加勁件結構具有孔；以及 黏合層，位於所述封裝基板與所述加勁件結構的底表面之間， 其中所述孔穿透所述加勁件結構的頂表面及所述加勁件結構的所述底表面，所述孔位於所述封裝基板的所述第一邊緣區上，且 其中所述封裝基板的所述第一邊緣區鄰近於其中所述封裝基板的二個相鄰側表面彼此交會的拐角。
  18. 如請求項17所述的半導體封裝，其中所述黏合層位於所述加勁件結構的所述孔中且覆蓋所述孔的側壁的至少一部分。
  19. 如請求項17所述的半導體封裝， 其中所述黏合層與所述底部填充層間隔開且包含與所述底部填充層的材料不同的材料，且 其中所述第一半導體晶片為與所述第二半導體晶片不同的類型。
  20. 如請求項17所述的半導體封裝， 其中所述黏合層的楊氏模數為所述加勁件結構的楊氏模數的約1/3000至約1/100， 其中所述孔的寬度為所述封裝基板的寬度約50%至約95%，且 其中所述加勁件結構的高度為約0.2毫米至約3.0毫米。
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