JP5224784B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP5224784B2 JP5224784B2 JP2007290789A JP2007290789A JP5224784B2 JP 5224784 B2 JP5224784 B2 JP 5224784B2 JP 2007290789 A JP2007290789 A JP 2007290789A JP 2007290789 A JP2007290789 A JP 2007290789A JP 5224784 B2 JP5224784 B2 JP 5224784B2
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- semiconductor element
- wiring board
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- stiffener
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- 238000004519 manufacturing process Methods 0.000 title claims description 74
- 239000004065 semiconductor Substances 0.000 claims description 302
- 239000003351 stiffener Substances 0.000 claims description 242
- 239000000463 material Substances 0.000 claims description 150
- 239000000758 substrate Substances 0.000 claims description 108
- 239000000853 adhesive Substances 0.000 claims description 106
- 230000001070 adhesive effect Effects 0.000 claims description 105
- 238000005520 cutting process Methods 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 45
- 230000000149 penetrating effect Effects 0.000 claims description 33
- 230000002093 peripheral effect Effects 0.000 claims description 15
- 238000003860 storage Methods 0.000 claims 2
- 229910000679 solder Inorganic materials 0.000 description 30
- 238000012986 modification Methods 0.000 description 20
- 230000004048 modification Effects 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 239000011347 resin Substances 0.000 description 14
- 229920005989 resin Polymers 0.000 description 14
- 239000004593 Epoxy Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 238000007747 plating Methods 0.000 description 10
- 229910000881 Cu alloy Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 7
- 230000035515 penetration Effects 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Description
本発明のその他の観点によれば、絶縁層と、該絶縁層上に設けられた、半導体素子が搭載される半導体素子搭載用パッドと、前記半導体素子が搭載される半導体素子搭載領域よりも外側に形成された、電子部品が搭載される電子部品搭載用パッドとを有する配線基板本体と、前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に接着され、前記半導体素子搭載領域を露出する半導体素子搭載用貫通部と前記電子部品搭載用パッドを露出する電子部品搭載用貫通部とを有するスティフナーと、を備えた配線基板の製造方法であって、前記電子部品搭載用パッドに前記電子部品を搭載する電子部品搭載工程と、該電子部品搭載工程の後に、接着剤を介して前記スティフナーを前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に密着させて、余分な接着剤を前記電子部品搭載用貫通部内にはみ出させる接着工程と、を含むことを特徴とする配線基板の製造方法が提供される。
図10は、本発明の第1の実施の形態に係る配線基板の断面図であり、図11は、図10に示す配線基板の平面図である。図11では、図10に示すはんだ17の図示を省略する。
図31は、本発明の第2の実施の形態に係る配線基板の断面図であり、図32は、図31に示す配線基板の平面図である。図31及び図32において、第1の実施の形態の配線基板10と同一構成部分には同一符号を付す。また、図32では、図31に示すはんだ17の図示を省略する。
図39は、本発明の第3の実施の形態に係る配線基板の断面図であり、図40は、図39に示す配線基板の平面図である。図39及び図40において、第1の実施の形態の配線基板10と同一構成部分には同一符号を付す。また、図40では、図39に示すはんだ17の図示を省略する。
図49は、本発明の第4の実施の形態に係る配線基板の断面図であり、図50は、図49に示す配線基板の平面図である。図49及び図50において、第3の実施の形態の配線基板110と同一構成部分には同一符号を付す。また、図50では、図49に示すはんだ17の図示を省略する。
11,111 配線基板本体
12,61,71,91,101,114,151 スティフナー
12A,72 半導体素子搭載用貫通部
12B,61A 側壁
13 接着剤
14 半導体素子
15 電極パッド
16 内部接続端子
17 はんだ
18 実装基板
19,35 パッド
20 外部接続端子
21,121 半導体素子搭載用パッド
21A,118A,121A,122A 搭載面
21B,22A,22B,26A,35A 面
22,26 絶縁層
23,27 ビア
25,117 配線パターン
28 外部接続用パッド
28A 端子配設面
31 ソルダーレジスト層
31A,33,38,45A 開口部
36,123 配線
41,63,75 切り欠き部
43 支持体
43A 上面
45 めっき用レジストパターン
50,130 基板
55,67,80,95,132,155 スティフナー母材
55A,67A,92,102 貫通部
74 収容部
112 電子部品
118,122 電子部品搭載用パッド
125,141,152 電子部品搭載用貫通部
A 半導体素子搭載領域
B,F 領域
C,G 距離
D 配線基板本体形成領域
E 切断位置
W1−1,W1−2,W2−1,W2−2,W3−1,W3−2,W4−1,W4−2,W5−1,W5−2,W6−1,W6−2 幅
Claims (10)
- 半導体素子が搭載される半導体素子搭載用パッドと、前記半導体素子搭載用パッドが設けられる絶縁層と、前記半導体素子が搭載される半導体素子搭載領域とを有する配線基板本体と、
前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に接着され、前記半導体素子搭載領域を露出する半導体素子搭載用貫通部を有するスティフナーと、を備えた配線基板であって、
前記スティフナーに前記半導体素子搭載領域よりも外側に位置する部分の前記絶縁層の面を露出する貫通部が設けられ、
前記貫通部は、前記スティフナーの前記配線基板本体の各辺に対応する部分ごとに、複数設けられ、かつ、
前記貫通部の平面視における形状は、長方形において短辺が略半円となる形状であり、前記形状の長辺は、前記半導体素子搭載領域の1つの辺と対向するように設けられることを特徴とする配線基板。 - 前記配線基板本体は、前記絶縁層に設けられ、電子部品が搭載される電子部品搭載用パッドを有し、
前記スティフナーに、前記電子部品が搭載される領域に対応する部分の前記絶縁層の面を露出する電子部品搭載用貫通部を設けたことを特徴とする請求項1記載の配線基板。 - 前記貫通部と前記電子部品搭載用貫通部とを一体的に構成したことを特徴とする請求項2記載の配線基板。
- 前記半導体素子搭載用貫通部は、前記半導体素子を収容する収容部と、前記収容部の側壁に対応する部分のスティフナーに設けられ、前記絶縁層の面を露出する他の切り欠き部とを有することを特徴とする請求項1ないし3のうち、いずれか一項記載の配線基板。
- 半導体素子が搭載される半導体素子搭載用パッドと、前記半導体素子搭載用パッドが設けられる絶縁層と、前記半導体素子が搭載される半導体素子搭載領域とを有する配線基板本体と、
前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に接着され、前記半導体素子搭載領域を露出する半導体素子搭載用貫通部を有するスティフナーと、を備えた配線基板の製造方法であって、
複数の前記配線基板本体が隣接するように配置され、前記複数の配線基板本体が一体的に構成された基板を形成する基板形成工程と、
前記半導体素子搭載領域に対応する部分の前記基板を露出する前記半導体素子搭載用貫通部と、前記半導体素子搭載領域よりも外側に位置する部分の前記絶縁層の面を露出する貫通部とを備え、複数の前記スティフナーの母材となるスティフナー母材を形成するスティフナー母材形成工程と、
接着剤により、前記基板に設けられた前記絶縁層の面に前記スティフナー母材を接着する接着工程と、
前記接着工程後に、前記基板及び前記スティフナー母材を切断して、前記複数の配線基板本体及び前記複数のスティフナーを個片化する切断工程と、を含むことを特徴とする配線基板の製造方法。 - 前記貫通部は、前記配線基板本体の外周部に対応する部分の前記絶縁層の面から隣り合う他の前記配線基板本体の外周部に対応する部分の前記絶縁層の面に亘る領域の前記絶縁層の面を露出するように形成することを特徴とする請求項5記載の配線基板の製造方法。
- 前記スティフナー母材形成工程では、前記半導体素子搭載用貫通部及び前記貫通部を同時に形成することを特徴とする請求項5又は6に記載の配線基板の製造方法。
- 前記基板は、前記絶縁層に設けられ、電子部品が搭載される電子部品搭載用パッドを有し、
前記スティフナー母材は、前記電子部品搭載用パッドが形成される領域に対応する部分の前記絶縁層の面を露出する電子部品搭載用貫通部を備え、
前記スティフナー母材形成工程では、前記電子部品搭載用貫通部と前記半導体素子搭載用貫通部及び前記貫通部とを同時に形成することを特徴とする請求項5又は6記載の配線基板の製造方法。 - 前記接着工程の前に、前記電子部品を前記電子部品搭載用パッドに搭載する電子部品搭載工程を設けたことを特徴とする請求項8記載の配線基板の製造方法。
- 絶縁層と、該絶縁層上に設けられた、半導体素子が搭載される半導体素子搭載用パッドと、前記半導体素子が搭載される半導体素子搭載領域よりも外側に形成された、電子部品が搭載される電子部品搭載用パッドとを有する配線基板本体と、
前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に接着され、前記半導体素子搭載領域を露出する半導体素子搭載用貫通部と前記電子部品搭載用パッドを露出する電子部品搭載用貫通部とを有するスティフナーと、を備えた配線基板の製造方法であって、
前記電子部品搭載用パッドに前記電子部品を搭載する電子部品搭載工程と、
該電子部品搭載工程の後に、接着剤を介して前記スティフナーを前記半導体素子搭載用パッドが形成された側の前記絶縁層の面に密着させて、余分な接着剤を前記電子部品搭載用貫通部内にはみ出させる接着工程と、を含むことを特徴とする配線基板の製造方法。
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