JP2012069739A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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Abstract
【解決手段】本配線基板の製造方法は、配線層11,13,15,17と絶縁層12,14,16,18を積層し、半導体チップ搭載領域が設けられた第1主面及び前記第1主面の反対面である第2主面を備えた基板本体10を作製する第1工程と、前記第1主面に、前記半導体チップ搭載領域を露出する開口部22yを備えた補強部材22を固着する第2工程と、前記第2工程の後、前記第2主面に設けられた接続パッドに導電材19を介してリードピン20を接合する第3工程と、を有する。
【選択図】図4
Description
始めに、本実施の形態に係る配線基板の構造について説明する。図4は、本実施の形態に係る配線基板を例示する断面図である。図5は、本実施の形態に係る配線基板を例示する底面図である。なお、図4は、図5のA−A線に沿う断面を示している。
続いて、本実施の形態に係る配線基板の製造方法について説明する。図6〜図14は、本実施の形態に係る配線基板の製造工程を例示する図である。
変形例では、前述の実施の形態とは異なる配線基板の製造方法を例示する。図17及び図18は、本実施の形態の変形例に係る配線基板の製造工程を例示する図である。
2 半導体パッケージ
10 基板本体
11 第1配線層
11a 第1層
11b 第2層
12 第1絶縁層
12x 第1ビアホール
13 第2配線層
14 第2絶縁層
14x 第2ビアホール
15 第3配線層
16 第3絶縁層
16x 第3ビアホール
17 第4配線層
18 第4絶縁層
18x、22x、22y 開口部
19、23 接合部
20 リードピン
21 接着層
22 補強部材
24 電子部品
25 バンプ
30 支持体
31 治具
40 半導体チップ
41 アンダーフィル樹脂
42 蓋部
Claims (10)
- 配線層と絶縁層を積層し、半導体チップ搭載領域が設けられた第1主面及び前記第1主面の反対面である第2主面を備えた基板本体を作製する第1工程と、
前記第1主面に、前記半導体チップ搭載領域を露出する開口部を備えた補強部材を固着する第2工程と、
前記第2工程の後、前記第2主面に設けられた接続パッドに導電材を介してリードピンを接合する第3工程と、を有することを特徴とする配線基板の製造方法。 - 前記第1工程と前記第2工程との間に、前記半導体チップ搭載領域に設けられた接続パッド上に導電材を形成する第4工程を更に有することを特徴とする請求項1記載の配線基板の製造方法。
- 前記第1工程では、支持体上に複数の前記基板本体を一体的に構成した基板を作製して、その後前記支持体を除去し、
前記第1工程と前記第4工程との間に、前記基板を、それぞれが複数の前記基板本体を含む複数の集合体に分割し、
前記第4工程では、前記集合体毎に、前記半導体チップ搭載領域に設けられた前記接続パッド上に前記導電材を形成することを特徴とする請求項2記載の配線基板の製造方法。 - 前記第2工程では、前記集合体に含まれる各前記基板本体の前記第1主面に、それぞれ前記半導体チップ搭載領域を露出する開口部を備えた前記補強部材を固着し、
前記第2工程と前記第3工程との間に、前記補強部材が固着された各前記基板本体を、隣接する前記補強部材間で切断して個片化することを特徴とする請求項3記載の配線基板の製造方法。 - 前記第2工程より前に、前記集合体に含まれる各前記基板本体を個片化し、
前記第2工程では、個片化された各前記基板本体の前記第1主面に、それぞれ前記半導体チップ搭載領域を露出する開口部を備えた前記補強部材を固着することを特徴とする請求項3記載の配線基板の製造方法。 - 前記第2工程において、前記第1主面にシリコーン系の接着剤を介して前記補強部材を固着することを特徴とする請求項1乃至5の何れか一項記載の配線基板の製造方法。
- 前記第2工程よりも後に、前記シリコーン系の接着剤から発生するガスにより前記第1主面に付着したシリコーンを除去するプラズマ洗浄工程を更に有することを特徴とする請求項6記載の配線基板の製造方法。
- 前記補強部材の厚さは、前記基板本体の厚さの2倍以上であることを特徴とする請求項1乃至7の何れか一項記載の配線基板の製造方法。
- 前記補強部材は、CrとNiを主成分とするステンレス鋼であることを特徴とする請求項1乃至8の何れか一項記載の配線基板の製造方法。
- 前記補強部材は、電子部品を露出する他の開口部を更に備え、
前記第1主面の前記他の開口部に対応する位置に前記電子部品を実装する工程を更に有する請求項1乃至9の何れか一項記載の配線基板の製造方法。
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JP2010213333A JP2012069739A (ja) | 2010-09-24 | 2010-09-24 | 配線基板の製造方法 |
US13/233,076 US8479385B2 (en) | 2010-09-24 | 2011-09-15 | Method of producing wiring substrate |
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JP2010213333A JP2012069739A (ja) | 2010-09-24 | 2010-09-24 | 配線基板の製造方法 |
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US8952540B2 (en) * | 2011-06-30 | 2015-02-10 | Intel Corporation | In situ-built pin-grid arrays for coreless substrates, and methods of making same |
IN2014CN02652A (ja) * | 2011-10-21 | 2015-06-26 | Koninkl Philips Nv | |
JP2014229761A (ja) * | 2013-05-23 | 2014-12-08 | 株式会社東芝 | 電子機器 |
US10168524B2 (en) * | 2016-08-10 | 2019-01-01 | Kla-Tencor Corporation | Optical measurement of bump hieght |
US10359613B2 (en) * | 2016-08-10 | 2019-07-23 | Kla-Tencor Corporation | Optical measurement of step size and plated metal thickness |
WO2018093379A1 (en) * | 2016-11-18 | 2018-05-24 | Intel Corporation | Package with wall-side capacitors |
TWI595812B (zh) * | 2016-11-30 | 2017-08-11 | 欣興電子股份有限公司 | 線路板結構及其製作方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179092A (ja) * | 2001-12-10 | 2003-06-27 | Nitto Denko Corp | 半導体装置の製造方法及びそれに用いるワイヤボンディング装置 |
JP2003309215A (ja) * | 2002-02-15 | 2003-10-31 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2009081356A (ja) * | 2007-09-27 | 2009-04-16 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び配線基板 |
JP2009117703A (ja) * | 2007-11-08 | 2009-05-28 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP2009194086A (ja) * | 2008-02-13 | 2009-08-27 | Denso Corp | 半導体装置の製造方法 |
JP2010040709A (ja) * | 2008-08-04 | 2010-02-18 | Shinko Electric Ind Co Ltd | 基板の製造方法 |
JP2010080808A (ja) * | 2008-09-29 | 2010-04-08 | Ngk Spark Plug Co Ltd | 補強材付き配線基板の製造方法 |
JP2010141159A (ja) * | 2008-12-12 | 2010-06-24 | Denso Corp | 電子装置 |
JP2010192545A (ja) * | 2009-02-16 | 2010-09-02 | Ngk Spark Plug Co Ltd | 補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4617730A (en) * | 1984-08-13 | 1986-10-21 | International Business Machines Corporation | Method of fabricating a chip interposer |
JP2000243869A (ja) | 1999-02-18 | 2000-09-08 | Ngk Spark Plug Co Ltd | 配線基板 |
EP1990831A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
JP4194408B2 (ja) | 2003-04-03 | 2008-12-10 | 日本特殊陶業株式会社 | 補強材付き基板、半導体素子と補強材と基板とからなる配線基板 |
-
2010
- 2010-09-24 JP JP2010213333A patent/JP2012069739A/ja active Pending
-
2011
- 2011-09-15 US US13/233,076 patent/US8479385B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179092A (ja) * | 2001-12-10 | 2003-06-27 | Nitto Denko Corp | 半導体装置の製造方法及びそれに用いるワイヤボンディング装置 |
JP2003309215A (ja) * | 2002-02-15 | 2003-10-31 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2009081356A (ja) * | 2007-09-27 | 2009-04-16 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び配線基板 |
JP2009117703A (ja) * | 2007-11-08 | 2009-05-28 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP2009194086A (ja) * | 2008-02-13 | 2009-08-27 | Denso Corp | 半導体装置の製造方法 |
JP2010040709A (ja) * | 2008-08-04 | 2010-02-18 | Shinko Electric Ind Co Ltd | 基板の製造方法 |
JP2010080808A (ja) * | 2008-09-29 | 2010-04-08 | Ngk Spark Plug Co Ltd | 補強材付き配線基板の製造方法 |
JP2010141159A (ja) * | 2008-12-12 | 2010-06-24 | Denso Corp | 電子装置 |
JP2010192545A (ja) * | 2009-02-16 | 2010-09-02 | Ngk Spark Plug Co Ltd | 補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板 |
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