JP4717523B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP4717523B2 JP4717523B2 JP2005172294A JP2005172294A JP4717523B2 JP 4717523 B2 JP4717523 B2 JP 4717523B2 JP 2005172294 A JP2005172294 A JP 2005172294A JP 2005172294 A JP2005172294 A JP 2005172294A JP 4717523 B2 JP4717523 B2 JP 4717523B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- bonding
- area
- probe
- circuit region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20756—Diameter ranges larger or equal to 60 microns less than 70 microns
Description
基板上に、内部回路が形成された内部回路領域と、前記内部回路領域の外側に設けられたI/O回路領域とを備えた半導体装置であって、
前記I/O回路領域の外側の端辺をまたぐように配置された電極パッドを有し、
前記電極パッドにおいて、前記I/O回路領域の前記端辺より内側の領域がプローブ検査が行われるプローブエリアとされ、前記I/O回路領域の前記端辺より外側の領域がボンディングワイヤが接続されるボンディングエリアとされており、
前記電極パッドの前記プローブエリアの下にトランジスタが形成され、前記ボンディングエリアの下にトランジスタ及び配線が形成されていない半導体装置である。
これにより、I/O回路領域の外側にボンディングすることができるため、半導体装置の損傷を防ぐことができる。よって、歩留まりを向上することができ、生産性を向上することができる。
上記の本発明の半導体装置の製造方法であって、
前記I/O回路領域の前記端辺をまたぐように前記電極パッドを設ける工程(1)と、
前記電極パッドの前記プローブエリアにプローブを当接させて検査を行う工程(2)と、
前記電極パッドの前記ボンディングエリアにワイヤボンディングする工程(3)とを有するものである。
これにより、I/O回路領域の外側にボンディングすることができるため、半導体装置の損傷を防ぐことができる。よって、歩留まりを向上することができ、生産性を向上することができる。
5 プローブエリア、6 ボンディングエリア、7 最上層絶縁膜、
9 I/O回路領域の端辺、11 スクライブライン、12 基板、
13 トランジスタ構成部、14 層間絶縁膜、15 配線構成部、
21 テストプローブ、22 ボンディングワイヤ、23 プローブ痕、
100 半導体ウエハ
Claims (6)
- 基板上に、内部回路が形成された内部回路領域と、前記内部回路領域の外側に設けられたI/O回路領域とを備えた半導体装置であって、
前記I/O回路領域の外側の端辺をまたぐように配置された電極パッドを有し、
前記電極パッドにおいて、前記I/O回路領域の前記端辺より内側の領域がプローブ検査が行われるプローブエリアとされ、前記I/O回路領域の前記端辺より外側の領域がボンディングワイヤが接続されるボンディングエリアとされており、
前記電極パッドの前記プローブエリアの下にトランジスタが形成され、前記ボンディングエリアの下にトランジスタ及び配線が形成されていない半導体装置。 - 前記I/O回路領域の前記端辺の外側において前記電極パッドにワイヤボンディングされている請求項1に記載の半導体装置。
- 前記I/O回路領域の前記端辺の内側において前記電極パッドにプローブ痕が形成されている請求項1又は2に記載の半導体装置。
- 前記基板上において前記電極パッドの前記ボンディングエリアの下には絶縁膜のみが形成された請求項1〜3のいずれかに記載の半導体装置。
- 請求項1〜4のいずれかに記載の半導体装置の製造方法であって、
前記I/O回路領域の前記端辺をまたぐように前記電極パッドを設ける工程(1)と、
前記電極パッドの前記プローブエリアにプローブを当接させて検査を行う工程(2)と、
前記電極パッドの前記ボンディングエリアにワイヤボンディングする工程(3)とを有する半導体装置の製造方法。 - 前記半導体装置は前記I/O回路領域が光学的に識別できるものであり、
工程(2)及び/又は工程(3)においては、
電極パッドの前記プローブエリアの下に前記トランジスタが形成され、前記ボンディングエリアの下にトランジスタ及び配線が形成されていないことを判別して、前記プローブエリア内か前記ボンディングエリア内かの位置検出を行う請求項5に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005172294A JP4717523B2 (ja) | 2005-06-13 | 2005-06-13 | 半導体装置及びその製造方法 |
US11/450,388 US7701072B2 (en) | 2005-06-13 | 2006-06-12 | Semiconductor device and manufacturing method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005172294A JP4717523B2 (ja) | 2005-06-13 | 2005-06-13 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006351588A JP2006351588A (ja) | 2006-12-28 |
JP4717523B2 true JP4717523B2 (ja) | 2011-07-06 |
Family
ID=37523431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005172294A Expired - Fee Related JP4717523B2 (ja) | 2005-06-13 | 2005-06-13 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7701072B2 (ja) |
JP (1) | JP4717523B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4519571B2 (ja) * | 2004-08-26 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその検査方法と検査装置並びに半導体装置の製造方法 |
JP5111878B2 (ja) * | 2007-01-31 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5160295B2 (ja) * | 2008-04-30 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及び検査方法 |
JP2013206905A (ja) | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP6231279B2 (ja) * | 2013-01-22 | 2017-11-15 | 株式会社デンソー | 半導体装置 |
JP5732493B2 (ja) * | 2013-07-29 | 2015-06-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6305754B2 (ja) * | 2013-12-20 | 2018-04-04 | 東京特殊電線株式会社 | コンタクトプローブユニット |
EP3422393A4 (en) * | 2016-02-23 | 2020-02-05 | Renesas Electronics Corporation | SEMICONDUCTOR COMPONENT AND PRODUCTION METHOD THEREFOR |
CN117199054A (zh) * | 2022-06-01 | 2023-12-08 | 长鑫存储技术有限公司 | 封装结构及其制作方法、半导体器件 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04167449A (ja) * | 1990-10-31 | 1992-06-15 | Nec Corp | 半導体装置 |
JP2002076075A (ja) * | 2000-08-24 | 2002-03-15 | Nec Corp | 半導体集積回路 |
JP2002329742A (ja) * | 2001-05-07 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置 |
JP2003218114A (ja) * | 2002-01-22 | 2003-07-31 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003282574A (ja) * | 2003-02-26 | 2003-10-03 | Mitsubishi Electric Corp | 半導体装置 |
WO2004093191A1 (ja) * | 2003-04-11 | 2004-10-28 | Fujitsu Limited | 半導体装置 |
JP2004356453A (ja) * | 2003-05-30 | 2004-12-16 | Trecenti Technologies Inc | 半導体装置およびその製造方法 |
JP2005079432A (ja) * | 2003-09-02 | 2005-03-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7091613B1 (en) * | 2003-10-31 | 2006-08-15 | Altera Corporation | Elongated bonding pad for wire bonding and sort probing |
JP4242336B2 (ja) * | 2004-02-05 | 2009-03-25 | パナソニック株式会社 | 半導体装置 |
KR100585142B1 (ko) * | 2004-05-04 | 2006-05-30 | 삼성전자주식회사 | 범프 테스트를 위한 플립 칩 반도체 패키지 및 그 제조방법 |
-
2005
- 2005-06-13 JP JP2005172294A patent/JP4717523B2/ja not_active Expired - Fee Related
-
2006
- 2006-06-12 US US11/450,388 patent/US7701072B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04167449A (ja) * | 1990-10-31 | 1992-06-15 | Nec Corp | 半導体装置 |
JP2002076075A (ja) * | 2000-08-24 | 2002-03-15 | Nec Corp | 半導体集積回路 |
JP2002329742A (ja) * | 2001-05-07 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置 |
JP2003218114A (ja) * | 2002-01-22 | 2003-07-31 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003282574A (ja) * | 2003-02-26 | 2003-10-03 | Mitsubishi Electric Corp | 半導体装置 |
WO2004093191A1 (ja) * | 2003-04-11 | 2004-10-28 | Fujitsu Limited | 半導体装置 |
JP2004356453A (ja) * | 2003-05-30 | 2004-12-16 | Trecenti Technologies Inc | 半導体装置およびその製造方法 |
JP2005079432A (ja) * | 2003-09-02 | 2005-03-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2006351588A (ja) | 2006-12-28 |
US7701072B2 (en) | 2010-04-20 |
US20060279001A1 (en) | 2006-12-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4717523B2 (ja) | 半導体装置及びその製造方法 | |
JP5486866B2 (ja) | 半導体装置の製造方法 | |
KR101121644B1 (ko) | 프로브 카드용 공간 변환기 및 공간 변환기의 복구 방법 | |
JP4761880B2 (ja) | 半導体装置 | |
US6784556B2 (en) | Design of interconnection pads with separated probing and wire bonding regions | |
JP2005159195A (ja) | 半導体装置 | |
KR100630756B1 (ko) | 개선된 패드 구조를 갖는 반도체 장치 | |
US8586983B2 (en) | Semiconductor chip embedded with a test circuit | |
US8482002B2 (en) | Semiconductor device including bonding pads and semiconductor package including the semiconductor device | |
KR102195561B1 (ko) | 전기적 접속 장치 | |
KR20070081640A (ko) | 반도체 소자 및 그 제조 방법 | |
US6972583B2 (en) | Method for testing electrical characteristics of bumps | |
JP2010098046A (ja) | プローブカードおよび半導体装置の製造方法 | |
US20080303177A1 (en) | Bonding pad structure | |
JP2001110858A (ja) | 半導体装置およびその製造方法、ならびにバーンイン装置 | |
US20130187158A1 (en) | Semiconductor device | |
JP2010225678A (ja) | 半導体装置及びその製造方法 | |
JP2007067008A (ja) | 半導体検査のプローブ方法 | |
JP4728628B2 (ja) | 半導体装置 | |
JP4877465B2 (ja) | 半導体装置、半導体装置の検査方法、半導体ウェハ | |
KR20130016765A (ko) | 반도체 소자의 전기특성 테스트용 박막 저항체 구비 전기적 연결 장치 및 그의 제작방법 | |
KR19990018725A (ko) | 반도체 웨이퍼 및 그의 전기적 특성 검사 방법 | |
KR20100099516A (ko) | 검사용 구조물 | |
KR20070056670A (ko) | 반도체 웨이퍼 검사용 본딩 패드 | |
JP2009076808A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080213 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100129 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100622 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100715 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100914 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101110 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101207 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110131 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110329 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110330 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140408 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |