CN112420819A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN112420819A
CN112420819A CN202010830288.0A CN202010830288A CN112420819A CN 112420819 A CN112420819 A CN 112420819A CN 202010830288 A CN202010830288 A CN 202010830288A CN 112420819 A CN112420819 A CN 112420819A
Authority
CN
China
Prior art keywords
semiconductor device
lower electrode
semiconductor substrate
electrode
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010830288.0A
Other languages
English (en)
Inventor
曾根田真也
新田哲也
原田健司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN112420819A publication Critical patent/CN112420819A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0218—Structure of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02185—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05013—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10254—Diamond [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本公开涉及半导体装置，其目的在于得到能够抑制由镀敷导致的对半导体基板的损伤并实现高可靠性的半导体装置。本公开涉及的半导体装置具有：半导体基板；下部电极，其设置于该半导体基板之上；绝缘膜，其设置于该半导体基板之上，将该下部电极包围；以及镀敷电极，其设置于该下部电极之上，该镀敷电极在上表面具有凸部，该凸部具有：第1部分，其在与该半导体基板的上表面平行的第1方向延伸；以及第2部分，其在与该半导体基板的该上表面平行且与该第1方向交叉的第2方向延伸，该镀敷电极比该绝缘膜薄。

Description

半导体装置
技术领域
本公开涉及半导体装置。
背景技术
在专利文献1中公开了半导体装置，该半导体装置具有：半导体基板，其形成有半导体元件；以及第1电极层，其设置于半导体基板之上，与半导体元件电连接。该半导体装置还具有：保护绝缘膜，其层叠于第1电极层的上表面的一部分；以及第2电极层，其是横跨第1电极层和保护绝缘膜这两者而层叠的。构成第2电极层的材料比构成第1电极层的材料机械强度高。在第1电极层的上表面设置有槽部。另外，在第2电极层的下表面设置有凸出至槽部内的凸出部。
专利文献1：日本特开2017-050358号公报
在如专利文献1所示那样的构造中，想到通过镀敷而形成第2电极层。此时，在槽部处，镀敷处理液到达半导体基板，半导体基板有可能受到损伤。
发明内容
本公开就是为了解决上述课题而提出的，其目的在于，得到能够抑制由镀敷导致的对半导体基板的损伤并实现高可靠性的半导体装置。
本公开涉及的半导体装置具有：半导体基板；下部电极，其设置于该半导体基板之上；绝缘膜，其设置于该半导体基板之上，将该下部电极包围；以及镀敷电极，其设置于该下部电极之上，该镀敷电极在上表面具有凸部，该凸部具有：第1部分，其在与该半导体基板的上表面平行的第1方向延伸；以及第2部分，其在与该半导体基板的该上表面平行且与该第1方向交叉的第2方向延伸，该镀敷电极比该绝缘膜薄。
本公开涉及的半导体装置具有：半导体基板；下部电极，其设置于该半导体基板之上；绝缘膜，其设置于该半导体基板之上，将该下部电极包围，形成芯片的外缘；以及镀敷电极，其设置于该下部电极之上，该镀敷电极在上表面具有凸部，该凸部具有：第1部分，其在该芯片的外周部在与该半导体基板的上表面平行的第1方向延伸；以及第2部分，其在该芯片的外周部在与该半导体基板的该上表面平行且与该第1方向交叉的第2方向延伸。
本公开涉及的半导体装置具有：半导体基板；下部电极，其设置于该半导体基板之上；绝缘膜，其设置于该半导体基板之上，将该下部电极包围；以及镀敷电极，其设置于该下部电极之上，该镀敷电极在上表面具有十字型的凸部。
发明的效果
就本公开涉及的半导体装置而言，在下部电极没有槽部，因此能够抑制由镀敷导致的对半导体基板的损伤。另外，由于通过凸部提高了半导体装置的机械强度，因此能够实现半导体装置的高可靠性。
附图说明
图1是实施方式1涉及的半导体装置的剖视图。
图2是实施方式1涉及的半导体装置的俯视图。
图3是表示在实施方式1涉及的半导体装置设置有焊料的状态的剖视图。
图4是实施方式1的第1变形例涉及的半导体装置的剖视图。
图5是实施方式1的第2变形例涉及的半导体装置的俯视图。
图6是实施方式1的第3变形例涉及的半导体装置的俯视图。
图7是实施方式2涉及的半导体装置的剖视图。
图8是实施方式3涉及的半导体装置的剖视图。
标号的说明
10半导体基板，12下部电极，13凸起部，14绝缘膜，16镀敷电极，17凸部，17a第1部分，17b第2部分，18背面电极，100、200、300、400、500、600半导体装置，513凸起部，613凸起部，613a第1凸起部，613b第2凸起部
具体实施方式
参照附图，对本公开的实施方式涉及的半导体装置进行说明。对相同或对应的结构要素标注相同标号，有时省略重复说明。
实施方式1.
图1是实施方式1涉及的半导体装置100的剖视图。半导体装置100具有半导体基板10、下部电极12、绝缘膜14、镀敷电极16、背面电极18。半导体装置100例如为电力半导体装置。电力半导体装置例如为MOSFET(Metal-Oxide-Semiconductor Field-EffectTransistor)。电力半导体装置也可以是IGBT(Insulated Gate Bipolar Transistor)或二极管。
下部电极12设置于半导体基板10之上。下部电极12被作为图案设置于半导体基板10的上表面。下部电极12是用于在半导体装置100流过主电流的电极。下部电极12例如为MOSFET的源极电极、IGBT的发射极电极或二极管的阳极电极。下部电极12例如为包含Al、Si、Cu等的Al合金。下部电极12的厚度例如为0.1μm～6μm。
凸起部13设置于下部电极12的上表面。凸起部13为下部电极12的一部分。凸起部13由与下部电极12相同的材料形成。通过将下部电极12的一部分形成得比其它部分厚而设置凸起部13。凸起部13的高度T1例如为0.5μm～10μm，宽度w1例如为0.5μm～100μm。
绝缘膜14设置于半导体基板10之上。绝缘膜14将半导体基板10的外周部覆盖。绝缘膜14将下部电极12包围。绝缘膜14的一部分攀至下部电极12之上。绝缘膜14将下部电极12的端部覆盖。绝缘膜14是对下部电极12及半导体基板10进行保护的保护绝缘膜。绝缘膜14例如由聚酰亚胺形成。
绝缘膜14在中央部具有开口部。在开口部处通过镀敷技术设置镀敷电极16。镀敷电极16设置于下部电极12之上。镀敷电极16整体与绝缘膜14相比设置于内侧。镀敷电极16为焊料接合用金属膜，例如是通过化学镀生长的Ni-P膜。Ni-P膜是含有百分之几的P的金属膜。镀敷电极16也可以由比下部电极12机械强度高的材料形成。
通常，在将金属膜和焊料接合后的状态下，金属膜和焊料的合金化得以发展。由此，有时金属膜的厚度会减少。因此，对镀敷电极16进行设计，以使得在半导体装置100的使用条件下，镀敷电极16不会由于合金化而消失。由此，能够确保焊料接合部的可靠性。特别地，当在严酷的热应力环境下使用半导体装置100的情况下，以镀敷电极16不消失的程度，将镀敷电极16设计得厚即可。在该情况下，与溅射技术相比，优选通过镀敷技术形成镀敷电极16。镀敷电极16的厚度T3例如为0.1μm～10μm。另外，镀敷电极16没有形成在绝缘膜14之上，比绝缘膜14薄。
镀敷电极16在上表面具有凸部17。镀敷电极16将下部电极12的凸起部13覆盖。由此，凸起部13的形状反映在镀敷电极16的表面，在镀敷电极16形成凸部17。因此，在俯视观察时凸部17设置于与凸起部13重叠的位置。凸部17沿凸起部13在剖视中形成为U字状。凸部17的高度T2例如为0.5μm～10μm。凸部17的宽度w2比凸起部13的宽度w1宽例如1μm～20μm。
凸部17处的镀敷电极16的厚度T2+T3比镀敷电极16中的凸部17之外的平面部的厚度T3厚。因此，凸部17与平面部相比垂直方向的机械刚性高。另外，镀敷电极16比绝缘膜14薄。特别地，镀敷电极16中的凸部17之外的平面部比在绝缘膜14的下部电极12之上设置的部分薄。即，T3<T4。如果T3>T4，则存在镀敷电极16在绝缘膜14之上也形成得薄的风险。在该情况下，镀敷电极16中的位于绝缘膜14之上的部分具有与T3和T4的差相等的厚度。此时，在镀敷电极16局部地形成刚性低的部位。在本实施方式中，通过设为T3<T4能够对在镀敷电极16形成刚性低的部位进行抑制。
背面电极18设置于与半导体基板10的上表面相对的面即背面。背面电极18是用于在半导体装置100流过主电流的电极。背面电极18例如为MOSFET的漏极电极、IGBT的集电极(collector)电极(electrode)、二极管的阴极电极。背面电极18例如为包含Al、Ti、Ni、Au、Cu等的层叠膜。背面电极18的厚度例如为0.1μm～10μm。
图2是实施方式1涉及的半导体装置100的俯视图。此外，图1是通过用图2所示的A-B直线切割半导体装置100而得到的。半导体装置100在俯视观察时为四边形。绝缘膜14形成芯片的外缘。镀敷电极16将绝缘膜14的开口部填充。镀敷电极16在俯视观察时为四边形。凸部17设置于镀敷电极16的外周部。凸部17沿镀敷电极16的四个边延伸。
凸部17具有：第1部分17a，其在芯片的外周部在第1方向延伸；以及第2部分17b，其在芯片的外周部在第2方向延伸。第1方向为与半导体基板10的上表面平行的方向。第1方向为图2中的X方向。第2方向为与半导体基板10的上表面平行且与第1方向交叉的方向。第2方向为图2中的Y方向。
图3是表示在实施方式1涉及的半导体装置100设置有焊料20的状态的剖视图。焊料20设置于镀敷电极16之上。焊料20以包含凸部17的方式将镀敷电极16覆盖。焊料20也可以将镀敷电极16整体覆盖。另外，焊料20与绝缘膜14相比设置于内侧，没有形成于绝缘膜14之上。焊料20的端部与镀敷电极16的端部对齐。
在本实施方式中，通过焊料20将外部电极和半导体装置100的电极直接接合。由此，能够降低电阻并且进行大电流的通电。
下面，对本实施方式的效果进行说明。通常，在下部电极之上设置有镀敷电极的构造中，有时在下部电极形成槽部。此时，形成没有下部电极的部位、或下部电极薄的部位。在这样的构造中，如果通过镀敷技术形成镀敷电极，则存在在槽部处镀敷处理液到达半导体基板的风险。由此，有可能使半导体基板受到损伤，损害半导体装置的可靠性。相对于此，由于在本实施方式的下部电极12没有槽部，因此具有下述效果，即，抑制由镀敷处理导致的对半导体基板10的损伤。
另外，通过在镀敷电极16设置凸部17，能够提高镀敷电极16的垂直方向的机械强度。特别地，通过使凸部17在第1方向及第2方向延伸，凸部17作为梁起作用。因此，能够提高镀敷电极16的刚性。由此，即使将镀敷电极16设得薄，也能够确保镀敷电极16相对于垂直方向的应力的强度。另外，通过由凸部17提高半导体装置100的机械强度，能够提高半导体装置100的可靠性。
图4是实施方式1的第1变形例涉及的半导体装置200的剖视图。下部电极12及镀敷电极16也可以分割为多个部分。在图4中，下部电极12及镀敷电极16各自被绝缘膜14分割。
图5是实施方式1的第2变形例涉及的半导体装置300的俯视图。就半导体装置300而言，凸部17的形状与半导体装置100不同。就半导体装置300而言，凸部17的第1部分17a和第2部分17b是分离的。在该情况下也能够得到与半导体装置100相同的效果。
图6是实施方式1的第3变形例涉及的半导体装置400的俯视图。就半导体装置100而言，凸部17沿绝缘膜14设置于镀敷电极16的外周部。凸部17的配置并不限于此。如图6所示，凸部17也可以为十字型。就半导体装置400而言，第1部分17a和第2部分17b在芯片的中央部交叉。
就半导体装置400而言，能够增强芯片的中央部。此外，如半导体装置100、300所示，呈如下倾向：在与镀敷电极16的端部越近的部位配置凸部17，镀敷电极16相对于垂直方向的应力的机械强度越高。
如上所述，凸部17至少具有在第1方向延伸的第1部分17a、在与第1方向交叉的第2方向延伸的第2部分17b即可。另外，第1方向和第2方向也可以相对于芯片的边倾斜。例如，第1部分17a和第2部分17b也可以沿芯片的对角线延伸。
另外，芯片、绝缘膜14及镀敷电极16的形状并不限于图2所示，例如也可以是正方形、长方形、多边形等。
另外，为了机械强度的提高，优选凸部17的高度T2比规定值大。优选凸部17的高度T2例如大于或等于1μm。
另外，在本实施方式中，利用凸起部13的凹凸在镀敷电极16形成了凸部17。并不限于此，只要能够在镀敷电极16形成凸部17，则也可以不设置凸起部13。在该情况下也能够得到与本实施方式相同的效果。在该情况下，在半导体基板10的上表面形成平坦的下部电极12。接着，在下部电极12的上表面，通过镀敷等设置成为镀敷电极16的平坦的金属膜。之后，也可以通过追加的加工工序，形成凸部17。
另外，在本实施方式中，将镀敷电极16设为与外部电极通过焊料20直接接合的金属膜。并不限于此，也可以将镀敷电极16用作导线接合或Ag接合用电极。在该情况下也能够得到与本实施方式相同的效果。
作为本实施方式的其它变形例，半导体基板10也可以由宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。半导体基板10也可以由硅形成。
这些变形能够适当应用于以下实施方式涉及的半导体装置。此外，由于与实施方式1的共通点较多，因此以与实施方式1的区别为中心对以下实施方式涉及的半导体装置进行说明。
实施方式2.
图7是实施方式2涉及的半导体装置500的剖视图。在本实施方式中，凸起部513由与下部电极12不同的材料形成。通过由凸起部513形成的台阶，在镀敷电极16形成凸部17。凸起部513既可以是绝缘膜，也可以是非绝缘膜。绝缘膜例如为氧化膜、硅氮化膜、聚酰亚胺。非绝缘膜例如为TiNi、Cu。在这样的情况下，也会得到与实施方式1相同的效果。
另外，凸起部513的宽度w1小于或等于镀敷电极16的厚度T3与凸起部513的厚度T5之间的差的2倍。通常，镀层在特定的材料之上生长。作为镀层的镀敷电极16在下部电极12之上生长。另外，在由与下部电极12不同的材料形成的凸起部513之上，镀层没有生长。
这里，镀层通常各向同性地生长。因此，能够从下部电极12和凸起部513的边界起仅在一定范围，在凸起部513的表面之上也形成镀层。具体而言，能够从下部电极12和凸起部513的边界起以镀敷电极16的厚度T3，在凸起部513的表面之上也形成镀敷。
因此，如果将凸起部513的宽度w1设为小于或等于镀敷电极16的厚度T3与凸起部513的厚度T5之间的差的2倍，则能够在凸起部513的整个上表面形成镀层。因此，在凸起部513由与下部电极12不同的材料形成的情况下，也能够通过镀敷电极16覆盖凸起部513。
实施方式3.
图8是实施方式3涉及的半导体装置600的剖视图。凸起部613具有第1凸起部613a和第2凸起部613b。第1凸起部613a为下部电极12的一部分，由与下部电极12相同的材料形成。第2凸起部613b设置于第1凸起部613a之上，由与下部电极12不同的材料形成。
接着，对凸起部613的制造方法进行说明。首先，在半导体基板10的上表面形成成为下部电极12的金属膜。接着，在金属膜的上表面形成成为第2凸起部613b的掩模层。接着，将掩模层图案化而形成第2凸起部613b。接着，沿第2凸起部613b对金属膜进行蚀刻，形成下部电极12及第1凸起部613a。
通常，凸部17越高，越能够提高镀敷电极16的垂直方向的机械强度。在本实施方式中，将用于形成第1凸起部613a的掩模以原状态残留，形成镀敷电极16。通过将第1凸起部613a和第2凸起部613b组合，能够将凸起部613形成得高。由此，能够将凸部17形成得高。因此，能够得到实施方式1的效果，并且提高镀敷电极16相对于垂直方向的应力的机械强度。
另外，能够将用于形成第1凸起部613a的掩模有效地用作第2凸起部613b。此外，在实施方式1中，也可以通过在对成为下部电极12的金属膜进行了蚀刻后，去除第2凸起部613b，从而形成凸起部13。
另外，与实施方式2相同地，第2凸起部613b的宽度w1也可以小于或等于镀敷电极16的厚度T3与第2凸起部613b的高度T5之间的差的2倍。由此，在第2凸起部613b由与下部电极12不同的材料形成的情况下，也能够通过镀敷电极16覆盖第2凸起部613b。
另外，在各实施方式中说明过的技术特征也可以适当地进行组合而使用。

Claims (17)

1.一种半导体装置，其特征在于，具有：
半导体基板；
下部电极，其设置于所述半导体基板之上；
绝缘膜，其设置于所述半导体基板之上，将所述下部电极包围；以及
金属膜，其由Ni-P形成，设置于所述下部电极之上，该金属膜在上表面具有凸部，
所述凸部具有：第1部分，其在与所述半导体基板的上表面平行的第1方向延伸；以及第2部分，其在与所述半导体基板的所述上表面平行且与所述第1方向交叉的第2方向延伸，
所述金属膜比所述绝缘膜薄。
2.根据权利要求1所述的半导体装置，其特征在于，
所述凸部沿所述绝缘膜设置于所述金属膜的外周部。
3.一种半导体装置，其特征在于，具有：
半导体基板；
下部电极，其设置于所述半导体基板之上；
绝缘膜，其设置于所述半导体基板之上，将所述下部电极包围，形成芯片的外缘；以及
金属膜，其由Ni-P形成，设置于所述下部电极之上，该金属膜在上表面具有凸部，
所述凸部具有：第1部分，其在所述芯片的外周部在与所述半导体基板的上表面平行的第1方向延伸；以及第2部分，其在所述芯片的外周部在与所述半导体基板的所述上表面平行且与所述第1方向交叉的第2方向延伸。
4.一种半导体装置，其特征在于，具有：
半导体基板；
下部电极，其设置于所述半导体基板之上；
绝缘膜，其设置于所述半导体基板之上，将所述下部电极包围；以及
金属膜，其由Ni-P形成，设置于所述下部电极之上，该金属膜在上表面具有十字型的凸部。
5.根据权利要求3或4所述的半导体装置，其特征在于，
所述金属膜比所述绝缘膜薄。
6.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
所述金属膜在俯视观察时为四边形，
所述凸部沿所述金属膜的四个边延伸。
7.根据权利要求1所述的半导体装置，其特征在于，
所述凸部为十字型。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
所述绝缘膜具有设置于所述下部电极之上的部分，
所述金属膜比所述绝缘膜的设置于所述下部电极之上的部分薄。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述金属膜整体与所述绝缘膜相比设置于内侧。
10.根据权利要求1至9中任一项所述的半导体装置，其特征在于，
在所述下部电极的上表面，在俯视观察时与所述凸部重叠的位置设置凸起部。
11.根据权利要求10所述的半导体装置，其特征在于，
所述凸起部为所述下部电极的一部分。
12.根据权利要求10所述的半导体装置，其特征在于，
所述凸起部由与所述下部电极不同的材料形成。
13.根据权利要求12所述的半导体装置，其特征在于，
所述凸起部的宽度小于或等于所述金属膜的厚度与所述凸起部的高度之间的差的2倍。
14.根据权利要求10所述的半导体装置，其特征在于，
所述凸起部具有：第1凸起部，其为所述下部电极的一部分；以及第2凸起部，其设置于所述第1凸起部之上，由与所述下部电极不同的材料形成。
15.根据权利要求14所述的半导体装置，其特征在于，
所述第2凸起部的宽度小于或等于所述金属膜的厚度与所述第2凸起部的高度之间的差的2倍。
16.根据权利要求1至15中任一项所述的半导体装置，其特征在于，
所述半导体基板由宽带隙半导体形成。
17.根据权利要求16所述的半导体装置，其特征在于，
所述宽带隙半导体为碳化硅、氮化镓类材料或金刚石。
CN202010830288.0A 2019-08-23 2020-08-18 半导体装置 Pending CN112420819A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019153085A JP7226186B2 (ja) 2019-08-23 2019-08-23 半導体装置
JP2019-153085 2019-08-23

Publications (1)

Publication Number Publication Date
CN112420819A true CN112420819A (zh) 2021-02-26

Family

ID=74495300

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010830288.0A Pending CN112420819A (zh) 2019-08-23 2020-08-18 半导体装置

Country Status (4)

Country Link
US (1) US11239329B2 (zh)
JP (1) JP7226186B2 (zh)
CN (1) CN112420819A (zh)
DE (1) DE102020120481A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314490B (zh) * 2021-05-27 2023-04-07 芯盟科技有限公司 半导体结构及半导体结构的形成方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140027A1 (en) * 2003-12-30 2005-06-30 Semiconductor Manufacturing International (Shanghai) Corporation Method and device for manufacturing bonding pads for chip scale packaging
CN1881572A (zh) * 2005-06-15 2006-12-20 三洋电机株式会社 半导体装置及其制造方法
JP2009111188A (ja) * 2007-10-30 2009-05-21 Denso Corp 半導体装置
CN101714538A (zh) * 2008-10-03 2010-05-26 三洋电机株式会社 半导体器件及其制造方法
US20160027746A1 (en) * 2014-07-28 2016-01-28 Infineon Technologies Ag Semiconductor Chip and Method for Forming a Chip Pad
US20170062340A1 (en) * 2015-08-31 2017-03-02 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20190067225A1 (en) * 2017-08-24 2019-02-28 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008027929A (ja) 2006-07-18 2008-02-07 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法および検査方法
JP2009200067A (ja) 2008-02-19 2009-09-03 Panasonic Corp 半導体チップおよび半導体装置
JP5350022B2 (ja) 2009-03-04 2013-11-27 パナソニック株式会社 半導体装置、及び該半導体装置を備えた実装体
KR101534682B1 (ko) * 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
US8492891B2 (en) * 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
JP6111907B2 (ja) 2013-07-05 2017-04-12 三菱電機株式会社 半導体装置の製造方法
JP2015050347A (ja) * 2013-09-02 2015-03-16 トヨタ自動車株式会社 半導体装置及びその製造方法
JP6094533B2 (ja) 2014-06-09 2017-03-15 トヨタ自動車株式会社 半導体装置
JP6895834B2 (ja) 2017-07-21 2021-06-30 三菱電機株式会社 パワーデバイス

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140027A1 (en) * 2003-12-30 2005-06-30 Semiconductor Manufacturing International (Shanghai) Corporation Method and device for manufacturing bonding pads for chip scale packaging
CN1881572A (zh) * 2005-06-15 2006-12-20 三洋电机株式会社 半导体装置及其制造方法
JP2009111188A (ja) * 2007-10-30 2009-05-21 Denso Corp 半導体装置
CN101714538A (zh) * 2008-10-03 2010-05-26 三洋电机株式会社 半导体器件及其制造方法
US20160027746A1 (en) * 2014-07-28 2016-01-28 Infineon Technologies Ag Semiconductor Chip and Method for Forming a Chip Pad
US20170062340A1 (en) * 2015-08-31 2017-03-02 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US20190067225A1 (en) * 2017-08-24 2019-02-28 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
DE102020120481A1 (de) 2021-02-25
US11239329B2 (en) 2022-02-01
JP2021034557A (ja) 2021-03-01
JP7226186B2 (ja) 2023-02-21
US20210057529A1 (en) 2021-02-25

Similar Documents

Publication Publication Date Title
JP5004800B2 (ja) 炭化ケイ素デバイス用のはんだ付け可能上部金属
JP6250864B2 (ja) パワー半導体装置
US20130307156A1 (en) Reliable Area Joints for Power Semiconductors
JP6264230B2 (ja) 半導体装置
US20210028085A1 (en) Semiconductor device
KR20080096483A (ko) 반도체 장치
JP2007049045A (ja) 半導体発光素子およびこれを備えた半導体装置
US12002914B2 (en) Semiconductor light-emitting element and semiconductor light-emitting device
WO2020032204A1 (ja) ＳｉＣ半導体装置
CN112420819A (zh) 半导体装置
US8803278B2 (en) Semiconductor device
JP2018074059A (ja) 半導体装置
JP2020202313A (ja) 半導体装置および半導体装置の製造方法
WO2021261102A1 (ja) 電子部品
US20230101079A1 (en) Semiconductor device
US20230105834A1 (en) Semiconductor device
JP2019165111A (ja) 半導体装置
JP6630410B1 (ja) ＳｉＣ半導体装置
KR20060044670A (ko) 반도체 장치
JP6939888B2 (ja) 半導体装置、半導体装置の製造方法
JP2006100530A (ja) 半導体装置とその製造方法
KR20070045359A (ko) 적어도 하나의 테스트 컨택트 구조를 포함하는 칩과 이를포함한 웨이퍼
KR20230135764A (ko) 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
JP2021150587A (ja) 半導体装置
CN111696943A (zh) 具有带有堤状构造的管芯焊盘的半导体器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination