US20190067225A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US20190067225A1 US20190067225A1 US16/029,334 US201816029334A US2019067225A1 US 20190067225 A1 US20190067225 A1 US 20190067225A1 US 201816029334 A US201816029334 A US 201816029334A US 2019067225 A1 US2019067225 A1 US 2019067225A1
- Authority
- US
- United States
- Prior art keywords
- conductive film
- film
- semiconductor device
- semiconductor substrate
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 123
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000013078 crystal Substances 0.000 claims abstract description 56
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 36
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 36
- 238000007747 plating Methods 0.000 claims abstract description 34
- 238000011282 treatment Methods 0.000 claims description 54
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 31
- 238000004544 sputter deposition Methods 0.000 claims description 25
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 238000004140 cleaning Methods 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 238000007772 electroless plating Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 description 18
- 239000010949 copper Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000011701 zinc Substances 0.000 description 14
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 239000007864 aqueous solution Substances 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 11
- 229910052725 zinc Inorganic materials 0.000 description 11
- 229910018104 Ni-P Inorganic materials 0.000 description 10
- 229910018536 Ni—P Inorganic materials 0.000 description 10
- 239000012535 impurity Substances 0.000 description 10
- 108091006146 Channels Proteins 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 238000005238 degreasing Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000002050 diffraction method Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910001453 nickel ion Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
- H01L2224/03614—Physical or chemical etching by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
- H01L2224/0362—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04034—Bonding areas specifically adapted for strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05084—Four-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
- H01L2224/05583—Three-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/40247—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
- H01L2224/40499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84399—Material
- H01L2224/84498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/84499—Material of the matrix
- H01L2224/8459—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84399—Material
- H01L2224/84498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/84598—Fillers
- H01L2224/84599—Base material
- H01L2224/846—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/053—Oxides composed of metals from groups of the periodic table
- H01L2924/0543—13th Group
- H01L2924/05432—Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/206—Length ranges
- H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, which can be applied to, for example, the semiconductor device having an OPM electrode and the method of manufacturing the same.
- Japanese Unexamined Patent Application Publication No. 2000-235964 discloses a technology of forming an OPM electrode made of a nickel film and a gold film on the pad electrode containing mainly aluminum using electroless plating.
- Japanese Unexamined Patent Application Publication No. 2007-227412 discloses an IGBT module including a diode and an IGBT (Insulated Gate Bipolar Transistor) coupled in antiparallel with each other.
- IGBT Insulated Gate Bipolar Transistor
- the OPM electrode made of the plating film of nickel or the like is formed on the pad electrode containing mainly aluminum as described in Japanese Unexamined Patent Application Publication No. 2000-235964, the OPM electrode is easily removed from the pad electrode, thereby reducing reliability of the semiconductor device.
- the semiconductor device includes: a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film; and a plating film that is formed over the second conductive film and serves to be coupled to an external connection terminal.
- FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment
- FIG. 2 is a s cross-sectional view of the semiconductor device during a manufacturing process that follows FIG. 1 ;
- FIG. 3 is a s cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 2 ;
- FIG. 4 is a s cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 3 ;
- FIG. 5 is a s cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 4 ;
- FIG. 6 shows a process flow indicative of the manufacturing process of the semiconductor device that follows FIG. 5 ;
- FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 6 ;
- FIG. 8 is a schematic view of the semiconductor device according to the first embodiment and an IGBT in a modularized form
- FIG. 9 is a plan view showing the semiconductor device of FIG. 8 in a mounted state
- FIG. 10 is a cross-sectional view taken along a line A-A in FIG. 9 ;
- FIG. 11 is a cross-sectional view of a main part of the semiconductor device of a third embodiment
- FIG. 12 is a cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 11 ;
- FIG. 13 is a cross-sectional view of the semiconductor device during the manufacturing process that follows FIG. 12 ;
- FIG. 14 is a plan view showing the semiconductor device of FIG. 13 in the mounted state.
- This embodiment presents a diode DI used as a super fast recover diode (Fast Recovery Diode), for example, as a semiconductor element mounted on the semiconductor device.
- a diode DI used as a super fast recover diode (Fast Recovery Diode)
- Fast Recovery Diode super fast recover diode
- a substrate is prepared first that has n-type conductivity and includes a semiconductor such as silicon.
- the substrate configures a drift region DR of the diode DI.
- An impurity region AN having p-type conductivity is then formed near a surface of the drift region DR by ion implantation or the like.
- the impurity region AN configures an anode region of the diode DI.
- This embodiment describes a configuration including the drift region DR and the anode region AN as a semiconductor substrate SUB.
- a crystal surface on a surface of the drift region DR is a (001) surface. Because a silicon substrate having the (001) surface is commonly used, the manufacturing cost can be suppressed compared with preparing a substrate having another crystal surface. Moreover, the crystal surface on the surface of the anode region AN formed over the surface of the drift region DR is also the (001) surface. That is, the crystal surface on the surface of the semiconductor substrate SUB is the (001) surface.
- FIG. 1 shows a state in which an insulating film IF 1 is formed over the surface of the semiconductor substrate SUB as a thin natural oxide film or a foreign matter.
- the surface of the semiconductor substrate SUB is subjected to, for example, a reactive dry etching treatment using a gas containing carbon tetrafluoride (CF4) and a wet etching treatment using a cleaning liquid containing hydrogen fluoride (HF) as a cleaning treatment.
- the cleaning treatment removes the insulating film IF 1 deposited over the surface of the semiconductor substrate SUB including the anode region AN.
- the cleaning treatment is performed primarily for reducing forward resistance of the diode DI, and thus for reducing contact resistance between the semiconductor substrate SUB and a pad electrode PD that will be formed later.
- a conductive film AL 1 containing mainly aluminum and doped with a small amount of silicon is formed over the semiconductor substrate SUB by, for example, sputtering.
- the thickness of the conductive film AL 1 is about 2,500 nm.
- Temperature of formation of the conductive film AL 1 by sputtering is about room temperature (23° C.) to 200° C., and more preferably about 150° C. It is to be noted that the reason why the conductive film AL 1 is doped with a small amount of silicon is to prevent an interface between the conductive film AL 1 and the semiconductor substrate SUB from having a spike shape.
- the conductive film AL 1 is an aluminum film
- forming the aluminum film by the above-mentioned sputtering makes the crystal structure of the aluminum film a face-centered cubic structure (FCC: Face-Centered Cubic), and therefore the conductive film AL 1 has the (111) surface or close-packed surface on almost all of its surfaces if not affected by its base.
- the conductive film AL 1 according to the embodiment is formed taking over the crystal surface of the semiconductor substrate SUB, and thus the crystal surface on the surface of the conductive film AL 1 is the (001) surface. This is because the step of forming the conductive film AL 1 is performed immediately after the cleaning treatment illustrated in FIG.
- a barrier metal film including titanium nitride having higher resistance than that of the conductive film AL 1 is not formed between the conductive film AL 1 and the semiconductor substrate SUB but the conductive film AL 1 is formed directly over the semiconductor substrate SUB.
- the (001) surface is equivalent to the (100) surface and a (010) surface as a crystal surface. Therefore, the (001) surface of the conductive film AL 1 according to the embodiment is treated as a crystal surface equivalent to the (100) surface disclosed in “zincate Treatment and Electroless Ni—P Plating on Al Single-Crystal Surface,” Journal of The Surface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997.
- the cleaning treatment is performed as in this embodiment, the thin natural oxide film or the foreign matter is present over the surface of the semiconductor substrate SUB. If the conductive film AL 1 is formed in such a state, the conductive film AL 1 can hardly take over the crystal surface on the surface of the semiconductor substrate SUB, making it easier for the crystal surface other than the (001) surface to be formed over the surface of the conductive film AL 1 . However, to reduce resistance of the diode DI, it is desirable to perform the cleaning treatment to remove the thin natural oxide film or the foreign matter. This may make the crystal surface on the surface of the conductive film AL 1 configuring the pad electrode PD the (001) surface.
- the inventors have come up with a method of reducing resistance of the diode DI and making the crystal surface on the surface of the pad electrode PD different from the (001) surface by performing the cleaning treatment.
- FIG. 4 is a cross-sectional view of the method of manufacturing the semiconductor device that follows FIG. 3 .
- the crystal surface on the surface of the conductive film AL 1 is the (001) surface.
- an insulating film BIF is formed over the conductive film AL 1 first.
- the insulating film BIF is formed by exposing the surface of the conductive film AL 1 to an atmosphere containing oxygen, e.g. by once taking out the semiconductor substrate SUB from a sputtering device and exposing the semiconductor substrate SUB to the atmospheric air at room temperature (23° C.). That is, the insulating film BIF includes an oxide of a material that forms the conductive film ALL such as aluminum oxide.
- the thickness of the insulating film BIF ranges from 0.5 nm to 4.0, and more preferably from 1.0 nm to 3.0 nm.
- a conductive film AL 2 containing mainly aluminum, for example, and also doped with silicon is formed over the insulating film BIF by the sputtering, for example.
- the thickness of the conductive film AL 2 is about 2,500 nm.
- the temperature for forming the conductive film AL 2 by the sputtering is between about the room temperature (23° C.) and 200° C., and more preferably about 150° C.
- the conductive film AL 2 does not take over the (001) surface that is the crystal surface on the surface of the conductive film AL 1 and thus it can be formed with the crystal surface different from the (001) surface.
- the crystal surface on the surface of the conductive film AL 2 is predominantly the (111) surface. Specifically, 90% or more of the surface area of the conductive film AL 2 is the (111) surface. In this manner, even if the (110) surface remains on a part of the conductive film AL 2 after the initial stage of film formation, because particles on the (110) surface are covered by the particles of the (111) surface that configures the most part of the conductive film AL 2 in the subsequent stage of film formation by the sputtering, the most part of the surface of the conductive film AL 2 eventually becomes the (111) surface.
- 90% or more of the surface of the conductive film AL 2 is finally the (111) surface, and more preferably 99% or more of the surface of the conductive film AL 2 is finally the (111) surface.
- the insulating film BIF is an orientation blocking film serving as a film for blocking orientation of crystal.
- the pad electrode PD may have three or more layers by further forming an insulating film such as the insulating film BIF over the conductive film AL 2 and subsequently forming a conductive film such as the conductive film AL 2 thereon.
- the thickness of the insulating film BIF is no less than 0.5 nm and no more than 4.0 nm, and more preferably no less than 1.0 nm and no more than 3.0 nm. This is the thickness range for the conductive film AL 2 not to take over the crystal surface of the conductive film AL 1 and for sufficient conductivity to be guaranteed between the conductive film AL 2 and the conductive film ALL That is, because voltage of millions of volts is applied to such a diode DI as described in this embodiment, the insulating film BIF having the thickness as described above does not affect properties of the diode DI.
- the pad electrode PD containing mainly the conductive film AL 2 and the conductive film AL 1 is formed by patterning the conductive film AL 2 , the insulating film BIF, and the conductive film AL 1 using photolithography and dry etching.
- An insulating film IF 2 including an organic resin such as photosensitive polyimide is then formed over the semiconductor substrate SUB so as to cover the pad electrode PD. Then, an opening OP 1 exposing a part of the pad electrode PD is formed over the insulating film IF 2 by selectively exposing the insulating film IF 2 to light. It is to be noted that a material for the insulating film IF 2 may be inorganic insulating film such as silicon oxide or silicon nitride instead of the organic resin described above.
- FIG. 6 illustrates a process flow to the step at which a conductive layer OPM is formed as in FIG. 7 to be described later, showing a plasma etching treatment S 11 and plating treatments S 12 to S 20 to be performed on the pad electrode PD.
- the plating treatment is described to include surface treatments S 12 to S 14 , zincate treatments S 15 to S 17 , and electroless plating treatments S 18 to S 20 .
- a pure water cleaning treatment may be performed.
- the plasma etching treatment S 11 and the surface treatments S 12 to S 14 are performed on the surface of the pad electrode PD.
- the plasma etching treatment S 11 and the surface treatments S 12 to S 14 are performed to remove the natural oxide film, the grease, the foreign matter, and the like present over the surface of the pad electrode PD.
- the plasma etching treatment is performed first on the surface of the conductive film AL 2 using inert gas such as argon (Ar).
- inert gas such as argon (Ar).
- Ar argon
- the plating treatment is performed on the surface of the conductive film AL 2 in the order of surface treatments S 12 to S 14 , zincate treatments S 15 to S 17 , and electroless plating treatments S 18 to S 20 .
- the degreasing treatment is performed on the surface of the conductive film AL 2 using a weak alkaline aqueous solution containing sodium hydroxide or the like.
- the grease over the surface of the conductive film AL 2 and the natural oxide film over the surface of the conductive film AL 2 are primarily removed by the degreasing treatment.
- the etching treatment is performed using an alkaline aqueous solution containing, for example, copper (Cu).
- the etching treatment is performed to remove aluminum oxide present near the surface of the conductive film AL 2 , and it is effective where the conductive film AL 2 is made of aluminum doped with silicon as in this embodiment. That is, by dissolving aluminum oxide present near the surface of the conductive film AL 2 with the alkaline aqueous solution and substituting the aluminum surface with copper having a standard electrode potential higher than that of aluminum, it is possible to effectively reduce aluminum oxide present near the surface of the conductive film AL 2 .
- an acid cleaning is performed on the surface of the conductive film AL 2 using an aqueous solution containing, for example, nitric acid.
- the acid cleaning allows for the copper substituted at Step S 13 to be dissolved in the aqueous solution containing nitric acid and for removing copper from the surface of the conductive film AL 2 .
- Step S 15 in FIG. 6 a first zincate treatment is performed on the surface of the conductive film AL 2 .
- the acid cleaning is performed on the surface of the conductive film AL 2 .
- the aqueous solution containing nitric acid zinc particles deposited by the first zincate treatment is dissolved in the aqueous solution containing nitric acid. This treatment allows aluminum to appear uniformly on the surface of the conductive film AL 2 .
- a second zincate treatment is performed on the surface of the conductive film AL 2 .
- a dense and uniform Zn film can be formed by repeating the zincate treatment two times. This allows the plating film of nickel or the like that will be formed in the following step to be deposited uniformly.
- Steps S 18 to S 20 in FIG. 6 and in FIG. 7 the electroless plating treatment is performed on the surface of the pad electrode PD, thereby sequentially forming the conductive films PF 1 to PF 3 .
- the conductive film PF 1 containing mainly nickel (Ni) or the like is formed over the exposed surface of the pad electrode PD (surface of the conductive film AL 2 ) by electroless plating.
- the surface of the conductive film AL 2 is immersed in plating aqueous solution containing nickel ion or the like.
- the zinc particles deposited by the zincate treatment in FIG. 6 are dissolved into the plating aqueous solution.
- nickel is reduced and deposited by electrons emitted from the zinc particles.
- Steps S 19 and S 20 by sequentially forming the conductive film PF 2 containing mainly palladium (Pd) or the like and the conductive film PF 3 containing mainly gold (Au) over the conductive film PF 1 by electroless plating, the conductive layer OPM including a lamination of the plating films. Because the conductive film PF 2 and the conductive film PF 3 are formed over the conductive film PF 1 having highly uniform thickness, the conductive film PF 2 and the conductive film PF 3 are also formed with highly uniform thickness. Thus, it is possible to improve uniformity of thickness of the conductive layer OPM.
- the thickness of the conductive film PF 1 is about 1,000 to 4,000 nm
- the thickness of the conductive film PF 2 is about 100 to 400 nm
- the thickness of the conductive film PF 3 is about 30 to 200 nm.
- the conductive film PF 1 is a principal film of the conductive layer OPM, it is preferable to include a material having low sheet resistance.
- the conductive film PF 3 is provided mainly to improve adhesiveness with an external connection terminal TR, and it is preferable to include a material having higher adhesiveness to the external connection terminal TR than the conductive film PF 1 .
- the conductive film PF 2 is provided to prevent that the conductive film PF 1 be diffused over the surface of the conductive film PF 3 to corrode a boundary between the conductive film PF 1 and the conductive film PF 3 .
- the conductive layer OPM may be a lamination of the conductive film PF 1 and the conductive film PF 3 or a lamination of the conductive film PF 1 and the conductive film PF 2 .
- the conductive film PF 1 and the conductive film PF 2 may contain phosphorus (P).
- the conductive layer OPM including a plating film is formed over the pad electrode PD. It is to be noted that the conductive layer OPM configures an anode electrode of the diode DI.
- a cathode region CT and a back electrode BE are formed on the back side of the semiconductor substrate SUB.
- the back side of the semiconductor substrate SUB is polished to reduce the thickness of the semiconductor substrate SUB.
- an n-type impurity is introduced from the back side of the semiconductor substrate SUB using ion implantation to form the cathode region CT having a higher impurity concentration than that of the drift region DR.
- the introduced impurity is activated by heat treatment.
- metal films including nickel (Ni), titanium (Ti), gold (Au), for example, are deposited in this order from the side abutting the cathode region CT using sputtering, thereby forming a cathode electrode (back electrode) BE including these metal films.
- the semiconductor device according to the embodiment is manufactured in the above-mentioned steps.
- FIG. 8 is a schematic view showing one configuration in which a semiconductor wafer having the semiconductor device according to the embodiment formed thereon is diced into a chip CP 1 by a dicing step of a post-processing treatment and then the semiconductor element including the diode DI according to the embodiment and an IGBT is modularized.
- dimensions of configurations such as the conductive layer OPM are different from those described with reference to FIG. 7 .
- the chip CP 1 is the semiconductor device including the diode DI according to the embodiment formed thereon, and a chip CP 2 is the semiconductor device including the semiconductor element of IGBT formed thereon.
- the IGBT includes a configuration shown on the left side of FIG. 8 .
- a p-type base layer 2 is formed over the surface of the n-type semiconductor substrate that configures a drift region 1 .
- Formed over the surface of the base layer 2 is an n-type source layer 3 , and the base layer 2 and the source layer 3 are coupled commonly to an emitter electrode 6 including an aluminum film or the like.
- the base layer 2 arranged between the drift region 1 and the source layer 3 is a channel region, and a gate electrode 5 is formed over the channel region via a gate insulating film 4 .
- Formed over the back side of the drift region 1 are a buffer layer 7 doped with an n-type impurity, an emitter layer 8 doped with a p-type impurity, and a collector electrode 9 .
- the cathode electrode BE of the diode DI and the collector electrode 9 of the IGBT are electrically coupled to each other, and the anode electrode (conductive layer) OPM of the diode DI and the emitter electrode 6 of the IGBT are also electrically coupled to each other.
- FIGS. 9 and 10 show an example in which the chip CP 1 and the chip CP 2 configuring the IGBT shown in FIG. 8 are packaged.
- FIG. 10 is a cross-sectional view taken along line A-A in the plan view shown in FIG. 9 . It is to be noted that a sealing resin MR and a die pad DP depicted in FIG. 10 are omitted in FIG. 9 for better understanding of the shape of the external connection terminal TR. It is illustrated here that the chip CP 1 and the chip CP 2 are coupled in a single package using a clip including, for example, a copper sheet, as an example of the external connection terminal TR.
- a clip including, for example, a copper sheet, as an example of the external connection terminal TR.
- the chip CP 1 and the chip CP 2 are mounted over the die pad DP via a solder BP 1 .
- the die pad DP also serves as a power source potential terminal DT that supplies power source potential to the chip CP 1 and the chip CP 2 . That is, the cathode electrode BE of the chip CP 1 and the collector electrode 9 of the chip CP 2 are electrically coupled to the power source potential terminal DT (die pad DP) via the solder BP 1 .
- the external connection terminal TR is coupled to the CP 1 and the chip CP 2 via a solder BP 2 .
- the external connection terminal TR is electrically coupled to the ground potential terminal ST via a conductive adhesive or the like.
- the conductive layer OPM of the chip CP 1 is coupled to the solder BP 2 . That is, the anode electrode (conductive layer) OPM of the chip CP 1 and the emitter electrode 6 of the chip CP 2 are electrically coupled to the ground potential terminal ST via the solder BP 2 and the external connection terminal TR.
- the gate electrode 5 of the IGBT is coupled to another terminal via a bonding wire or the like other than the external connection terminal TR.
- the chip CP 1 and the chip CP 2 coupled to the die pad DP and the external connection terminal TR are sealed with the sealing resin MR. In this manner, the semiconductor device according to the embodiment is packaged.
- the external connection terminal TR may be a bonding wire including copper or gold.
- the external connection terminal TR may be a bonding wire including copper or gold.
- the semiconductor device that has a large area of the anode electrode (conductive layer) OPM of the diode DI and a large area of the emitter electrode 6 of the IGBT and that is to receive voltage of hundreds of volts as in the embodiment, it is desirable to use a copper clip having a large area to reduce resistance related to coupling to another chip. It is also possible to use sintered silver (Ag) instead of the solders BP 1 , BP 2 .
- the embodiment is characterized in that the crystal surface on the surface of the conductive film AL 2 is formed with the crystal surface different from that of the crystal surface on the surface of the conductive film AL 1 .
- the crystal surface on the surface of the pad electrode PD is formed with the (001) surface
- the first and second zincate treatments in FIG. 6 there is a problem that the size of the deposited zinc particle is so large that the deposition of the plating film such as nickel formed by the electroless plating cannot be performed uniformly and the surface of the plating film becomes rough.
- moisture or the like enters the interface between the pad electrode PD and the conductive layer OPM facilitating separation in this portion, which reduces reliability of the semiconductor device.
- appearance abnormality is observed on the surface of the plating film.
- the conductive film AL 2 formed over the insulating film BIF is not affected by the crystal surface on the surface of the conductive film ALL allowing the he crystal surface on the surface of the conductive film AL 2 to have the (111) surface.
- the size of each zinc particle deposited during the first and second zincate treatments shown in FIG. 6 is uniform and small, the deposite from the conductive film PF 1 including nickel and the like formed by electroless plating can be formed relatively uniformly. This allows for a configuration in which separation is hardly caused on the interface between the pad electrode PD and the conductive layer OPM, thereby improving reliability of the semiconductor device. Furthermore, appearance abnormality on the surface of the plating film can be minimized.
- the cleaning treatment is performed on the semiconductor substrate SUB serving as the base of the conductive film AL 1 to keep the surface of the semiconductor substrate SUB clean.
- the conductive film AL 1 tends to take over the (001) surface that is the crystal surface on the surface of the semiconductor substrate SUB, the crystal surface on the surface of the conductive film AL 1 also tends to have the (001) surface.
- the crystal surface on the surface of the conductive film AL 2 may have the (111) surface, which achieves the structure in which separation is hardly caused on the interface between the pad electrode PD and the conductive layer OPM. That is, using the technique of the embodiment can improve performance of the semiconductor device and also improve reliability of the semiconductor device.
- the insulating film BIF is formed over the conductive film AL 1 by once taking out the semiconductor substrate SUB from the sputtering device and exposing it to the atmospheric air, as shown in FIG. 4 .
- the semiconductor substrate SUB is transferred to another chamber without taking it out of the sputtering device, an oxygen-containing gas is introduced into the sputtering device, and the surface of the conductive film AL 1 is exposed to oxygen atmosphere, thereby forming the insulating film BIF.
- oxygen atmosphere is performed in oxygen gas atmosphere at room temperature.
- the oxidation treatment maybe combined with heat treatment, and may be conducted by emitting plasma using oxygen gas.
- the conductive film AL 2 is formed over the insulating film BIF by the sputtering as in the first embodiment, without taking out the semiconductor substrate SUB from the sputtering device.
- the conductive film AL 2 is configured using the same material as that of the conductive film ALL the material containing mainly, for example, aluminum doped with silicon.
- the conductive film AL 2 is configured using a material different from that of the conductive film AL 1 , the material containing mainly, for example, aluminum doped with copper. That is, the element doped into the conductive film AL 2 is different from the element doped into the conductive film AL 1 .
- the conductive film AL 1 is in direct contact with the diode DI and made of aluminum film doped with silicon for the purpose of reducing spike shapes on the interface between the semiconductor substrate SUB and the conductive film AL 1 .
- the material of the conductive film AL 2 may be other material than the aluminum film doped with silicon.
- the copper-doped aluminum film exhibits better electromigration than the silicon-doped aluminum film, the copper doped aluminum film is used as the conductive film AL 2 of the second modification.
- the etching treatment at Step S 13 in FIG. 6 can be omitted. That is, the aluminum oxide present over the surface of the conductive film AL 2 is substituted using the aqueous solution containing copper having high standard electrode potential at Step S 13 described above.
- copper is already included in the conductive film AL 2 . Therefore, it is possible to more effectively remove the oxide over the surface of the conductive film AL 2 by the degreasing treatment using the alkaline aqueous solution at Step S 12 or the subsequent zincate treatment.
- the zincate treatment further facilitates deposition of the zinc particles, and the electroless plating treatment further facilitates substitute and deposite nickel.
- Step S 13 shown in FIG. 6 can be omitted in the second modification, the method of manufacturing the semiconductor device can be simplified.
- the conductive film AL 2 may be made of a material containing mainly aluminum and doped with copper and silicon.
- the insulating film BIF is formed over the conductive film AL 1 to differentiate the crystal surface of the conductive film AL 2 from that of the conductive film ALL
- amorphous film formed over the conductive film AL 1 is an amorphous film that is a conductive film made of a material different from that of the conductive film AL 1 and in an amorphous state over the conductive film AL 1 .
- the amorphous film a replacement from the insulating film BIF in the first embodiment and therefore it is not presented in the drawings.
- the reference symbol “BIF” indicated in FIG. 4 or the like designates the amorphous film.
- Such an amorphous film is formed by sputtering or CVD and configured by a film containing mainly, for example, tantalum, titanium nitride, or tungsten nitride. Moreover, the thickness of the amorphous film is between 0.5 nm and 4.0 nm, and more preferably between 1.0 nm and 3.0 nm.
- the above-mentioned material can exist in the amorphous state as long as it has such a small film thickness. Because the amorphous film is in the amorphous state, it does not have a specific crystal surface. Therefore, when the conductive film AL 2 is formed over the amorphous film by sputtering, the conductive film AL 2 does not take over the crystal surface of the conductive film AL 1 but grows mainly based on the (111) surface, as in the first embodiment. That is, the amorphous film is an orientation blocking film serving as a film for blocking orientation of crystal, like the insulating film BIF. Thus, the semiconductor device according to the second embodiment can provide the same effect as the first embodiment.
- the conductive film AL 1 and the conductive film AL 2 used in the first embodiment are applied to wiring of a power MOS.
- a case is described in which the conductive film AL 1 and the conductive film AL 2 are applied to a source electrode SPD.
- a structure of the semiconductor device according to the third embodiment and a method of manufacturing the same are described below with reference to FIGS. 11 to 13 .
- FIG. 11 shows an n-type power MOS including an n-type gate electrode GE, a gate insulating film GI, an insulating film IF 3 that covers the gate electrode GE, a p-type channel region CH, an n-type source region SR, an n-type drift region NV serving as a drain region, and an n-type substrate SB.
- the substrate SB having n-type conductivity and including semiconductor such as silicon is prepared first.
- a drift region NV (impurity region NV) having n-type conductivity and impurity concentration lower than that of the substrate SB is formed over the substrate SB by epitaxy or the like.
- explanation is given assuming a structure including the substrate SB and the drift region NV as the semiconductor substrate SUB.
- a gate insulating film GI including silicon oxide is formed over the side face and the bottom face of the groove.
- the gate electrode GE including polycrystalline silicon or the like is formed over the gate insulating film GI so as to fill the groove.
- the channel region CH having p-type conductivity is formed on top of the drift region NV by ion implantation.
- a boundary between the channel region CH and the drift region NV is located above the bottom face of the gate electrode GE.
- the source region SR (impurity region SR) having n-type conductivity is then formed on top of the channel region CH by ion implantation.
- the insulating film IF 3 is then selectively formed over a portion of the source region SR and over the gate electrode GE. Next, by performing dry etching on a portion exposed on the insulating film IF 3 , an opening OP 2 reaching the channel region CH through the source region SR is formed.
- the n-type power MOS is manufactured as described above.
- the conductive film AL 1 and the conductive film AL 2 serving as the source electrode SPD are formed over the insulating film IF 3 .
- a barrier metal film BM including titanium tungsten (TiW), titanium nitride (TiN), or the like is formed in the opening OP 2 and over the insulating film IF 3 .
- the conductive film AL 1 containing mainly aluminum, for example is formed over the barrier metal film BM so as to fill the opening OP 2 . This allows the conductive film AL 1 serving as a part of the source electrode SPD to be electrically coupled to the source region SR and the channel region CH.
- the barrier metal film BM is formed between the semiconductor substrate SUB and the conductive film AL 1 unlike the first embodiment and the second embodiment described above. Accordingly, the conductive film AL 1 may use a material mainly containing aluminum and doped with silicon or a material mainly containing aluminum and doped with copper.
- the conductive film AL 1 is formed by sputtering, and the maximum temperature in the forming process ranges from 250 to 400 degrees, which is higher than that in the first embodiment. This is to prevent a void formed in the conductive film AL 1 when the conductive film AL 1 is filled in the opening OP 2 .
- the formation of the conductive film AL 1 may be performed in two steps including an initial film formation performed at a low temperature ranging from room temperature (23° C.) to 200° C. and a second step performed at a high temperature ranging from 250 to 400° C. for filling. Moreover, a step is made between the surface of the conductive film AL 1 located on top of the opening OP 2 and the surface of the conductive film AL 1 located on top of the gate electrode GE.
- the conductive layer OPM is formed over the source electrode SPD in a later step.
- the size of the aluminum particle tends to be larger compared with an aluminum film formed at relatively low temperature as in the first embodiment. That is, the crystal surface on the surface of the conductive film AL 1 tends to have not only the (111) surface but also the (001) surface. Thus, if the conductive layer OPM is formed over the conductive film AL 1 , separation would easily occur between the source electrode SPD and the conductive layer OPM as in the first embodiment.
- the thin insulating film BIF is formed over the conductive film AL 1 and then the conductive film AL 2 is formed over the conductive film AL 1 as in the first embodiment.
- This can differentiate the crystal surface on the surface of the conductive film AL 2 from the crystal surface on the surface of the conductive film AL 1 .
- the method of forming the insulating film BIF and the conductive film AL 2 is the same as that in the first embodiment. Accordingly, the crystal surface on the surface of the conductive film AL 2 in this embodiment is also the (111) surface.
- the temperature of formation of the conductive film AL 2 is lower than that of the conductive film ALL and it is about room temperature (23° C.) to 200° C., for example, and more preferably about 150° C. That is, because the conductive film AL 1 is formed at relatively high temperature, the flatness of its surface is improved whereas the possibility of generating the (001) surface having a large particle size also increases. Therefore, generation of the (001) surface having the large particle size can be suppressed by forming the conductive film AL 2 at relatively low temperature.
- the area ratio of the (111) surface on the surface of the conductive film AL 2 is higher than that of the (111) surface on the surface of the conductive film AL 1
- the source electrode SPD shown in FIG. 12 is formed by patterning the conductive film AL 2 , the insulating film BIF, the conductive film ALL and the barrier metal film BM using photolithography and dry etching. It is to be noted that a gate pad electrode GPD to be coupled to the gate electrode GE of the power MOS is also formed at this time (not shown in the figure).
- the insulating film IF 2 having the opening OP 1 is formed over the conductive film AL 2 so as to expose a portion of the conductive film AL 2 serving as a portion of the source electrode SPD. It is to be noted that the method of forming the insulating film IF 2 and its material are the same as those in the first embodiment.
- the conductive layer OPM is formed over the conductive film AL 2 in the opening OP 1 .
- the back side of the substrate SB is polished to form the drain electrode (back electrode) BE.
- the semiconductor device of the third embodiment is manufactured according to the above-mentioned steps.
- the third embodiment it is possible to suppress the separation between the source electrode SPD and the conductive layer OPM and to obtain the same effect as the first embodiment.
- FIG. 14 shows a view of a chip CP 3 including the power MOS according to the third embodiment formed thereon in the packaged state.
- the external connection terminal TR to be coupled to the conductive layer OPM a case of using a clip made of a copper sheet is described.
- the chip CP 3 is mounted over the die pad DP via a solder BP 3 .
- the die pad DP also serves as the power source potential terminal DT that supplies power source potential to the chip CP 3 . That is, the drain electrode BE of the chip CP 3 is electrically coupled to the power source potential terminal DT (die pad DP) via the solder BP 3 .
- the external connection terminal TR is coupled to the chip CP 3 via a solder BP 4 .
- the external connection terminal TR is electrically coupled to the ground potential terminal ST via a solder BP 5 .
- the conductive layer OPM of the chip CP 3 is coupled to the solder BP 4 . That is, the source electrode SPD of the chip CP 3 is electrically coupled to the ground potential terminal ST via the conductive layer OPM, the solder BP 4 , the external connection terminal TR, and the solder BP 5 .
- the gate pad electrode GPD of the power MOS is coupled to a gate potential terminal GT via a bonding wire WB.
- Such a chip CP 3 is sealed with the sealing resin MR. In this manner, the semiconductor device according to the third embodiment is packaged.
- the conductive film AL 1 and the conductive film AL 2 are employed as the source electrode SPD of the power MOS in the third embodiment, it is also possible to employ the conductive film AL 1 and the conductive film AL 2 as the emitter electrode of the IGBT. Furthermore, when applied to the IGBT, the channel region CH of the power MOS is a base region.
- the chip CP 3 described in the third embodiment maybe employed instead of the chip CP 2 shown in FIGS. 8 to 10 of the first embodiment.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemically Coating (AREA)
Abstract
Description
- The disclosure of Japanese Patent Application No. 2017-161043 filed on Aug. 24, 2017 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
- The present invention relates to a semiconductor device and a method of manufacturing the same, which can be applied to, for example, the semiconductor device having an OPM electrode and the method of manufacturing the same.
- Recently, based on demands for improving reliability of semiconductor device and so on, there is proposed a structure obtained by forming a pad electrode containing mainly aluminum on a semiconductor substrate, forming a conductive layer called an OPM (Over Pad Metal) electrode on the pad electrode, and coupling an external coupling terminal such as a clip or a bonding wire to the OPM electrode.
- For example, Japanese Unexamined Patent Application Publication No. 2000-235964 discloses a technology of forming an OPM electrode made of a nickel film and a gold film on the pad electrode containing mainly aluminum using electroless plating.
- Moreover, Japanese Unexamined Patent Application Publication No. 2007-227412 discloses an IGBT module including a diode and an IGBT (Insulated Gate Bipolar Transistor) coupled in antiparallel with each other.
- Furthermore, “Zincate Treatment and Electroless Ni—P Plating on Al Single-Crystal Surface,” Journal of The Surface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997 discloses a technology of obtaining a (100) surface, a (110) surface, and a (111) surface from single-crystal aluminum (Al) and then performing a zincate treatment using an aqueous solution containing zinc (Zn) and an electroless Ni—P plating treatment on these surfaces. The above-mentioned document describes study on how the differences among the crystal surfaces affects the size of deposited Zn particles and growth of an Ni—P plating film.
- As disclosed in “Zincate Treatment and Electroless Ni—P Plating on Al Single-Crystal Surface,” Journal of The Surface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997, when zincate treatment is performed on the (100) surface of aluminum, there is a problem that relatively large Zn particles are deposited and the thickness of the Ni—P plating film formed thereon may not be uniform. Because the surface of the Ni—P plating film is rough and does not present a dense film, moisture may easily enter from the outside of the semiconductor device. This may cause such a problem that corrosion occurs to an interface between the Ni—P plating film and an aluminum film, which increases possibility that the Ni—P plating film would be separated from the aluminum film. In such a case, if the OPM electrode made of the plating film of nickel or the like is formed on the pad electrode containing mainly aluminum as described in Japanese Unexamined Patent Application Publication No. 2000-235964, the OPM electrode is easily removed from the pad electrode, thereby reducing reliability of the semiconductor device.
- Other problems and novel features will become apparent from the following description and accompanying drawings.
- Outline of representative one of embodiments disclosed herein is briefly described below.
- According to a semiconductor device and a method of manufacturing the same of one embodiment, the semiconductor device includes: a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film; and a plating film that is formed over the second conductive film and serves to be coupled to an external connection terminal.
- According to one embodiment, it is possible to improve reliability of the semiconductor device.
-
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment; -
FIG. 2 is a s cross-sectional view of the semiconductor device during a manufacturing process that followsFIG. 1 ; -
FIG. 3 is a s cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 2 ; -
FIG. 4 is a s cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 3 ; -
FIG. 5 is a s cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 4 ; -
FIG. 6 shows a process flow indicative of the manufacturing process of the semiconductor device that followsFIG. 5 ; -
FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 6 ; -
FIG. 8 is a schematic view of the semiconductor device according to the first embodiment and an IGBT in a modularized form; -
FIG. 9 is a plan view showing the semiconductor device ofFIG. 8 in a mounted state; -
FIG. 10 is a cross-sectional view taken along a line A-A inFIG. 9 ; -
FIG. 11 is a cross-sectional view of a main part of the semiconductor device of a third embodiment; -
FIG. 12 is a cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 11 ; -
FIG. 13 is a cross-sectional view of the semiconductor device during the manufacturing process that followsFIG. 12 ; and -
FIG. 14 is a plan view showing the semiconductor device ofFIG. 13 in the mounted state. - In the following embodiments, although explanation is given with respect to each section or each embodiment as needed for convenience, the sections or embodiments are not irrelevant to each other but one may be a part or all of a modification, detailed description, or supplementary explanation of another, unless otherwise specified.
- Moreover, in the following embodiments, when a number (including number of pieces, numerical value, amount, range and the like) of an element is referenced, it is not limited to the specific number but may be more or less than the specific number, unless otherwise specified or explicitly limited to the specific number in principle.
- Furthermore, in the following embodiments, components (including element steps) are not necessarily essential unless otherwise specified or explicitly essential in principle.
- Similarly, in the following embodiments, when a shape, positional relationship, or the like of the component is referenced, it includes substantially approximate or similar shape or the like unless otherwise specified or explicitly inapplicable in principle. This also applies to the numerical values and ranges described above.
- Throughout the figures for illustrating the embodiments, like reference numerals designate like parts in principle and the description thereof is not repeated. It is to be noted that a plan view may be hatched for better understanding.
- With reference to
FIGS. 1 to 7 , explanation is given about a semiconductor device and a method of manufacturing the same according to a first embodiment. This embodiment presents a diode DI used as a super fast recover diode (Fast Recovery Diode), for example, as a semiconductor element mounted on the semiconductor device. - As shown in
FIG. 1 , a substrate is prepared first that has n-type conductivity and includes a semiconductor such as silicon. The substrate configures a drift region DR of the diode DI. An impurity region AN having p-type conductivity is then formed near a surface of the drift region DR by ion implantation or the like. The impurity region AN configures an anode region of the diode DI. - This embodiment describes a configuration including the drift region DR and the anode region AN as a semiconductor substrate SUB.
- Here, a crystal surface on a surface of the drift region DR is a (001) surface. Because a silicon substrate having the (001) surface is commonly used, the manufacturing cost can be suppressed compared with preparing a substrate having another crystal surface. Moreover, the crystal surface on the surface of the anode region AN formed over the surface of the drift region DR is also the (001) surface. That is, the crystal surface on the surface of the semiconductor substrate SUB is the (001) surface.
- Moreover,
FIG. 1 shows a state in which an insulating film IF1 is formed over the surface of the semiconductor substrate SUB as a thin natural oxide film or a foreign matter. - Next, as shown in
FIG. 2 , the surface of the semiconductor substrate SUB is subjected to, for example, a reactive dry etching treatment using a gas containing carbon tetrafluoride (CF4) and a wet etching treatment using a cleaning liquid containing hydrogen fluoride (HF) as a cleaning treatment. The cleaning treatment removes the insulating film IF1 deposited over the surface of the semiconductor substrate SUB including the anode region AN. The cleaning treatment is performed primarily for reducing forward resistance of the diode DI, and thus for reducing contact resistance between the semiconductor substrate SUB and a pad electrode PD that will be formed later. - Next, as shown in
FIG. 3 , a conductive film AL1 containing mainly aluminum and doped with a small amount of silicon is formed over the semiconductor substrate SUB by, for example, sputtering. The thickness of the conductive film AL1 is about 2,500 nm. Temperature of formation of the conductive film AL1 by sputtering is about room temperature (23° C.) to 200° C., and more preferably about 150° C. It is to be noted that the reason why the conductive film AL1 is doped with a small amount of silicon is to prevent an interface between the conductive film AL1 and the semiconductor substrate SUB from having a spike shape. - Here, when the conductive film AL1 is an aluminum film, forming the aluminum film by the above-mentioned sputtering makes the crystal structure of the aluminum film a face-centered cubic structure (FCC: Face-Centered Cubic), and therefore the conductive film AL1 has the (111) surface or close-packed surface on almost all of its surfaces if not affected by its base. However, the conductive film AL1 according to the embodiment is formed taking over the crystal surface of the semiconductor substrate SUB, and thus the crystal surface on the surface of the conductive film AL1 is the (001) surface. This is because the step of forming the conductive film AL1 is performed immediately after the cleaning treatment illustrated in
FIG. 2 and therefore the conductive film AL1 tends to take over the crystal surface on the surface of the semiconductor substrate SUB during the forming step. Moreover, with the diode DI according to the embodiment, for the purpose of reducing the forward resistance, a barrier metal film including titanium nitride having higher resistance than that of the conductive film AL1 is not formed between the conductive film AL1 and the semiconductor substrate SUB but the conductive film AL1 is formed directly over the semiconductor substrate SUB. - In the light of crystallography, with regard to a cubic crystal, the (001) surface is equivalent to the (100) surface and a (010) surface as a crystal surface. Therefore, the (001) surface of the conductive film AL1 according to the embodiment is treated as a crystal surface equivalent to the (100) surface disclosed in “zincate Treatment and Electroless Ni—P Plating on Al Single-Crystal Surface,” Journal of The Surface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997. Here, as described in the above-mentioned document, there is a problem that, when the zincate treatment is performed on the (001) surface of the conductive film AL1 in the following step, zinc particles having a relatively large size are deposited, resulting in uneven thickness of the plating film of nickel or the like formed in the following step. This may cause separation between the plating film and the conductive film AL1, thereby reducing reliability of the semiconductor device.
- In other words, unless the cleaning treatment is performed as in this embodiment, the thin natural oxide film or the foreign matter is present over the surface of the semiconductor substrate SUB. If the conductive film AL1 is formed in such a state, the conductive film AL1 can hardly take over the crystal surface on the surface of the semiconductor substrate SUB, making it easier for the crystal surface other than the (001) surface to be formed over the surface of the conductive film AL1. However, to reduce resistance of the diode DI, it is desirable to perform the cleaning treatment to remove the thin natural oxide film or the foreign matter. This may make the crystal surface on the surface of the conductive film AL1 configuring the pad electrode PD the (001) surface.
- Therefore, the inventors have come up with a method of reducing resistance of the diode DI and making the crystal surface on the surface of the pad electrode PD different from the (001) surface by performing the cleaning treatment.
-
FIG. 4 is a cross-sectional view of the method of manufacturing the semiconductor device that followsFIG. 3 . - As described with reference to
FIG. 3 , the crystal surface on the surface of the conductive film AL1 is the (001) surface. In this state, as shown inFIG. 4 , an insulating film BIF is formed over the conductive film AL1 first. The insulating film BIF is formed by exposing the surface of the conductive film AL1 to an atmosphere containing oxygen, e.g. by once taking out the semiconductor substrate SUB from a sputtering device and exposing the semiconductor substrate SUB to the atmospheric air at room temperature (23° C.). That is, the insulating film BIF includes an oxide of a material that forms the conductive film ALL such as aluminum oxide. The thickness of the insulating film BIF ranges from 0.5 nm to 4.0, and more preferably from 1.0 nm to 3.0 nm. - Next, a conductive film AL2 containing mainly aluminum, for example, and also doped with silicon is formed over the insulating film BIF by the sputtering, for example. The thickness of the conductive film AL2 is about 2,500 nm. The temperature for forming the conductive film AL2 by the sputtering is between about the room temperature (23° C.) and 200° C., and more preferably about 150° C.
- Now, due to the insulating film BIF formed between the conductive film AL2 and the conductive film ALL the conductive film AL2 does not take over the (001) surface that is the crystal surface on the surface of the conductive film AL1 and thus it can be formed with the crystal surface different from the (001) surface.
- In this embodiment, at the initial stage of forming the conductive film AL2 by the sputtering, the crystal surface on the surface of the conductive film AL2 is predominantly the (111) surface. Specifically, 90% or more of the surface area of the conductive film AL2 is the (111) surface. In this manner, even if the (110) surface remains on a part of the conductive film AL2 after the initial stage of film formation, because particles on the (110) surface are covered by the particles of the (111) surface that configures the most part of the conductive film AL2 in the subsequent stage of film formation by the sputtering, the most part of the surface of the conductive film AL2 eventually becomes the (111) surface. Preferably, 90% or more of the surface of the conductive film AL2 is finally the (111) surface, and more preferably 99% or more of the surface of the conductive film AL2 is finally the (111) surface.
- In this manner, by forming the thin insulating film BIF over the surface of the conductive film AL1 having the (100) crystal surface, the crystal surface on the surface of the conductive film AL2 to be the surface of the pad electrode PD can be the (111) surface. That is, the insulating film BIF is an orientation blocking film serving as a film for blocking orientation of crystal.
- Although the embodiment shows the pad electrode PD having a two-layer structure of the conductive film AL1 and the conductive film AL2, the pad electrode PD may have three or more layers by further forming an insulating film such as the insulating film BIF over the conductive film AL2 and subsequently forming a conductive film such as the conductive film AL2 thereon.
- Moreover, as described above, the thickness of the insulating film BIF is no less than 0.5 nm and no more than 4.0 nm, and more preferably no less than 1.0 nm and no more than 3.0 nm. This is the thickness range for the conductive film AL2 not to take over the crystal surface of the conductive film AL1 and for sufficient conductivity to be guaranteed between the conductive film AL2 and the conductive film ALL That is, because voltage of millions of volts is applied to such a diode DI as described in this embodiment, the insulating film BIF having the thickness as described above does not affect properties of the diode DI.
- Next, as shown in
FIG. 5 , the pad electrode PD containing mainly the conductive film AL2 and the conductive film AL1 is formed by patterning the conductive film AL2, the insulating film BIF, and the conductive film AL1 using photolithography and dry etching. - An insulating film IF2 including an organic resin such as photosensitive polyimide is then formed over the semiconductor substrate SUB so as to cover the pad electrode PD. Then, an opening OP1 exposing a part of the pad electrode PD is formed over the insulating film IF2 by selectively exposing the insulating film IF2 to light. It is to be noted that a material for the insulating film IF2 may be inorganic insulating film such as silicon oxide or silicon nitride instead of the organic resin described above.
-
FIG. 6 illustrates a process flow to the step at which a conductive layer OPM is formed as inFIG. 7 to be described later, showing a plasma etching treatment S11 and plating treatments S12 to S20 to be performed on the pad electrode PD. In this embodiment, the plating treatment is described to include surface treatments S12 to S14, zincate treatments S15 to S17, and electroless plating treatments S18 to S20. After each process at S12 to S20, a pure water cleaning treatment may be performed. - Before conductive films PF1 to PF3 that are plating films are formed over the pad electrode PD by the electroless plating treatments S18 to S20, the plasma etching treatment S11 and the surface treatments S12 to S14 are performed on the surface of the pad electrode PD. The plasma etching treatment S11 and the surface treatments S12 to S14 are performed to remove the natural oxide film, the grease, the foreign matter, and the like present over the surface of the pad electrode PD.
- As indicated at Step S11 in
FIG. 6 , the plasma etching treatment is performed first on the surface of the conductive film AL2 using inert gas such as argon (Ar). The natural oxide film over the surface of the conductive film AL2 is removed by the plasma etching treatment. - Next, the plating treatment is performed on the surface of the conductive film AL2 in the order of surface treatments S12 to S14, zincate treatments S15 to S17, and electroless plating treatments S18 to S20.
- As indicated at Step S12 in
FIG. 6 , the degreasing treatment is performed on the surface of the conductive film AL2 using a weak alkaline aqueous solution containing sodium hydroxide or the like. The grease over the surface of the conductive film AL2 and the natural oxide film over the surface of the conductive film AL2 are primarily removed by the degreasing treatment. - Next, as indicated at Step S13 in
FIG. 6 , the etching treatment is performed using an alkaline aqueous solution containing, for example, copper (Cu). The etching treatment is performed to remove aluminum oxide present near the surface of the conductive film AL2, and it is effective where the conductive film AL2 is made of aluminum doped with silicon as in this embodiment. That is, by dissolving aluminum oxide present near the surface of the conductive film AL2 with the alkaline aqueous solution and substituting the aluminum surface with copper having a standard electrode potential higher than that of aluminum, it is possible to effectively reduce aluminum oxide present near the surface of the conductive film AL2. - Next, as indicated at Step S14 in
FIG. 6 , an acid cleaning is performed on the surface of the conductive film AL2 using an aqueous solution containing, for example, nitric acid. The acid cleaning allows for the copper substituted at Step S13 to be dissolved in the aqueous solution containing nitric acid and for removing copper from the surface of the conductive film AL2. - Next, as indicated at Step S15 in
FIG. 6 , a first zincate treatment is performed on the surface of the conductive film AL2. - As disclosed in “Zincate Treatment and Electroless Ni—P Plating on Al Single-Crystal Surface,” Journal of The Surface Finishing Society of Japan, Vol. 48, No. 8, p. 820-825, 1997, if ever the surface of the conductive film AL2 is (001) surface, growth of the zinc particles would be less even and its size may further increase.
- Next, as indicated at Step S16 in
FIG. 6 , the acid cleaning is performed on the surface of the conductive film AL2. For example, by using the aqueous solution containing nitric acid, zinc particles deposited by the first zincate treatment is dissolved in the aqueous solution containing nitric acid. This treatment allows aluminum to appear uniformly on the surface of the conductive film AL2. - Next, as indicated at Step S17 in
FIG. 6 , a second zincate treatment is performed on the surface of the conductive film AL2. This makes the zinc particles deposited onto aluminum again. A dense and uniform Zn film can be formed by repeating the zincate treatment two times. This allows the plating film of nickel or the like that will be formed in the following step to be deposited uniformly. - Next, as indicated at Steps S18 to S20 in
FIG. 6 and inFIG. 7 , the electroless plating treatment is performed on the surface of the pad electrode PD, thereby sequentially forming the conductive films PF1 to PF3. - First, as indicated at Step S18 in
FIG. 6 , the conductive film PF1 containing mainly nickel (Ni) or the like is formed over the exposed surface of the pad electrode PD (surface of the conductive film AL2) by electroless plating. To form the conductive film PF1, the surface of the conductive film AL2 is immersed in plating aqueous solution containing nickel ion or the like. At this time, the zinc particles deposited by the zincate treatment inFIG. 6 are dissolved into the plating aqueous solution. At the same time, nickel is reduced and deposited by electrons emitted from the zinc particles. That is, in the region where the zinc particles are deposited, nickel is reduced and deposited and the plating film grows using the deposited nickel as catalyst, thereby forming the conductive film PF1. As described above, because the size of each zinc particle is small and constant, the substituted and deposited nickel film also grow uniformly. Thus, it is possible to improve uniformity of the thickness of the conductive film PF1. - Then, as indicated at Steps S19 and S20, by sequentially forming the conductive film PF2 containing mainly palladium (Pd) or the like and the conductive film PF3 containing mainly gold (Au) over the conductive film PF1 by electroless plating, the conductive layer OPM including a lamination of the plating films. Because the conductive film PF2 and the conductive film PF3 are formed over the conductive film PF1 having highly uniform thickness, the conductive film PF2 and the conductive film PF3 are also formed with highly uniform thickness. Thus, it is possible to improve uniformity of thickness of the conductive layer OPM.
- It is to be noted that the thickness of the conductive film PF1 is about 1,000 to 4,000 nm, the thickness of the conductive film PF2 is about 100 to 400 nm, and the thickness of the conductive film PF3 is about 30 to 200 nm.
- Because the conductive film PF1 is a principal film of the conductive layer OPM, it is preferable to include a material having low sheet resistance. The conductive film PF3 is provided mainly to improve adhesiveness with an external connection terminal TR, and it is preferable to include a material having higher adhesiveness to the external connection terminal TR than the conductive film PF1. The conductive film PF2 is provided to prevent that the conductive film PF1 be diffused over the surface of the conductive film PF3 to corrode a boundary between the conductive film PF1 and the conductive film PF3.
- Moreover, the conductive layer OPM may be a lamination of the conductive film PF1 and the conductive film PF3 or a lamination of the conductive film PF1 and the conductive film PF2. Furthermore, the conductive film PF1 and the conductive film PF2 may contain phosphorus (P).
- In this manner, the conductive layer OPM including a plating film is formed over the pad electrode PD. It is to be noted that the conductive layer OPM configures an anode electrode of the diode DI.
- Next, a cathode region CT and a back electrode BE are formed on the back side of the semiconductor substrate SUB.
- First, the back side of the semiconductor substrate SUB is polished to reduce the thickness of the semiconductor substrate SUB. Next, an n-type impurity is introduced from the back side of the semiconductor substrate SUB using ion implantation to form the cathode region CT having a higher impurity concentration than that of the drift region DR. Subsequently, the introduced impurity is activated by heat treatment. Then, metal films including nickel (Ni), titanium (Ti), gold (Au), for example, are deposited in this order from the side abutting the cathode region CT using sputtering, thereby forming a cathode electrode (back electrode) BE including these metal films.
- The semiconductor device according to the embodiment is manufactured in the above-mentioned steps.
-
FIG. 8 is a schematic view showing one configuration in which a semiconductor wafer having the semiconductor device according to the embodiment formed thereon is diced into a chip CP1 by a dicing step of a post-processing treatment and then the semiconductor element including the diode DI according to the embodiment and an IGBT is modularized. In the schematic view, dimensions of configurations such as the conductive layer OPM are different from those described with reference toFIG. 7 . - In
FIG. 8 , the chip CP1 is the semiconductor device including the diode DI according to the embodiment formed thereon, and a chip CP2 is the semiconductor device including the semiconductor element of IGBT formed thereon. - The IGBT includes a configuration shown on the left side of
FIG. 8 . As shown inFIG. 8 , a p-type base layer 2 is formed over the surface of the n-type semiconductor substrate that configures adrift region 1. Formed over the surface of thebase layer 2 is an n-type source layer 3, and thebase layer 2 and thesource layer 3 are coupled commonly to anemitter electrode 6 including an aluminum film or the like. Thebase layer 2 arranged between thedrift region 1 and thesource layer 3 is a channel region, and agate electrode 5 is formed over the channel region via a gate insulating film 4. Formed over the back side of thedrift region 1 are abuffer layer 7 doped with an n-type impurity, anemitter layer 8 doped with a p-type impurity, and a collector electrode 9. - Moreover, as shown in
FIG. 8 , the cathode electrode BE of the diode DI and the collector electrode 9 of the IGBT are electrically coupled to each other, and the anode electrode (conductive layer) OPM of the diode DI and theemitter electrode 6 of the IGBT are also electrically coupled to each other. -
FIGS. 9 and 10 show an example in which the chip CP1 and the chip CP2 configuring the IGBT shown inFIG. 8 are packaged.FIG. 10 is a cross-sectional view taken along line A-A in the plan view shown inFIG. 9 . It is to be noted that a sealing resin MR and a die pad DP depicted inFIG. 10 are omitted inFIG. 9 for better understanding of the shape of the external connection terminal TR. It is illustrated here that the chip CP1 and the chip CP2 are coupled in a single package using a clip including, for example, a copper sheet, as an example of the external connection terminal TR. - As shown in
FIGS. 9 and 10 , the chip CP1 and the chip CP2 are mounted over the die pad DP via a solder BP1. The die pad DP also serves as a power source potential terminal DT that supplies power source potential to the chip CP1 and the chip CP2. That is, the cathode electrode BE of the chip CP1 and the collector electrode 9 of the chip CP2 are electrically coupled to the power source potential terminal DT (die pad DP) via the solder BP1. - Moreover, the external connection terminal TR is coupled to the CP1 and the chip CP2 via a solder BP2. The external connection terminal TR is electrically coupled to the ground potential terminal ST via a conductive adhesive or the like. The conductive layer OPM of the chip CP1 is coupled to the solder BP2. That is, the anode electrode (conductive layer) OPM of the chip CP1 and the
emitter electrode 6 of the chip CP2 are electrically coupled to the ground potential terminal ST via the solder BP2 and the external connection terminal TR. - Although detailed explanation is not provided, the
gate electrode 5 of the IGBT is coupled to another terminal via a bonding wire or the like other than the external connection terminal TR. - The chip CP1 and the chip CP2 coupled to the die pad DP and the external connection terminal TR are sealed with the sealing resin MR. In this manner, the semiconductor device according to the embodiment is packaged.
- Moreover, the external connection terminal TR may be a bonding wire including copper or gold. However, for such a semiconductor device that has a large area of the anode electrode (conductive layer) OPM of the diode DI and a large area of the
emitter electrode 6 of the IGBT and that is to receive voltage of hundreds of volts as in the embodiment, it is desirable to use a copper clip having a large area to reduce resistance related to coupling to another chip. It is also possible to use sintered silver (Ag) instead of the solders BP1, BP2. - Hereinbelow, main features of the embodiment are briefly summarized. The embodiment is characterized in that the crystal surface on the surface of the conductive film AL2 is formed with the crystal surface different from that of the crystal surface on the surface of the conductive film AL1.
- For example, when the crystal surface on the surface of the pad electrode PD is formed with the (001) surface, in the first and second zincate treatments in
FIG. 6 , there is a problem that the size of the deposited zinc particle is so large that the deposition of the plating film such as nickel formed by the electroless plating cannot be performed uniformly and the surface of the plating film becomes rough. Thus, moisture or the like enters the interface between the pad electrode PD and the conductive layer OPM facilitating separation in this portion, which reduces reliability of the semiconductor device. Furthermore, appearance abnormality is observed on the surface of the plating film. - To the contrary, in this embodiment, by forming the thin insulating film BIF over the conductive film AL1 having the (001) surface, the conductive film AL2 formed over the insulating film BIF is not affected by the crystal surface on the surface of the conductive film ALL allowing the he crystal surface on the surface of the conductive film AL2 to have the (111) surface. Thus, because the size of each zinc particle deposited during the first and second zincate treatments shown in
FIG. 6 is uniform and small, the deposite from the conductive film PF1 including nickel and the like formed by electroless plating can be formed relatively uniformly. This allows for a configuration in which separation is hardly caused on the interface between the pad electrode PD and the conductive layer OPM, thereby improving reliability of the semiconductor device. Furthermore, appearance abnormality on the surface of the plating film can be minimized. - Especially, in this embodiment, the cleaning treatment is performed on the semiconductor substrate SUB serving as the base of the conductive film AL1 to keep the surface of the semiconductor substrate SUB clean. This reduces the contact resistance between the semiconductor substrate SUB and the conductive film ALL thereby reducing resistance of the diode DI. However, because the conductive film AL1 tends to take over the (001) surface that is the crystal surface on the surface of the semiconductor substrate SUB, the crystal surface on the surface of the conductive film AL1 also tends to have the (001) surface. Here, by forming the conductive film AL2 over the conductive film AL1 via the insulating film BIF as described above, the crystal surface on the surface of the conductive film AL2 may have the (111) surface, which achieves the structure in which separation is hardly caused on the interface between the pad electrode PD and the conductive layer OPM. That is, using the technique of the embodiment can improve performance of the semiconductor device and also improve reliability of the semiconductor device.
- In the first embodiment, the insulating film BIF is formed over the conductive film AL1 by once taking out the semiconductor substrate SUB from the sputtering device and exposing it to the atmospheric air, as shown in
FIG. 4 . - To the contrary, according to a first modification, the semiconductor substrate SUB is transferred to another chamber without taking it out of the sputtering device, an oxygen-containing gas is introduced into the sputtering device, and the surface of the conductive film AL1 is exposed to oxygen atmosphere, thereby forming the insulating film BIF. Specifically, exposure to such oxygen atmosphere is performed in oxygen gas atmosphere at room temperature. The oxidation treatment maybe combined with heat treatment, and may be conducted by emitting plasma using oxygen gas.
- Subsequently, the conductive film AL2 is formed over the insulating film BIF by the sputtering as in the first embodiment, without taking out the semiconductor substrate SUB from the sputtering device.
- In this manner, because there is no need of taking out the semiconductor substrate SUB from the sputtering device to form the insulating film BIF, it is possible to perform the next step of forming the conductive film AL2 immediately. Thus, compared with the first embodiment, it is possible to simplify the process of manufacturing the semiconductor device.
- In the first embodiment, the conductive film AL2 is configured using the same material as that of the conductive film ALL the material containing mainly, for example, aluminum doped with silicon.
- To the contrary, in a second modification, the conductive film AL2 is configured using a material different from that of the conductive film AL1, the material containing mainly, for example, aluminum doped with copper. That is, the element doped into the conductive film AL2 is different from the element doped into the conductive film AL1.
- The conductive film AL1 is in direct contact with the diode DI and made of aluminum film doped with silicon for the purpose of reducing spike shapes on the interface between the semiconductor substrate SUB and the conductive film AL1. However, because the conductive film AL2 is not in direct contact with the diode DI, the material of the conductive film AL2 may be other material than the aluminum film doped with silicon. Here, because the copper-doped aluminum film exhibits better electromigration than the silicon-doped aluminum film, the copper doped aluminum film is used as the conductive film AL2 of the second modification.
- Moreover, by using the copper-doped aluminum film as the conductive film AL2, the etching treatment at Step S13 in
FIG. 6 can be omitted. That is, the aluminum oxide present over the surface of the conductive film AL2 is substituted using the aqueous solution containing copper having high standard electrode potential at Step S13 described above. However, in the second modification, copper is already included in the conductive film AL2. Therefore, it is possible to more effectively remove the oxide over the surface of the conductive film AL2 by the degreasing treatment using the alkaline aqueous solution at Step S12 or the subsequent zincate treatment. The zincate treatment further facilitates deposition of the zinc particles, and the electroless plating treatment further facilitates substitute and deposite nickel. Thus, because Step S13 shown inFIG. 6 can be omitted in the second modification, the method of manufacturing the semiconductor device can be simplified. - Furthermore, the conductive film AL2 may be made of a material containing mainly aluminum and doped with copper and silicon.
- It is to be noted that the technique disclosed in the second modification is also applicable to the above-mentioned first modification.
- In the first embodiment, the insulating film BIF is formed over the conductive film AL1 to differentiate the crystal surface of the conductive film AL2 from that of the conductive film ALL
- To the contrary, in the second embodiment, formed over the conductive film AL1 is an amorphous film that is a conductive film made of a material different from that of the conductive film AL1 and in an amorphous state over the conductive film AL1. It is to be noted that the amorphous film a replacement from the insulating film BIF in the first embodiment and therefore it is not presented in the drawings. In other words, the reference symbol “BIF” indicated in
FIG. 4 or the like designates the amorphous film. - Such an amorphous film is formed by sputtering or CVD and configured by a film containing mainly, for example, tantalum, titanium nitride, or tungsten nitride. Moreover, the thickness of the amorphous film is between 0.5 nm and 4.0 nm, and more preferably between 1.0 nm and 3.0 nm.
- That is, the above-mentioned material can exist in the amorphous state as long as it has such a small film thickness. Because the amorphous film is in the amorphous state, it does not have a specific crystal surface. Therefore, when the conductive film AL2 is formed over the amorphous film by sputtering, the conductive film AL2 does not take over the crystal surface of the conductive film AL1 but grows mainly based on the (111) surface, as in the first embodiment. That is, the amorphous film is an orientation blocking film serving as a film for blocking orientation of crystal, like the insulating film BIF. Thus, the semiconductor device according to the second embodiment can provide the same effect as the first embodiment.
- It is to be noted that the second modification of the first embodiment described above can be applied to the technique disclosed in the second embodiment.
- In a third embodiment, the conductive film AL1 and the conductive film AL2 used in the first embodiment are applied to wiring of a power MOS. Here, as an example of the wiring of the power MOS, a case is described in which the conductive film AL1 and the conductive film AL2 are applied to a source electrode SPD.
- A structure of the semiconductor device according to the third embodiment and a method of manufacturing the same are described below with reference to
FIGS. 11 to 13 . -
FIG. 11 shows an n-type power MOS including an n-type gate electrode GE, a gate insulating film GI, an insulating film IF3 that covers the gate electrode GE, a p-type channel region CH, an n-type source region SR, an n-type drift region NV serving as a drain region, and an n-type substrate SB. - An example method of manufacturing such a power MOS is described below.
- The substrate SB having n-type conductivity and including semiconductor such as silicon is prepared first. Next, a drift region NV (impurity region NV) having n-type conductivity and impurity concentration lower than that of the substrate SB is formed over the substrate SB by epitaxy or the like. In this embodiment, explanation is given assuming a structure including the substrate SB and the drift region NV as the semiconductor substrate SUB.
- After forming a groove in the drift region NV, a gate insulating film GI including silicon oxide is formed over the side face and the bottom face of the groove. Next, the gate electrode GE including polycrystalline silicon or the like is formed over the gate insulating film GI so as to fill the groove. Then, the channel region CH having p-type conductivity is formed on top of the drift region NV by ion implantation. A boundary between the channel region CH and the drift region NV is located above the bottom face of the gate electrode GE. The source region SR (impurity region SR) having n-type conductivity is then formed on top of the channel region CH by ion implantation. The insulating film IF3 is then selectively formed over a portion of the source region SR and over the gate electrode GE. Next, by performing dry etching on a portion exposed on the insulating film IF3, an opening OP2 reaching the channel region CH through the source region SR is formed. The n-type power MOS is manufactured as described above.
- Next, as shown in
FIG. 12 , the conductive film AL1 and the conductive film AL2 serving as the source electrode SPD are formed over the insulating film IF3. - First, a barrier metal film BM including titanium tungsten (TiW), titanium nitride (TiN), or the like is formed in the opening OP2 and over the insulating film IF3. Then, the conductive film AL1 containing mainly aluminum, for example, is formed over the barrier metal film BM so as to fill the opening OP2. This allows the conductive film AL1 serving as a part of the source electrode SPD to be electrically coupled to the source region SR and the channel region CH.
- It is to be noted that, in the third embodiment, the barrier metal film BM is formed between the semiconductor substrate SUB and the conductive film AL1 unlike the first embodiment and the second embodiment described above. Accordingly, the conductive film AL1 may use a material mainly containing aluminum and doped with silicon or a material mainly containing aluminum and doped with copper.
- Here, the conductive film AL1 is formed by sputtering, and the maximum temperature in the forming process ranges from 250 to 400 degrees, which is higher than that in the first embodiment. This is to prevent a void formed in the conductive film AL1 when the conductive film AL1 is filled in the opening OP2. The formation of the conductive film AL1 may be performed in two steps including an initial film formation performed at a low temperature ranging from room temperature (23° C.) to 200° C. and a second step performed at a high temperature ranging from 250 to 400° C. for filling. Moreover, a step is made between the surface of the conductive film AL1 located on top of the opening OP2 and the surface of the conductive film AL1 located on top of the gate electrode GE. To minimize the step to make the entire surface of the conductive film AL1 as flat as possible, it is effective to form the conductive film AL1 at high temperature. For the semiconductor device according to this embodiment, the conductive layer OPM is formed over the source electrode SPD in a later step. Thus, by eliminating any void in the conductive film AL1 serving as apart of the source electrode SPD and flattening its surface, it is possible to make the thickness of the conductive layer OPM more uniform.
- In such an aluminum film formed at relatively high temperature, however, the size of the aluminum particle tends to be larger compared with an aluminum film formed at relatively low temperature as in the first embodiment. That is, the crystal surface on the surface of the conductive film AL1 tends to have not only the (111) surface but also the (001) surface. Thus, if the conductive layer OPM is formed over the conductive film AL1, separation would easily occur between the source electrode SPD and the conductive layer OPM as in the first embodiment.
- Therefore, in the third embodiment, the thin insulating film BIF is formed over the conductive film AL1 and then the conductive film AL2 is formed over the conductive film AL1 as in the first embodiment. This can differentiate the crystal surface on the surface of the conductive film AL2 from the crystal surface on the surface of the conductive film AL1. It is to be noted that the method of forming the insulating film BIF and the conductive film AL2 is the same as that in the first embodiment. Accordingly, the crystal surface on the surface of the conductive film AL2 in this embodiment is also the (111) surface.
- In this embodiment, the temperature of formation of the conductive film AL2 is lower than that of the conductive film ALL and it is about room temperature (23° C.) to 200° C., for example, and more preferably about 150° C. That is, because the conductive film AL1 is formed at relatively high temperature, the flatness of its surface is improved whereas the possibility of generating the (001) surface having a large particle size also increases. Therefore, generation of the (001) surface having the large particle size can be suppressed by forming the conductive film AL2 at relatively low temperature. In other words, in the third embodiment, the area ratio of the (111) surface on the surface of the conductive film AL2 is higher than that of the (111) surface on the surface of the conductive film AL1
- Then, the source electrode SPD shown in
FIG. 12 is formed by patterning the conductive film AL2, the insulating film BIF, the conductive film ALL and the barrier metal film BM using photolithography and dry etching. It is to be noted that a gate pad electrode GPD to be coupled to the gate electrode GE of the power MOS is also formed at this time (not shown in the figure). - Next, as shown in
FIG. 13 , the insulating film IF2 having the opening OP1 is formed over the conductive film AL2 so as to expose a portion of the conductive film AL2 serving as a portion of the source electrode SPD. It is to be noted that the method of forming the insulating film IF2 and its material are the same as those in the first embodiment. - Next, by sequentially forming the conductive films PF1 to PF3 using the same technique as in the first embodiment, the conductive layer OPM is formed over the conductive film AL2 in the opening OP1.
- Then, as in the first embodiment, the back side of the substrate SB is polished to form the drain electrode (back electrode) BE.
- The semiconductor device of the third embodiment is manufactured according to the above-mentioned steps.
- As described above, according to the third embodiment, it is possible to suppress the separation between the source electrode SPD and the conductive layer OPM and to obtain the same effect as the first embodiment.
-
FIG. 14 shows a view of a chip CP3 including the power MOS according to the third embodiment formed thereon in the packaged state. Here, as an example of the external connection terminal TR to be coupled to the conductive layer OPM, a case of using a clip made of a copper sheet is described. - As shown in
FIG. 14 , the chip CP3 is mounted over the die pad DP via a solder BP3. The die pad DP also serves as the power source potential terminal DT that supplies power source potential to the chip CP3. That is, the drain electrode BE of the chip CP3 is electrically coupled to the power source potential terminal DT (die pad DP) via the solder BP3. - Moreover, the external connection terminal TR is coupled to the chip CP3 via a solder BP4. The external connection terminal TR is electrically coupled to the ground potential terminal ST via a solder BP5. Here, the conductive layer OPM of the chip CP3 is coupled to the solder BP4. That is, the source electrode SPD of the chip CP3 is electrically coupled to the ground potential terminal ST via the conductive layer OPM, the solder BP4, the external connection terminal TR, and the solder BP5.
- Moreover, the gate pad electrode GPD of the power MOS is coupled to a gate potential terminal GT via a bonding wire WB.
- Such a chip CP3 is sealed with the sealing resin MR. In this manner, the semiconductor device according to the third embodiment is packaged.
- Furthermore, it is also possible to apply the technique of the first and second modifications of the first embodiment and the second embodiment to the technique disclosed in the third embodiment.
- Moreover, although the conductive film AL1 and the conductive film AL2 are employed as the source electrode SPD of the power MOS in the third embodiment, it is also possible to employ the conductive film AL1 and the conductive film AL2 as the emitter electrode of the IGBT. Furthermore, when applied to the IGBT, the channel region CH of the power MOS is a base region.
- Moreover, when applying the technique disclosed in the third embodiment to the IGBT, the chip CP3 described in the third embodiment maybe employed instead of the chip CP2 shown in
FIGS. 8 to 10 of the first embodiment. - Although the invention made by the inventors are specifically described with reference to the embodiments, the invention is not limited to the embodiments but various modifications may be made without departing from the scope of the invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/225,639 US11652072B2 (en) | 2017-08-24 | 2021-04-08 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017161043A JP7027066B2 (en) | 2017-08-24 | 2017-08-24 | Semiconductor devices and their manufacturing methods |
JP2017-161043 | 2017-08-24 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/225,639 Continuation US11652072B2 (en) | 2017-08-24 | 2021-04-08 | Semiconductor device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190067225A1 true US20190067225A1 (en) | 2019-02-28 |
Family
ID=65435621
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/029,334 Abandoned US20190067225A1 (en) | 2017-08-24 | 2018-07-06 | Semiconductor device and method of manufacturing the same |
US17/225,639 Active 2039-02-09 US11652072B2 (en) | 2017-08-24 | 2021-04-08 | Semiconductor device and method of manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/225,639 Active 2039-02-09 US11652072B2 (en) | 2017-08-24 | 2021-04-08 | Semiconductor device and method of manufacturing the same |
Country Status (3)
Country | Link |
---|---|
US (2) | US20190067225A1 (en) |
JP (1) | JP7027066B2 (en) |
CN (1) | CN109427876A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200013749A1 (en) * | 2016-05-20 | 2020-01-09 | Infineon Technologies Ag | Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact |
CN112420819A (en) * | 2019-08-23 | 2021-02-26 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
US11152318B2 (en) * | 2017-11-22 | 2021-10-19 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method of semiconductor device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7237785B2 (en) * | 2019-09-20 | 2023-03-13 | 株式会社東芝 | Semiconductor device manufacturing method |
CN111540680A (en) * | 2020-05-29 | 2020-08-14 | 上海华虹宏力半导体制造有限公司 | Electroless plating method applied to IGBT device |
JP7447703B2 (en) * | 2020-06-26 | 2024-03-12 | 株式会社デンソー | Semiconductor device and its manufacturing method |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59100565A (en) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | Semiconductor device |
JPS59172770A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Semiconductor device |
JPS61242018A (en) * | 1985-04-19 | 1986-10-28 | Toshiba Corp | Manufacture of semiconductor device |
JP2581666B2 (en) | 1985-09-06 | 1997-02-12 | 株式会社日立製作所 | Manufacturing method of wiring structure |
US4987562A (en) * | 1987-08-28 | 1991-01-22 | Fujitsu Limited | Semiconductor layer structure having an aluminum-silicon alloy layer |
JP2680468B2 (en) * | 1989-07-01 | 1997-11-19 | 株式会社東芝 | Semiconductor device and method of manufacturing semiconductor device |
US5262361A (en) * | 1992-01-07 | 1993-11-16 | Texas Instruments Incorporated | Via filling by single crystal aluminum |
JPH05206054A (en) * | 1992-01-29 | 1993-08-13 | Nec Corp | Al contact structure and manufacture thereof |
US5501174A (en) | 1994-04-07 | 1996-03-26 | Texas Instruments Incorporated | Aluminum metallization for sige devices |
JP3483490B2 (en) | 1999-02-16 | 2004-01-06 | シャープ株式会社 | Method for manufacturing semiconductor device |
JP5033335B2 (en) | 2006-02-21 | 2012-09-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device and inverter device using the same |
JP4973046B2 (en) * | 2006-07-20 | 2012-07-11 | 株式会社デンソー | Manufacturing method of semiconductor device |
JP5672685B2 (en) * | 2009-09-29 | 2015-02-18 | 富士電機株式会社 | Manufacturing method of semiconductor device |
JP2016004877A (en) | 2014-06-16 | 2016-01-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device and electronic device |
-
2017
- 2017-08-24 JP JP2017161043A patent/JP7027066B2/en active Active
-
2018
- 2018-07-06 US US16/029,334 patent/US20190067225A1/en not_active Abandoned
- 2018-08-21 CN CN201810953004.XA patent/CN109427876A/en active Pending
-
2021
- 2021-04-08 US US17/225,639 patent/US11652072B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200013749A1 (en) * | 2016-05-20 | 2020-01-09 | Infineon Technologies Ag | Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact |
US10978418B2 (en) * | 2016-05-20 | 2021-04-13 | Infineon Technologies Ag | Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer |
US11152318B2 (en) * | 2017-11-22 | 2021-10-19 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method of semiconductor device |
CN112420819A (en) * | 2019-08-23 | 2021-02-26 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
US11239329B2 (en) * | 2019-08-23 | 2022-02-01 | Mitsubishi Electric Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US11652072B2 (en) | 2023-05-16 |
JP2019040975A (en) | 2019-03-14 |
CN109427876A (en) | 2019-03-05 |
JP7027066B2 (en) | 2022-03-01 |
US20210225789A1 (en) | 2021-07-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11652072B2 (en) | Semiconductor device and method of manufacturing the same | |
JP3871607B2 (en) | Semiconductor device and manufacturing method thereof | |
US11728376B2 (en) | Structure and formation method of semiconductor device structure with gate stack | |
US11456265B2 (en) | Semiconductor device and method of manufacturing the same | |
JP4221012B2 (en) | Semiconductor device and manufacturing method thereof | |
US7329614B2 (en) | Heat resistant ohmic electrode and method of manufacturing the same | |
KR20170038645A (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP2015056532A (en) | Semiconductor device and manufacturing method of the same | |
CN110582852A (en) | vertical gallium nitride schottky diode | |
US20120220122A1 (en) | Nitride semiconductor device and manufacturing method thereof | |
US20090026486A1 (en) | Nitride based compound semiconductor light emitting device and method of manufacturing the same | |
TWI557944B (en) | Optoelectronic semiconductor chip | |
JP4800239B2 (en) | Manufacturing method of semiconductor device | |
JP2010165983A (en) | Light-emitting chip integrated device and method for manufacturing the same | |
US6838744B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2009010421A (en) | Method for mounting semiconductor device on circuit board | |
JP3340648B2 (en) | Method for forming electrode of semiconductor device | |
JP2007305906A (en) | Diode | |
JP6945037B2 (en) | Manufacturing method of semiconductor devices | |
JP2005333147A (en) | Semiconductor device and manufacturing method of same | |
KR101147715B1 (en) | Semiconductor light emitting device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TONEGAWA, TAKASHI;INAGAWA, HIROSHI;REEL/FRAME:046298/0029 Effective date: 20180530 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |