JPS59100565A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59100565A JPS59100565A JP21015882A JP21015882A JPS59100565A JP S59100565 A JPS59100565 A JP S59100565A JP 21015882 A JP21015882 A JP 21015882A JP 21015882 A JP21015882 A JP 21015882A JP S59100565 A JPS59100565 A JP S59100565A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- alloy
- aluminum
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910000861 Mg alloy Inorganic materials 0.000 claims description 6
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- SNAAJJQQZSMGQD-UHFFFAOYSA-N aluminum magnesium Chemical compound [Mg].[Al] SNAAJJQQZSMGQD-UHFFFAOYSA-N 0.000 claims description 4
- 229910018182 Al—Cu Inorganic materials 0.000 abstract description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 8
- 229910018134 Al-Mg Inorganic materials 0.000 abstract description 7
- 229910018467 Al—Mg Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910052749 magnesium Inorganic materials 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract 3
- 238000003475 lamination Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000013078 crystal Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 229910000881 Cu alloy Inorganic materials 0.000 description 6
- 239000011777 magnesium Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000013508 migration Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001556 precipitation Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910000979 O alloy Inorganic materials 0.000 description 1
- 229910000711 U alloy Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Abstract
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置の構造に係シ、特に浅い接合を有す
る半導体装置に配設されるアルミニウム電極配線の構造
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor device, and particularly to the structure of an aluminum electrode wiring provided in a semiconductor device having a shallow junction.
(b) 技術の背景
高集積度のバイポーラICのエミツタ層等、浅い接合を
有するn型拡散領域は、通常、p型半導体基体面に多結
晶シリコ4層を介して堆積されたりん珪酸ガラス(PS
G)からシん(P)を固相−固相・拡散させて形成する
(ウオツシつ、ド・エミッタ法)。そして該浅い拡散層
に対するアルミニウム(Al)配線の接続に際しては、
Alが拡散層内にもぐシ込んで接合を破壊するのを防止
するために、前記多結晶シリコン層上にAl配線ノ(タ
ーンが形成される。従ってこのよう々構造に於てはA[
配線パターンの下部には全域にわたって多結晶シリコン
層が配設されているので、表面保護絶縁膜の成長等配線
パターンが形成されて後の400〜450〔℃〕程度の
熱処理工程に於て、多結晶シリコンがAl配線中に過飽
和に溶は込んで析出し、配線抵抗を増大せしめるという
問題がある。(b) Background of the technology An n-type diffusion region with a shallow junction, such as the emitter layer of a highly integrated bipolar IC, is usually made of phosphosilicate glass (which is deposited on the surface of a p-type semiconductor substrate through four layers of polycrystalline silicon). P.S.
G) is formed by solid phase-solid phase diffusion of thin (P) (washing, de-emitter method). When connecting the aluminum (Al) wiring to the shallow diffusion layer,
In order to prevent Al from penetrating into the diffusion layer and destroying the junction, Al wiring turns are formed on the polycrystalline silicon layer. Therefore, in such a structure, A[
Since a polycrystalline silicon layer is disposed over the entire area under the wiring pattern, many problems occur during the heat treatment process at about 400 to 450 [°C] after the wiring pattern is formed, such as the growth of a surface protection insulating film. There is a problem in that crystalline silicon dissolves into the Al wiring at supersaturation and precipitates, increasing the wiring resistance.
又一方ICの高集積化が進み、配線が微細化されて配線
に流れる電流密度が高まって来ると)純Alからなる配
線に於ては、長時間通電を行った際公知のエレクトロ・
マイグレーション効果によシ断線を生ずるという問題が
あシ、該エレクトロ・マイグレーション効果を減殺して
配線寿命を増加せしめる手段として、4層%)以下程度
の銅(Cu)若しくはマグネシウム(Mg)を含有せし
めたAl−Cu合金配琺成るいけAl−Mg合金配線が
多く用いられるようになって来た。On the other hand, as ICs become more highly integrated, the wiring becomes finer, and the density of current flowing through the wiring increases.) In wiring made of pure Al, when electricity is applied for a long time, the well-known electromagnetic
There is a problem that wire breakage occurs due to the migration effect, and as a means to reduce the electro-migration effect and increase the wiring life, copper (Cu) or magnesium (Mg) is contained in the layer at an amount of 4% or less. Al--Mg alloy interconnects made of Al--Cu alloy interconnects have come to be widely used.
しかしながら該Al−Cu合金配線若しくは1−Mg合
金配線を、前述した方法で浅い接合を形成したIC基板
の多結晶シリコン層上に形成した際には、前述したよう
な配線形成後の熱処理によって配線内へのシリコン結晶
の析出が促進され、且つ析出結晶の形状も純Alの場合
に比べて大型化するため、配線抵抗が大幅に増大してI
Cの動作速度を低下させるという問題を生ずる。第1図
はシリコン結晶が析出したAl−Cu若しくは1−Mg
合金配線を模式的に示したもので、図中1はAl−Cu
若しくはAl−Mg合金配線、2はシリコン析出結晶、
3は多結晶シリコン層を表わしている。However, when the Al-Cu alloy wiring or 1-Mg alloy wiring is formed on the polycrystalline silicon layer of the IC substrate on which shallow junctions have been formed by the method described above, the wiring is removed by heat treatment after wiring formation as described above. As the precipitation of silicon crystals inside is promoted and the shape of the precipitated crystals becomes larger than in the case of pure Al, wiring resistance increases significantly and I
A problem arises in that the operating speed of C is reduced. Figure 1 shows Al-Cu or 1-Mg with precipitated silicon crystals.
This is a schematic diagram of alloy wiring, and 1 in the figure is Al-Cu.
or Al-Mg alloy wiring, 2 is silicon precipitated crystal,
3 represents a polycrystalline silicon layer.
(c)従来技術と問題点
そこでAl−Cu合金配線若しくはAl−Mg合金配線
を用いた場合、析出シリコン結晶を多結晶シリコン層に
接する下層部のみに閉じ込めるために、従来第2図に示
すように例えばAd−Cu合金配置9工の下層に近い部
分に高融点配線材料として多用されているチタン・タン
グステン(T i −W)合金層4からなる500〜1
500 CX)程度の厚さのブロッキング層を挾み込ん
だ構造が試みられ、Al−Cu合金配線1に於ける下層
部5以外でのシリコン結晶の析出は防止された。(c) Prior art and problems Therefore, when using Al-Cu alloy wiring or Al-Mg alloy wiring, in order to confine the precipitated silicon crystal only in the lower layer in contact with the polycrystalline silicon layer, the conventional technique shown in Fig. 2 is used. For example, a titanium-tungsten (Ti-W) alloy layer 4, which is often used as a high-melting point wiring material, is placed near the lower layer of the Ad-Cu alloy arrangement 9.
A structure in which blocking layers with a thickness of about 500 CX) were sandwiched was tried, and precipitation of silicon crystals in areas other than the lower layer 5 of the Al--Cu alloy wiring 1 was prevented.
しかしこの構造に於てはTi−W合金のシリコンに対す
る反応性が極めて強いため、電極コンタクト部に於て多
結晶シリコン層の下部の例えば浅いエミツタ層のシリコ
ンまで該Ti−W合金層に食われ、エミツタ層の接合が
破壊されてエミッターヘース(E−B)ショート障害が
誘起されるという問題があった。However, in this structure, the reactivity of the Ti-W alloy with silicon is extremely strong, so even the silicon in the shallow emitter layer below the polycrystalline silicon layer at the electrode contact part is eaten away by the Ti-W alloy layer. However, there is a problem in that the junction of the emitter layer is destroyed and an emitter head (E-B) short failure is induced.
(d) 発明の目的
本発明は上記問題点に鑑み、シリコンに対する反応性が
なく、且つ遮蔽効果が充分なシリコンのブロック層を底
部近傍に配設したjW! −Cu若しくはAl−Mg層
からなる配線構造を提供するものでアシ、その目的とす
るところは配線の品質及び信頼性を高めて、半導体IC
の性能及び信頼性を向上せしめるにある。(d) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a jW! that has a silicon block layer near the bottom that is not reactive to silicon and has a sufficient shielding effect. - It provides a wiring structure consisting of Cu or Al-Mg layer, and its purpose is to improve the quality and reliability of wiring, and to improve the quality and reliability of semiconductor ICs.
The goal is to improve the performance and reliability of
(e) 発明の椙”成
即ち本発明は半導体装置に於て、アルミニウム若しくは
アルミニウム合金からなる第1層と、窒化チタンからな
る第2層と、アルミニウムー銅O合金若しくはアルミニ
ウムーマグネシウム・合金からなる第3層が、下部よシ
順次積層されてなる金属配線を具備してなることを特徴
とする。(e) At the dawn of the invention, the present invention provides a semiconductor device comprising a first layer made of aluminum or an aluminum alloy, a second layer made of titanium nitride, and an aluminum-copper O alloy or an aluminum-magnesium alloy. The third layer is characterized in that it includes metal wiring that is sequentially laminated from the bottom.
(f) 発明の実施例
以下本発明を実施例について、図を用い詳細に説明する
。(f) Examples of the Invention The present invention will now be described in detail with reference to the drawings.
第3図は本発明に於ける金属配線構造の一実施例を示す
断面図、第4図は本発明の半導体装置に於ける一実施例
の要部断面図である。FIG. 3 is a cross-sectional view showing an embodiment of a metal wiring structure according to the present invention, and FIG. 4 is a cross-sectional view of essential parts of an embodiment of a semiconductor device according to the present invention.
本発明の特徴とする金属配線は、該配線が直に接するシ
リコン(St)基板、エピタキシャル層。The metal wiring, which is a feature of the present invention, is a silicon (St) substrate and an epitaxial layer that the wiring directly contacts.
拡散層、多結晶St層等の半導体基体とオーミック・コ
ンタクトをとるための純Al若しくはAl−Cu 、
A l −Mg等のAA合金層からなる第1層と、該第
1層内に過飽和に溶は込んだStを該第1層内のみに閉
じ込めておくための遮蔽効果を持つ窒化チタン(TiN
)からなる第2層と、主たる導電層でありAl−Cu若
しくはAl−Mg等のA1合金層を用いAlのマイグレ
ーションを防止した第3層が下部から順次積層された三
層構造を有してなっている。Pure Al or Al-Cu for making ohmic contact with semiconductor substrates such as diffusion layers and polycrystalline St layers;
The first layer consists of an AA alloy layer such as Al-Mg, and the titanium nitride (TiN
), and the third layer, which is the main conductive layer and is made of an A1 alloy layer such as Al-Cu or Al-Mg to prevent migration of Al, are laminated sequentially from the bottom. It has become.
第3図はその断面を示しだもので、オーミックコンタク
トをとるだめの第1層は500〜1500〔久〕程度の
厚さに、Siの拡散を阻止するための第2層は500〜
1500〔久〕程度の厚さに、又主たる導電層である第
3層は4000〜8000〔X〕程度の厚さにそれぞれ
形成される。Figure 3 shows its cross section. The first layer for making ohmic contact has a thickness of about 500 to 1,500 [ku], and the second layer to prevent Si diffusion has a thickness of about 500 to 1,500 [ku].
The third layer, which is the main conductive layer, is formed to have a thickness of about 4000 to 8000 [X].
なおここで必ずAl−Cu若しくはAl−Mg合つ組織
を不均一化させないためには、0.5〜4〔チ〕程度の
Cu若しくはMgを含むA1合金が望ましい。Note that in order to prevent the Al--Cu or Al--Mg structure from becoming non-uniform, an A1 alloy containing about 0.5 to 4 [chi] of Cu or Mg is desirable.
又第1層の材料にAl−Cu、A/−Mg等のA4合金
を含めたのは、第3層と同材料にして形成工程の簡略化
を図ったもので、機能的には純Alで充分である。In addition, the reason why A4 alloys such as Al-Cu and A/-Mg are included in the material of the first layer is to simplify the formation process by using the same material as the third layer, and it is functionally pure Al. is sufficient.
更に又、Siの遮蔽層として用いたTiN層は80〔μ
Ω−Cm、]程度の比較的高い抵抗率を有するが、層の
厚さが極めて薄いので、配線抵抗及ぼす影響は極めて少
ない。Furthermore, the TiN layer used as the Si shielding layer has a thickness of 80 [μ
Although it has a relatively high resistivity of about Ω-Cm, since the layer thickness is extremely thin, the effect on wiring resistance is extremely small.
第4図は上記配線が形成された浅いエミツタ層を有する
バイポーラICの要部断面を示したもので、図中11は
n型コレクタ領域、12はp型ベース領域、13はn上
型エミッタ領域、14は二酸化シリコン(Sin2)膜
、15は多結晶Si層、16はAl−Cu合金・オーミ
ック・コンタクト層、17はTiN層、18はA7−C
u合金Φ主導電層、19はエミッタ配線、20はベース
配線、21はカバー絶縁膜を表わしている。FIG. 4 shows a cross section of a main part of a bipolar IC having a shallow emitter layer on which the above wiring is formed, in which 11 is an n-type collector region, 12 is a p-type base region, and 13 is an n-type emitter region. , 14 is a silicon dioxide (Sin2) film, 15 is a polycrystalline Si layer, 16 is an Al-Cu alloy ohmic contact layer, 17 is a TiN layer, 18 is A7-C
The U alloy Φ main conductive layer, 19 is an emitter wiring, 20 is a base wiring, and 21 is a cover insulating film.
そしてエミッタ配線19.ベース配線20等本発明の構
造を有する金属配線を形成する際には、DCマグネトロ
ン・スパッタ法若しくはRFマグネトロン争スパッタ法
を用いて基体上にAl−Cu合金層16.TiN層1層
上711−Cu合金層18を順次積層形成し、三塩化硼
素(B CAR)+四塩化炭素<CC,、)等塩素系の
ガスを用いるドライエツチング法により、前記積層膜を
一気にパターンニングすれば良い。And emitter wiring 19. When forming metal wiring having the structure of the present invention, such as the base wiring 20, the Al-Cu alloy layer 16. A 711-Cu alloy layer 18 is sequentially laminated on one TiN layer, and the laminated film is etched all at once by a dry etching method using a chlorine gas such as boron trichloride (B CAR) + carbon tetrachloride <CC, . All you have to do is pattern.
なおTiN層1層上7素< N2)l成るいはN2にア
ルゴン(Ar )をまぜた雰囲気中に於けるTiの反応
性スパッタによって形成することもできる。Note that it can also be formed by reactive sputtering of Ti in an atmosphere of 7 elements < N2) on one TiN layer or in an atmosphere containing N2 and argon (Ar).
(g) 発明の詳細
な説明したように本発明に於けるアルミニウム配線は、
アルミニウム若しくはアルミニウム合金からカるオーミ
ック・コンタクト層と、アルミニウム・銅若しくはアル
ミニウム・マグネシウム合金からなシアルミニウムのマ
イグレーションを防止した主導電層とがシリコンの拡散
を阻止する窒化チタン層によって分離されてなっている
O従ってオーミック・コンタクト層に溶は込んだシリコ
ンは該オーミック・コンタクト層内に閉じ込められて析
出し、主導電層内でのシリコンの析出は皆無になる。(g) As described in detail, the aluminum wiring in the present invention is
An ohmic contact layer made of aluminum or aluminum alloy and a main conductive layer made of aluminum-copper or aluminum-magnesium alloy that prevents migration of sialuminium are separated by a titanium nitride layer that prevents silicon diffusion. Therefore, the silicon that has melted into the ohmic contact layer is confined and precipitated within the ohmic contact layer, and no silicon is precipitated within the main conductive layer.
従って本発明によれば、低配線抵抗を有し、且つアルミ
ニウムのマイグレーションによる断線が防止されたアル
ミニウム配線が提供されるので、半導体装置の性能及び
信頼性が向上する。Therefore, according to the present invention, an aluminum wiring having low wiring resistance and preventing disconnection due to aluminum migration is provided, thereby improving the performance and reliability of a semiconductor device.
第1図はアルミニウム・銅若しくはアルミニウム・マグ
ネシウム合金配線に於けるシリコン結晶の析出状態を示
す模式図、第2図は従来のアルミニウム合金配線の断面
図、第3図は本発明に於ける金属配線の一実施例の断面
図、第4図は本発明の半導体装置に於ける一実施例の壁
部断面図であるQ
図に於て、11はn型コレクタ領域、12はp型ベース
領域、13はn上型エミッタ領域、14は二酸化シリコ
ン膜、15は多結晶シリコン層、16はアルミニウムー
銅合金・オーミック・コンタクト層、17は窒化チタン
層、18はアルミニウムー銅合金・主導電層、19はエ
ミッタ配線、20はベース配線、21はカバー絶縁膜を
示す○千 1 目
亭 ? 閉Fig. 1 is a schematic diagram showing the state of silicon crystal precipitation in aluminum-copper or aluminum-magnesium alloy wiring, Fig. 2 is a cross-sectional view of conventional aluminum alloy wiring, and Fig. 3 is a metal wiring according to the present invention. 4 is a cross-sectional view of a wall of an embodiment of the semiconductor device of the present invention. In the diagram, 11 is an n-type collector region, 12 is a p-type base region, 13 is an n-type emitter region, 14 is a silicon dioxide film, 15 is a polycrystalline silicon layer, 16 is an aluminum-copper alloy ohmic contact layer, 17 is a titanium nitride layer, 18 is an aluminum-copper alloy main conductive layer, 19 is the emitter wiring, 20 is the base wiring, and 21 is the cover insulating film. closed
Claims (1)
と、窒化チタンからなる第2層と、アルミニウムー銅・
合金若しくはアルミニウムーマグネシウム・合金からな
る第3層が、下部よシ順次積層されてなる金属配線を具
備してなることを特徴とする半導体装置。A first layer made of aluminum or an aluminum alloy, a second layer made of titanium nitride, and an aluminum-copper layer.
1. A semiconductor device comprising metal wiring in which a third layer made of an alloy or an aluminum-magnesium alloy is laminated sequentially from the bottom.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21015882A JPS59100565A (en) | 1982-11-30 | 1982-11-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21015882A JPS59100565A (en) | 1982-11-30 | 1982-11-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59100565A true JPS59100565A (en) | 1984-06-09 |
JPH0479146B2 JPH0479146B2 (en) | 1992-12-15 |
Family
ID=16584720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21015882A Granted JPS59100565A (en) | 1982-11-30 | 1982-11-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59100565A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6190445A (en) * | 1984-10-09 | 1986-05-08 | Nec Corp | Semiconductor device |
JPS63129662A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Semiconductor device |
JPH02159064A (en) * | 1988-12-13 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH04186728A (en) * | 1990-11-20 | 1992-07-03 | Nec Corp | Semiconductor integrated circuit device |
JP2019040975A (en) * | 2017-08-24 | 2019-03-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5272570A (en) * | 1975-12-15 | 1977-06-17 | Fujitsu Ltd | Formation of electrode of semiconductor deviced |
-
1982
- 1982-11-30 JP JP21015882A patent/JPS59100565A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5272570A (en) * | 1975-12-15 | 1977-06-17 | Fujitsu Ltd | Formation of electrode of semiconductor deviced |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6190445A (en) * | 1984-10-09 | 1986-05-08 | Nec Corp | Semiconductor device |
JPS63129662A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Semiconductor device |
JPH02159064A (en) * | 1988-12-13 | 1990-06-19 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH04186728A (en) * | 1990-11-20 | 1992-07-03 | Nec Corp | Semiconductor integrated circuit device |
JP2019040975A (en) * | 2017-08-24 | 2019-03-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US11652072B2 (en) | 2017-08-24 | 2023-05-16 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0479146B2 (en) | 1992-12-15 |
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