JP2723023B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2723023B2
JP2723023B2 JP5331411A JP33141193A JP2723023B2 JP 2723023 B2 JP2723023 B2 JP 2723023B2 JP 5331411 A JP5331411 A JP 5331411A JP 33141193 A JP33141193 A JP 33141193A JP 2723023 B2 JP2723023 B2 JP 2723023B2
Authority
JP
Japan
Prior art keywords
wiring
aluminum alloy
semiconductor device
contact hole
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5331411A
Other languages
Japanese (ja)
Other versions
JPH07193066A (en
Inventor
秀和 岡林
宏之 喜多村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5331411A priority Critical patent/JP2723023B2/en
Publication of JPH07193066A publication Critical patent/JPH07193066A/en
Application granted granted Critical
Publication of JP2723023B2 publication Critical patent/JP2723023B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の配線構造
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体装置のアルミニウム(A
l)・銅(Cu)系配線における上下接続孔(基板への
コンタクト孔及び多層配線のビア)内の配線は、図7に
コンタクト孔断面模式図を示したように、層内配線36
と同一組成のAl−Cu合金によって形成されてきた。
2. Description of the Related Art Conventionally, aluminum (A) of a semiconductor device has been used.
1) The wiring in the upper and lower connection holes (contact holes to the substrate and vias of the multilayer wiring) in the copper (Cu) -based wiring is, as shown in FIG.
And has been formed of an Al-Cu alloy having the same composition.

【0003】[0003]

【発明が解決しようとする課題】Al配線の微細化にと
もないエレクトロマイグレーション対策が益々重要とな
っている。従来、Cuの添加がAl配線のエレクトロマ
イグレーション対策として標準的に用いられてきた。し
かし、Cuの添加は、Al配線の耐食性を低下させるの
で、ドライエッチング法によるAl−Cu合金パターン
形成工程で、配線に腐食が生じやすくなる。従って、エ
レクトロマイグレーション耐性という観点からはCu濃
度が1〜4重量%程度のAl−Cu合金を使用すること
が望ましいにも関わらず、ドライエッチング時の腐食や
ドライエッチング性の低下を避けるため、0.5重量%
程度の低濃度合金を用いざるを得なかった。
With the miniaturization of Al wiring, measures against electromigration have become increasingly important. Conventionally, addition of Cu has been used as a standard measure against electromigration of Al wiring. However, since the addition of Cu lowers the corrosion resistance of the Al wiring, the wiring is likely to be corroded in the Al-Cu alloy pattern forming step by the dry etching method. Therefore, although it is desirable to use an Al—Cu alloy having a Cu concentration of about 1 to 4% by weight from the viewpoint of electromigration resistance, it is preferable to use 0% in order to avoid corrosion during dry etching and a decrease in dry etching property. 0.5% by weight
We had to use a low concentration alloy.

【0004】一方、もう一つの方法として、エレクトロ
マイグレーション耐性や動作速度を含む電気特性に応じ
部分的に異なる材質の金属を用いて配線を形成する方法
が特開昭63−253644号公報に記載されている。
しかし、同公報に記載されている様に同一平面の配線に
おいて高濃度にCuを含む部分を形成しようとする平面
配線内で局部的にCu濃度を変化させねばならず、現時
点では量産に適した方法は考え難い。また、配線への加
工前の膜の状態で部分的にCu高濃度領域を形成し得た
としても、上述のドライエッチングの問題に遭遇する。
たとえ、ドライエッチングの問題を克服できたとして
も、この方法では、同公報に記載されている様にボンデ
ィング部や電源線等設計上明らかにエレクトロマイグレ
ーション耐性が低い部分のみが対象になっており、その
部分をCu濃度の低い他の部分と同程度のエレクトロマ
イグレーション耐性を確保することを目的としたもので
あることが明らかである。従って、大部分の配線のエレ
クトロマイグレーション耐性は従来のままであり、その
配線に確率的に存在するエレクトロマイグレーション耐
性の低い箇所に対する対策は全く立てられていなかっ
た。
On the other hand, Japanese Patent Application Laid-Open No. 63-253644 discloses another method of forming a wiring by using a metal having a partially different material depending on electrical characteristics including electromigration resistance and operation speed. ing.
However, as described in the publication, it is necessary to locally change the Cu concentration in a plane wiring in which a portion containing Cu at a high concentration is to be formed in the wiring on the same plane, which is suitable for mass production at present. The method is hard to imagine. Further, even if a high-concentration Cu region can be partially formed in a state of a film before being processed into wiring, the problem of dry etching described above is encountered.
Even if the problem of dry etching can be overcome, this method targets only a portion having a clearly low electromigration resistance, such as a bonding portion or a power line, as described in the same publication. It is clear that this portion is intended to ensure the same level of electromigration resistance as the other portions having a low Cu concentration. Therefore, the electromigration resistance of most of the wirings remains the same as before, and no countermeasure has been taken at all for a portion of the wiring which has a low electromigration resistance stochastically.

【0005】本発明の目的は、これらの従来のAl−C
u系配線における問題点を大幅に改善した新規な配線構
造を提供することにある。
It is an object of the present invention to provide these conventional Al-C
It is an object of the present invention to provide a new wiring structure in which a problem in u-type wiring is greatly improved.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成するた
め、本発明は、上下接続孔内のAl合金の配線のCu濃
度を層内のAl合金配線のCu濃度より高くすることを
特徴とするものである。
In order to achieve the above object, the present invention is characterized in that the Cu concentration of the Al alloy wiring in the upper and lower connection holes is higher than the Cu concentration of the Al alloy wiring in the layer. Is what you do.

【0007】[0007]

【作用】本発明のAl−Cu合金配線構造を用いると、
Cuが加熱工程での熱拡散や実使用中でのエレクトロマ
イグレーションによってCu濃度の高い上下接続孔より
それに接続されている層内配線に輸送されるので、層内
配線のCu濃度が従来構造の場合より実質的に高められ
ている。従って、エレクトロマイグレーションやストレ
スマイグレーションに対する耐性が向上する。また、C
u濃度の接続孔形成には、化学機械研磨等の全面除去方
法を適用できるので、従来構造形成上の問題点も回避さ
れる。
When the Al-Cu alloy wiring structure of the present invention is used,
Since Cu is transported from the upper and lower connection holes having a high Cu concentration to the wiring in the layer connected thereto due to thermal diffusion in a heating step or electromigration in actual use, the Cu concentration in the wiring in the layer is the same as that of the conventional structure. Has been substantially enhanced. Therefore, resistance to electromigration and stress migration is improved. Also, C
In forming the connection hole having the u concentration, a method for removing the entire surface, such as chemical mechanical polishing, can be applied.

【0008】[0008]

【実施例】以下、本発明の実施例を図を用いて説明す
る。標準的な集積回路の製造技術を用いて、図1の断面
模式図に示したように、p型シリコン基板17にn+
純物領域に設けた後、シリコン酸化膜13を堆積し、n
+ 領域へのコンタクト孔14を開口する。次にチタニウ
ム(Ti)を全面に約600オングストロームの厚さに
堆積した後、窒素・水素混合ガス等窒化性雰囲気中で熱
処理を行い、シリコン基板に接するTiの一部とシリコ
ンの反応によって図2に示したようにTiシリサイド1
6をコンタクト自己整合的に形成するとともに、その表
面及び絶縁膜13上のTiを窒化チタニウム15に変換
する。次に、図3に示したようにCuを約46重量%含
みほぼCuAl2 組成のAl−Cu合金17を堆積し
た。次に標準的な化学的機械研磨(ケミカルメカニカル
ポリシュ:CMP)法を用いて絶縁膜13上のAl−C
u合金及び窒化チタニウム膜を除去することにより、図
4に示したように、窒化チタニウム15′と高濃度Cu
含有Al−Cu合金17′から構成されるコンタクト構
造が形成される。次に、図5に示したように、第一層配
線として、Cuを0.5重量%含むAl−Cu合金18
及び窒化チタニウム19よりなる積層構造配線を標準的
な方法によって形成する。さらに図6に示したように、
酸化シリコン系等の層間絶縁膜20を形成し、ビア(上
下層接続孔)を開口した後、前述のコンタクト孔内配線
形成と同様な方法を用いることにより、高濃度Cu含有
Al−Cu合金ビア配線21及び標準的なCu含有量の
Al−Cu合金22と窒化チタニウム23とによって構
成された第2層目の積層配線を形成することができる。
この際窒化チタニウム19の開口部において露出した部
分を除去したが、除去せずに残存させたままにしても構
わない。上述の第2の層配線形成方法を繰り返すことに
より3層以上の多層配線を形成することができる。本実
施例によって形成されたAl−Cu合金配線は、従来の
Al−0.5重量%Cuのみからなる配線に比して2倍
以上のエレクトロマイグレーション耐性を示した。上記
実施例においては、上下層接続孔内でのCu濃度を約4
6重量%のものについて示したが、数重量%の濃度にお
いても従来の0.5重量%Cu濃度の単一組成配線に比
してエレクトロマイグレーション耐性の改善が実現でき
た。また、Cuのほかにシリコン等の他の元素を添加し
ても、本発明の構造の有効性を損うものではない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Using manufacturing techniques standard integrated circuits, as shown in schematic cross-sectional view of FIG. 1, after providing the n + impurity region in the p-type silicon substrate 17, a silicon oxide film is deposited 13, n
A contact hole 14 to the + region is opened. Next, after titanium (Ti) is deposited on the entire surface to a thickness of about 600 angstroms, a heat treatment is performed in a nitriding atmosphere such as a mixed gas of nitrogen and hydrogen, and a reaction between part of Ti in contact with the silicon substrate and silicon causes the reaction shown in FIG. Ti silicide 1
6 is formed in a contact self-alignment manner, and Ti on the surface and the insulating film 13 is converted into titanium nitride 15. Next, as shown in FIG. 3, an Al—Cu alloy 17 containing approximately 46% by weight of Cu and substantially having a composition of CuAl 2 was deposited. Next, the Al-C on the insulating film 13 is formed using a standard chemical mechanical polishing (Chemical Mechanical Polish: CMP) method.
By removing the u-alloy and the titanium nitride film, as shown in FIG.
A contact structure composed of the contained Al-Cu alloy 17 'is formed. Next, as shown in FIG. 5, as the first layer wiring, an Al—Cu alloy 18 containing 0.5% by weight of Cu was used.
And a multilayer structure wiring made of titanium nitride 19 is formed by a standard method. Further, as shown in FIG.
After forming an interlayer insulating film 20 of silicon oxide or the like and opening vias (upper and lower layer connection holes), a high concentration Cu-containing Al-Cu alloy via It is possible to form a second-layer laminated wiring composed of the wiring 21 and the Al—Cu alloy 22 having a standard Cu content and the titanium nitride 23.
At this time, the portion exposed at the opening of the titanium nitride 19 was removed, but it may be left without being removed. By repeating the above-described second layer wiring forming method, a multilayer wiring of three or more layers can be formed. The Al-Cu alloy wiring formed according to the present example exhibited twice or more electromigration resistance as compared with the conventional wiring composed of only Al-0.5% by weight Cu. In the above embodiment, the Cu concentration in the upper and lower connection holes is set to about 4
Although the case of 6% by weight is shown, even at a concentration of several% by weight, the electromigration resistance can be improved as compared with the conventional single composition wiring having a Cu concentration of 0.5% by weight. Further, addition of other elements such as silicon in addition to Cu does not impair the effectiveness of the structure of the present invention.

【0009】[0009]

【発明の効果】以上説明したように、本発明によれば、
Al−Cu合金配線系の上下層接続孔内でのCu濃度を
高くすることにより、該上下層接続孔より層内配線へC
uが供給されるので、配線のマイグレーション耐性が改
善され、信頼性の高いAl−Cu系配線を形成すること
ができる。
As described above, according to the present invention,
By increasing the Cu concentration in the upper and lower layer connection holes of the Al-Cu alloy wiring system, C
Since u is supplied, the migration resistance of the wiring is improved, and a highly reliable Al—Cu-based wiring can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 1 is a schematic diagram of a cross section of a sample in a main manufacturing process in an example of the present invention.

【図2】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 2 is a schematic diagram of a sample cross section in a main manufacturing process according to an example of the present invention.

【図3】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 3 is a schematic diagram of a sample cross section in a main manufacturing process according to an example of the present invention.

【図4】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 4 is a schematic diagram of a sample cross section in a main manufacturing process in an example of the present invention.

【図5】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 5 is a schematic view of a cross section of a sample in a main manufacturing process in an example of the present invention.

【図6】本発明の実施例における主要製造工程での試料
断面の模式図である。
FIG. 6 is a schematic diagram of a cross section of a sample in a main manufacturing process in an example of the present invention.

【図7】従来の構造の断面模式図である。FIG. 7 is a schematic sectional view of a conventional structure.

【符号の説明】[Explanation of symbols]

11、31 シリコン基板 12、32 n+ 領域 13、33 シリコン酸化膜 14 コンタクト孔 15、15′、19、23、35 窒化チタニウム 16、34 チタンシリサイド 17、17′、21 アルミニウム・銅合金(高銅濃
度) 18、22、36 アルミニウム・銅合金(低銅濃度)
11, 31 Silicon substrate 12, 32 n + region 13, 33 Silicon oxide film 14 Contact hole 15, 15 ', 19, 23, 35 Titanium nitride 16, 34 Titanium silicide 17, 17', 21 Aluminum / copper alloy (high copper Concentration) 18, 22, 36 Aluminum / copper alloy (low copper concentration)

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板へのコンタクト孔内配線および第1
層配線のそれぞれにアルミニウム合金を有する半導体装
置において、コンタクト孔内配線のアルミニウム合金は
コンタクト孔内の全領域において第1層配線のアルミニ
ウム合金中の銅濃度よりも高い濃度の銅を含有し、該コ
ンタクト孔内配線のアルミニウム合金と第1層配線のア
ルミニウム合金はコンタクト孔の上端面において接する
ことを特徴とする半導体装置。
A wiring in a contact hole to a substrate and a first wiring.
A semiconductor device having an aluminum alloy in each of the layer wirings
The aluminum alloy of the wiring in the contact hole is
The aluminum of the first layer wiring is formed in the entire area inside the contact hole.
Containing a higher concentration of copper than the copper concentration in the
Aluminum alloy for wiring in contact hole and
Luminium alloy contacts at the top surface of the contact hole
A semiconductor device characterized by the above-mentioned.
【請求項2】 多層配線における上下層間の接続孔内配
線および層内配線のそれぞれにアルミニウム合金を有す
る多層配線構造の半導体装置において、接続孔内配線の
アルミニウム合金は接続孔内の全領域において上層配線
および下層配線のいずれのアルミニウム合金中の銅濃度
よりも高い濃度の銅を含有し、該接続孔内配線のアルミ
ニウム合金と前記上層配線、下層配線のアルミニウム合
金はそれぞれ接続孔の上端面、下端面において接するこ
とを特徴とする半導体装置。
2. Arrangement in a connection hole between upper and lower layers in a multilayer wiring.
Aluminum alloy for each wire and in-layer wiring
In a semiconductor device having a multilayer wiring structure,
Aluminum alloy is the upper layer wiring in the entire area of the connection hole
Copper concentration in aluminum alloys for both lower and upper wiring
Containing copper at a higher concentration than the aluminum
Alloy and the aluminum of the upper wiring and the lower wiring
Gold contacts the top and bottom surfaces of the connection holes, respectively.
A semiconductor device characterized by the following.
【請求項3】 基板へのコンタクト孔内配線、多層配線3. Wiring in a contact hole to a substrate, multilayer wiring
における上下層間の接続孔内配線および層内配線のそれIn the connection hole between the upper and lower layers and that in the layer
ぞれにアルミニウム合金を有する多層配線構造の半導体Semiconductors with multi-layer wiring structures each having an aluminum alloy
装置において、In the device, コンタクト孔内配線のアルミニウム合金はコンタクト孔Aluminum alloy for wiring in contact hole is contact hole
内の全領域において第1層配線のアルミニウム合金中のIn the aluminum alloy of the first layer wiring
銅濃度よりも高い濃度の銅を含有し、該コンタクト孔内Contains copper at a concentration higher than the copper concentration, and
配線のアルミニウム合金と第1層配線のアルミニウム合Aluminum alloy of wiring and aluminum of first layer wiring
金はコンタクト孔の上端面において接しており、Gold is in contact with the upper end surface of the contact hole, 接続孔内配線のアルミニウム合金は接続孔内の全領域にThe aluminum alloy of the wiring in the connection hole covers the entire area in the connection hole
おいて上層配線および下層配線のいずれのアルミニウムAluminum for both upper and lower wiring
合金中の銅濃度よりも高い濃度の銅を含有し、該接続孔Containing copper at a higher concentration than the copper concentration in the alloy,
内配線のアルミニウム合金と前記上層配線、下層配線のThe inner wiring aluminum alloy and the upper wiring, the lower wiring
アルミニウム合金はそれぞれ接続孔の上端面、下端面にAluminum alloy on the upper and lower surfaces of the connection hole respectively
おいて接することを特徴とする半導体装置。A semiconductor device, which is in contact with the semiconductor device.
【請求項4】 請求項1から請求項3のいずれかに記載4. The method according to claim 1, wherein
の半導体装置における前記コンタクト孔内配線あるいはWiring in the contact hole in the semiconductor device of
前記接続孔内配線のアルミニウム合金に含有された銅Copper contained in the aluminum alloy of the wiring in the connection hole
が、熱拡散あるいはエレクトロマイグレーションによっCan be caused by heat diffusion or electromigration.
て層内配線中に輸送されたことを特徴とする半導体装Semiconductor device transported into the intra-layer wiring
置。Place.
【請求項5】 前記コンタクト孔内配線あるいは前記
続孔内配線のアルミニウム合金としてアルミニウムと銅
の金属間化合物を用いる請求項1から請求項4のいずれ
かに記載の半導体装置。
5. The one of claims 1 to use aluminum and copper intermetallic compound as the aluminum alloy of the contact hole wiring or the contact <br/> the connection hole interconnection of claim 4
13. A semiconductor device according to claim 1.
【請求項6】 不純物領域を形成した半導体基板上に絶6. A semiconductor substrate having an impurity region formed thereon.
縁膜を堆積する工程と、該絶縁膜に前記不純物領域に達Depositing an edge film and reaching the impurity region in the insulating film.
するコンタクト孔を開口する工程と、該コンタクト孔にOpening a contact hole to be formed;
均一な濃度分布の銅を含有するアルミニウム合金を埋めFill aluminum alloy containing copper with uniform concentration distribution
込み形成する工程と、前記コンタクト孔の上端面よりもAnd forming the contact hole from the upper end surface of the contact hole.
上側の前記アルミニウム合金を化学的機械研磨により除The upper aluminum alloy is removed by chemical mechanical polishing.
去する工程と、前記コンタクト孔内のアルミニウム合金Removing the aluminum alloy in the contact hole
よりも銅濃度が低いアルミニウム合金を用いて前記絶縁Insulation using aluminum alloy with lower copper concentration than
膜上に第1層配線を形成する工程と、を有することを特Forming a first layer wiring on the film.
徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device.
【請求項7】 多層配線構造を有する半導体装置の製造7. Manufacturing of a semiconductor device having a multilayer wiring structure.
方法において、アルミニウム合金からなる下層配線を形In the method, the lower wiring made of aluminum alloy is formed.
成した後に該下層配線上に層間絶縁膜を形成する工程Forming an interlayer insulating film on the lower wiring after the formation
と、該層間絶縁膜に上下層の接続孔を開口する工程と、Opening a connection hole in the upper and lower layers in the interlayer insulating film;
該接続孔に均一な濃度分布で銅を含有しかつ前記下層配The connection hole contains copper in a uniform concentration distribution and the lower layer
線のアルミニウム合金よりも銅濃度が高いアルミニウムAluminum with higher copper concentration than aluminum alloy of wire
合金を埋め込み形成する工程と、前記接続孔上端面よりBurying and forming an alloy; and
も上側の前記アルミニウム合金を化学的機械研磨によりThe upper aluminum alloy by chemical mechanical polishing
除去する工程と、前記接続孔内のアルミニウム合金よりRemoving the aluminum alloy in the connection hole
も銅濃度が低いアルミニウム合金を用いて前記層間絶縁The interlayer insulation using aluminum alloy with low copper concentration
膜上に上層配線を形成する工程と、を有することを特徴Forming an upper layer wiring on the film.
とする半導体装置の製造方法。Manufacturing method of a semiconductor device.
JP5331411A 1993-12-27 1993-12-27 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2723023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5331411A JP2723023B2 (en) 1993-12-27 1993-12-27 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5331411A JP2723023B2 (en) 1993-12-27 1993-12-27 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH07193066A JPH07193066A (en) 1995-07-28
JP2723023B2 true JP2723023B2 (en) 1998-03-09

Family

ID=18243387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5331411A Expired - Lifetime JP2723023B2 (en) 1993-12-27 1993-12-27 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2723023B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4117101B2 (en) * 2000-08-30 2008-07-16 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2748443B2 (en) * 1988-10-22 1998-05-06 日本電気株式会社 Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH07193066A (en) 1995-07-28

Similar Documents

Publication Publication Date Title
JP4571781B2 (en) Semiconductor device and manufacturing method thereof
US5904556A (en) Method for making semiconductor integrated circuit device having interconnection structure using tungsten film
US7679193B2 (en) Use of AIN as cooper passivation layer and thermal conductor
KR0172205B1 (en) Semiconductor device and method of manufacturing the same
US5070036A (en) Process for contacting and interconnecting semiconductor devices within an integrated circuit
TW503493B (en) Copper pad structure
JP2003031575A (en) Semiconductor device and manufacturing method therefor
JPH0778821A (en) Semiconductor device and its manufacture
JPH04271144A (en) Semiconductor device
JP3177968B2 (en) Semiconductor device and manufacturing method thereof
JP3149846B2 (en) Semiconductor device and manufacturing method thereof
US6624516B2 (en) Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer
US4977440A (en) Structure and process for contacting and interconnecting semiconductor devices within an integrated circuit
US6753259B2 (en) Method of improving the bondability between Au wires and Cu bonding pads
US6790778B1 (en) Method for capping over a copper layer
JP2001203205A (en) Semiconductor device and its manufacturing method
JP2000068269A (en) Semiconductor device and manufacture thereof
JP2723023B2 (en) Semiconductor device and manufacturing method thereof
US6479898B1 (en) Dielectric treatment in integrated circuit interconnects
US6445070B1 (en) Coherent carbide diffusion barrier for integrated circuit interconnects
US6462417B1 (en) Coherent alloy diffusion barrier for integrated circuit interconnects
JPH11102911A (en) Semiconductor device and its manufacture
JP3368629B2 (en) Semiconductor device
JPH11283981A (en) Semiconductor device and manufacture thereof
JP2006024968A (en) Semiconductor device and manufacturing method of same

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19971028

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071128

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081128

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081128

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091128

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091128

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101128

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111128

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111128

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121128

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121128

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131128

Year of fee payment: 16

EXPY Cancellation because of completion of term