JP2006024968A - Semiconductor device and manufacturing method of same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a high reliability to use with a large current and for a long time and includes wiring having a high resistance to corrosion, and to provide a manufacturing method of the same. <P>SOLUTION: A wiring layer 33 is formed, which has a laminated structure in which an aluminum wiring layer 32 being better resistant to oxygen than that of a copper wiring layer 30 is stacked on the copper wiring layer 30. Therefore, since the wiring layer 33 includes the copper wiring layer therein, a breaking of wire due to electromigration is not easily occurred and a reliability to use with a large current and for a long time can be improved. Additionally, even if a processing in an atmosphere including oxygen is performed under the condition that the formed wiring layer 33 is exposed, the wiring layer 33 is not easily corroded. That is to say, it is possible to obtain the wiring layer 33 which has a high reliability to use with a large current and for a long time and has a high resistance to corrosion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a technique for forming internal wiring of a semiconductor device.

Aluminum wiring is used as the internal wiring of the LSI chip. Since aluminum (Al) can form an alloy with gold (Au) at a relatively low temperature, it has high reliability when bonding a gold wire. However, since the aluminum wiring is easily broken by electromigration, the reliability is low when a large current flows or when it is used for a long time.

For this reason, a technique using copper or a copper alloy as wiring inside the LSI chip has been proposed. If copper or a copper alloy is used as the wiring, disconnection due to electromigration is unlikely to occur, so that reliability when a large current is passed or used for a long time can be improved.

7A to 8B show a part of a conventional manufacturing process when copper is used as the wiring. First, as shown in FIG. 7A, a wiring groove 2a is provided in the upper part of the interlayer film 2, and a barrier metal layer 4 and a copper wiring layer 6 made of titanium nitride (TiN) or the like are formed thereon in this order. Next, as shown in FIG. 7B, the wiring 8 is formed by removing unnecessary portions of the barrier metal layer 4 and the copper wiring layer 6 using a CMP (chemical mechanical polishing) method or the like.

Next, low-temperature heat treatment such as annealing for adjusting crystal grains of the copper wiring layer 6 and heat treatment using hydrogen for removing crystal defects is performed. Thereafter, as shown in FIG. 7C, a passivation film 10 is formed thereon.

Next, as shown in FIG. 8A, a resist 12 having a predetermined shape is formed on the passivation film 10, and etching is performed using the resist 12 as a mask to expose a part of the surface of the wiring 8 as a pad portion 8a. Next, after removing the resist 12 by an ashing process, as shown in FIG. 8B, the wire 14 is bonded to the pad portion 8a.

However, the method for manufacturing a wiring using copper or a copper alloy has the following problems. Although the above-described annealing treatment and heat treatment using hydrogen are performed in an inert gas atmosphere, in reality, some oxygen is involved. On the other hand, copper and copper alloys are more easily corroded by oxygen or the like than aluminum. For this reason, in the above-mentioned low temperature heat treatment performed with the copper wiring layer 6 exposed (see FIG. 7B), the exposed copper wiring layer 6 is corroded by oxygen, and in the worst case, the wiring is cut.

Further, since the ashing process described above is performed using oxygen plasma, when the resist 12 is removed by ashing, the exposed pad portion 8a (see FIG. 8A) is corroded by oxygen.

That is, the conventional method of manufacturing a wiring using copper or copper alloy has a problem that the wiring is corroded and the reliability of the wiring is lowered.

The present invention solves such problems, and provides a semiconductor device having a wiring having high reliability when flowing a large current or being used for a long period of time and having high reliability against corrosion, and a method for manufacturing the same. The purpose is to do.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film, and is formed once on the first interlayer insulating film having the first wiring layer. A step of forming a second interlayer insulating film by a continuous process, a step of providing a wiring recess on the second interlayer insulating film so as not to reach the first interlayer insulating film, and a bottom of the wiring recess, A step of providing a contact hole for connecting the first interlayer insulating film to the first wiring layer, a step of providing a second wiring layer on the wiring recess and the contact hole, and polishing the second wiring layer by CMP. The process which has a process to do.

  Further, in the above configuration, the step of providing a barrier metal layer on the wiring recess and the contact hole before the step of providing the second wiring layer, and the step of polishing the second wiring layer by the CMP method, The second wiring layer is polished by CMP until the barrier metal layer is exposed, and then the second interlayer insulating film is formed using a photoresist having a pattern obtained by inverting the pattern used in the step of forming the wiring recess. The structure which has the process of removing the barrier metal layer which remains on may be sufficient.

  The semiconductor device of the present invention is a semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film, and is formed on a second interlayer of a uniform material on the first interlayer insulating film having the first wiring layer. An insulating film, a wiring recess provided on the second interlayer insulating film so as not to reach the first interlayer insulating film, and a bottom of the wiring recess connected to the first wiring layer of the first interlayer insulating film And a second wiring layer formed so as to fill the contact hole provided for this purpose.

  Alternatively, the semiconductor device of the present invention is a semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film, and is formed of a uniform material on the first interlayer insulating film having the first wiring layer. A second interlayer insulating film, a wiring recess provided on the second interlayer insulating film so as not to reach the first interlayer insulating film, and a first wiring layer of the first interlayer insulating film at the bottom of the wiring recess A second wiring layer formed so as to fill a contact hole provided for connection, a second interlayer insulating film and a passivation film on the second wiring layer, and an opening of the passivation film on the second wiring layer And a pad portion made of a conductive layer provided.

  In the above configuration, a conductive layer may be provided so as to substantially cover the second wiring layer, and the conductive layer exposed from the opening may be a pad portion.

  In the above configuration, the copper alloy may be a copper / magnesium alloy having a magnesium ratio of about 1 percent to about 5 percent.

  In the above structure, the conductive layer is aluminum, an aluminum / silicon alloy having a silicon ratio of about 0.5 to about 2%, a silicon ratio of about 0.5 to about 1.5%, and a copper ratio. An aluminum / silicon / copper alloy of about 0.5% to about 1.5% or an aluminum / copper alloy having a copper ratio of about 0.5% to about 3% may be included.

  The configuration of the present invention may be as follows.

  For example, as a first modification, the semiconductor device manufacturing method forms a first conductor layer containing copper, and the second is less corrosive in an atmosphere containing a copper corrosive substance than the first conductor layer. A first conductor layer and a second conductor layer that substantially covers the first conductor layer by forming the first conductor layer on the first conductor layer. The structure which forms the wiring layer of a structure may be sufficient.

  Since the wiring layer has the first conductor layer containing copper, disconnection due to electromigration hardly occurs, and the reliability when a large current flows or when used for a long time can be improved.

In addition, since the wiring layer having the laminated structure in which the second conductor layer, which is less corroded by the copper corrosive substance than the first conductor layer, is formed on the first conductor layer, is formed. Even when the treatment is performed in an atmosphere containing a copper corrosive substance with the wiring layer exposed after the layer formation, the wiring layer is hardly corroded. It is possible to obtain a wiring having high reliability when flowing a large current or when used for a long period of time and having high reliability against corrosion.

As a second modification, in the first modification, a step of forming an insulating film, a step of forming a wiring recess in the insulating film by etching, and a first conductor layer having a predetermined pattern in the wiring recess. A step of forming, a step of forming a second conductor layer on the first conductor layer and the insulating film formed in a predetermined pattern, and a step of forming the second conductor layer in a predetermined pattern by etching And a mask having a pattern obtained by inverting the mask used in the step of forming the concave portion for wiring of the predetermined pattern in the insulating film by etching as a mask used in the step of forming the second conductor layer in the predetermined pattern by etching. It may be used.

  By forming the wiring layer using a CMP (Chemical Mechanical Polishing) method, it is possible to finely process the wiring layer containing copper, which is difficult to perform anisotropic etching. In addition, as a mask used in the step of forming the second conductor layer in a predetermined pattern, a mask having a pattern obtained by inverting the mask used in the step of forming the wiring recess of the predetermined pattern in the insulating film can be easily and A second conductor layer may be formed that substantially completely covers the first conductor layer.

  As modified example 3, in modified example 1, a step of forming an insulating film, a step of forming a wiring recess in a predetermined pattern in the insulating film, and a step of forming a barrier metal layer on the insulating film including the wiring recess The first conductor layer is formed on the barrier metal layer by polishing, and the first conductor layer is removed by polishing until the barrier metal layer in a portion other than the wiring recess is exposed. Forming a conductive layer in a predetermined pattern, forming a second conductive layer on the first conductive layer and the exposed barrier metal layer formed in the predetermined pattern, and second conductive Forming the body layer and the exposed barrier metal layer in a predetermined pattern.

  By forming a barrier metal layer between the first conductor layer containing copper and the insulating film, copper can be prevented from diffusing into the insulating layer.

  In the step of forming the first conductor layer having a predetermined pattern by polishing, the barrier metal layer that is harder to polish than the first conductor layer is left without polishing, and then the second conductor is formed. Since the barrier metal layer is simultaneously formed in the predetermined pattern when the layer is formed in the predetermined pattern, dishing is performed on the first conductive layer in the step of forming the first conductive layer having the predetermined pattern by polishing. Less likely to occur. Therefore, a wiring layer having a more uniform thickness can be obtained. That is, it is possible to prevent the copper contained in the wiring layer from diffusing into the insulating layer and to obtain a wiring layer having a more uniform thickness that is less likely to cause dishing.

As Modification 4, in the above-described modification, the treatment performed in the atmosphere containing the copper corrosive substance may be a low-temperature heat treatment with the wiring layer exposed. For example, when performing low-temperature heat treatment such as annealing for adjusting crystal grains of the first wiring layer or heat treatment using hydrogen for removing crystal defects, the first wiring layer is the second wiring layer. Therefore, the first wiring layer is not corroded by the entrained oxygen.

As a modified example 5, in any one of the modified examples 1 to 3, the treatment performed in the atmosphere containing the copper corrosive substance may be a photoresist ashing process in a state where the wiring layer is exposed. For example, even if the photoresist used in the step of exposing the pad portion for external wiring in the wiring layer is ashed using oxygen plasma, the first wiring layer is the second wiring. Since it is covered with the layer, the first wiring layer is not corroded by oxygen.

Further, as a sixth modification, in the above-described modification, the second conductor layer may be a metal layer made of aluminum or an aluminum alloy. Since the wiring layer having a laminated structure covering the first conductor layer is formed by a metal layer made of aluminum or aluminum alloy that is easier to alloy with gold than the first conductor layer, the wiring layer Of these, the gold (Au) wire can be easily and reliably connected to the pad portion for external wiring.

In the semiconductor device of Modification 7, the wiring layer includes a first conductor layer made of copper or a copper alloy substantially free of aluminum, and a first conductor layer made of aluminum or an aluminum alloy substantially. And a second conductor layer arranged so as to cover it may be a laminated structure. Since the wiring layer has the first conductor layer made of copper or a copper alloy substantially free of aluminum, disconnection due to electromigration hardly occurs, and reliability when a large current flows or when it is used for a long time Can be improved. In addition, since the first conductor layer is substantially covered with the second conductor layer made of aluminum or aluminum alloy which is superior in moisture resistance and corrosion resistance compared to the first conductor layer, the wiring layer Its own moisture resistance and corrosion resistance are high.

As described above, according to the configuration of the present invention, it is possible to obtain a semiconductor device that is highly reliable when flowing a large current or used for a long period of time and has high moisture resistance and corrosion resistance.

FIG. 6 shows a part of a cross-sectional configuration of a semiconductor device 18 according to an embodiment of the present invention. The semiconductor device 18 includes a wiring layer 33 formed on the interlayer film 24 that is an insulating film. The wiring layer 33 includes a barrier metal layer 28, a copper wiring layer 30 as a first conductor layer, another barrier metal layer 31, and an aluminum wiring layer 32 as a second conductor layer.

The copper wiring layer 30 is made of copper or a copper alloy substantially free of aluminum, for example, a copper-magnesium (Cu—Mg) alloy or the like, and has a barrier in the wiring recess 24 a formed on the interlayer film 24. It is formed via the metal layer 28.

The component ratio of the copper-magnesium (Cu—Mg) alloy is not particularly limited. For example, the magnesium ratio may be about 1 percent to about 5 percent.

An aluminum wiring layer 32 is formed through a barrier metal layer 31 so as to cover the upper surfaces of the copper wiring layer 30 and the barrier metal layer 28. The aluminum wiring layer 32 is made of aluminum or an aluminum alloy, for example, an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy, an aluminum-copper (Al-Cu) alloy, or the like. ing.

The component ratio of the aluminum-silicon (Al-Si) alloy is not particularly limited. For example, the ratio of silicon may be about 0.5 percent to about 2 percent.

The component ratio of the aluminum / silicon / copper (Al—Si—Cu) alloy is not particularly limited. For example, the silicon ratio is about 0.5 to about 1.5 percent, The copper ratio may be about 0.5 percent to about 1.5 percent.

Further, the component ratio of the aluminum-copper (Al-Cu) alloy is not particularly limited. For example, the ratio of copper may be about 0.5 percent to about 3 percent.

A passivation film 36 is formed so as to cover the wiring layer 33 and the interlayer film 24. The passivation film 36 is provided with an opening 36 a that reaches the pad portion 33 a of the wiring layer 33. A wire 40 made of gold (Au) is connected to the pad portion 33a.

Note that another interlayer film 20 is formed below the interlayer film 24, and another wiring layer 22 is formed above the interlayer film 20. The wiring layer 22 and the wiring layer 33 are connected via a contact hole 24b.

Thus, in the semiconductor device 18, the wiring layer 33 has a laminated structure including the copper wiring layer 30 and the aluminum wiring layer 32 disposed so as to substantially cover the copper wiring layer 30.

Therefore, since the wiring layer 33 includes the copper wiring layer 30, disconnection due to electromigration hardly occurs, and the reliability when a large current flows or when used for a long time can be improved.

In addition, since the copper wiring layer 30 is substantially covered with the aluminum wiring layer 32 that is superior in moisture resistance and corrosion resistance compared to the copper wiring layer 30, the wiring layer 33 itself has high moisture resistance and corrosion resistance. That is, as shown in FIG. 6, it is possible to ensure moisture resistance and corrosion resistance even though the pad portion 33a is exposed.

That is, the semiconductor device 18 has high reliability when flowing a large current or when used for a long period of time, and has high moisture resistance and corrosion resistance.

1A to 5B are cross-sectional views for explaining a method for manufacturing the semiconductor device 18. A method for manufacturing the semiconductor device 18 will be described with reference to FIGS. 1A to 5B and FIG.

As shown in FIG. 1A, first, a structure in which a wiring layer 22 is formed on an interlayer film 20 provided on a semiconductor substrate (not shown) is prepared. The wiring layer 22 may be formed by any method, for example, by using a CMP (Chemical Mechanical Polishing) method or the like. The material of the wiring layer 22 is not particularly limited. For example, the wiring layer 22 can be formed of a copper or copper alloy layer whose lower surface and side surfaces are covered with a barrier metal layer.

Next, an interlayer film 24 is formed thereon. The interlayer film 24 is formed, for example, by depositing silicon oxide using a CVD method (chemical vapor deposition method) or the like.

Next, as shown in FIG. 1B, a wiring recess 24 a is formed on the interlayer film 24. In order to form the wiring recess 24a, a photoresist 26 having a predetermined shape is formed on the interlayer film 24, and RIE (reactive ion etching) is performed using the photoresist 26 as a mask.

Thereafter, the photoresist 26 is removed, and a contact hole 24b is formed using another photoresist (not shown) as shown in FIG. 2A.

Next, a barrier metal layer 28 is formed thereon, as shown in FIG. 2B. The material of the barrier metal layer 28 is not particularly limited. For example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like may be used. Further, the method for forming the barrier metal layer 28 is not particularly limited, but for example, a sputtering method or a CVD method may be used.

Next, a copper wiring layer 30 is formed on the barrier metal layer 28 as shown in FIG. 3A. Although the formation method of the copper wiring layer 30 is not specifically limited, For example, it can form using the plating method and CVD method.

Thus, by forming the barrier metal layer 28 between the copper wiring layer 30 (first conductor layer containing copper) and the interlayer film 24 (insulating film), the copper of the copper wiring layer 30 becomes the interlayer film. It is possible to prevent diffusion to 24, which is convenient.

Next, the copper wiring layer 30 is polished from above by using a CMP method. As shown in FIG. 3B, the polishing is finished when the upper surface of the barrier metal layer 28 formed in a portion other than the wiring recess 24a is exposed. By this polishing process, the copper wiring layer 30 is patterned into a predetermined shape.

Next, as shown in FIG. 4A, another barrier metal layer 31 and an aluminum wiring layer 32 are overlaid in this order. The material and formation method of the barrier metal layer 31 are not particularly limited. For example, the barrier metal layer 31 may be formed using the same material as the barrier metal layer 28 and using the same formation method as the barrier metal layer 28. Can do. Further, the method for forming the aluminum wiring layer 32 is not particularly limited, but for example, it is formed using a sputtering method or the like.

Thus, the copper wiring layer 30 is formed by forming the barrier metal layer 31 between the copper wiring layer 30 (first conductor layer containing copper) and the aluminum wiring layer 32 (second conductor layer). It is possible to prevent alloying due to mutual contact between copper and aluminum of the aluminum wiring layer 32, which is advantageous.

Next, as shown in FIG. 4B, the aluminum wiring layer 32, the barrier metal layer 31, and the barrier metal layer 28 are patterned into a predetermined shape. In order to pattern the aluminum wiring layer 32, the barrier metal layer 31, and the barrier metal layer 28 into a predetermined shape, a photoresist 34 having a predetermined shape is formed on the aluminum wiring layer 32, and RIE (reaction) is performed using the photoresist 34 as a mask. Ion etching). The photoresist 34 is a photoresist having a pattern obtained by inverting the photoresist 26 (see FIG. 1B) used for forming the wiring recess 24a.

Thus, the wiring layer 33 having a structure in which the barrier metal layer 28, the copper wiring layer 30, the barrier metal layer 31, and the aluminum wiring layer 32 are laminated in this order is formed.

After the wiring layer 33 is formed, low-temperature heat treatment such as annealing for adjusting crystal grains of the copper wiring layer 30 or heat treatment using hydrogen for removing crystal defects is performed. These treatments are performed in an inert gas atmosphere, but actually, oxygen, which is a copper corrosive substance, is slightly involved.

Next, as shown in FIG. 5A, a passivation film 36 is formed so as to cover the wiring layer 33 and the interlayer film 24. The material of the passivation film 36 is not particularly limited. For example, a silicon nitride film or the like may be used. Further, the method for forming the passivation film 36 is not particularly limited, but, for example, a CVD method or the like can be used.

Next, as shown in FIG. 5B, a photoresist 38 having a predetermined shape is formed on the passivation film 36, and RIE is performed using the photoresist 38 as a mask, thereby providing an opening 36a in the passivation film 36. Thereby, a part of the surface of the wiring layer 33 is exposed. This exposed portion is the pad portion 33a.

Next, the resist 38 is removed by ashing (ashing). The ashing process is performed using oxygen plasma.

Next, as shown in FIG. 6, the wire 40 is bonded to the pad portion 33a. In this way, the semiconductor device 18 is manufactured.

Thus, in this manufacturing method, the copper wiring layer 30 is formed, and the copper wiring layer 30 is formed on the copper wiring layer 30 by forming the aluminum wiring layer 32 that is less corroded by oxygen than the copper wiring layer 30. 30 and an aluminum wiring layer 32 that substantially covers the copper wiring layer 30 are formed.

Therefore, since the wiring layer 33 includes the copper wiring layer 30, disconnection due to electromigration hardly occurs, and the reliability when a large current flows or when used for a long time can be improved.

Further, since the wiring layer 33 having a laminated structure in which the aluminum wiring layer 32 having less corrosion due to oxygen than the copper wiring layer 30 is formed on the copper wiring layer 30 is formed, the wiring layer 33 is formed after the wiring layer 33 is formed. Even when the treatment is performed in an atmosphere containing oxygen in an exposed state, the wiring layer 33 is hardly corroded.

That is, it is possible to obtain the wiring layer 33 having high reliability when flowing a large current or when used for a long period of time and having high reliability against corrosion.

Further, in this manufacturing method, a step of forming an interlayer film 24, a step of forming a wiring recess 24a of a predetermined pattern in the interlayer film 24 by etching, and a copper wiring layer 30 of a predetermined pattern in the wiring recess 24a. An etching process including a step of forming, a step of forming an aluminum wiring layer 32 on the copper wiring layer 30 and the interlayer film 24 formed in a predetermined pattern, and a step of forming the aluminum wiring layer 32 in a predetermined pattern by etching. As a photoresist 34 used in the process of forming the aluminum wiring layer 32 in a predetermined pattern by etching, a photoresist having a pattern obtained by inverting the photoresist 26 used in the process of forming the wiring recess 24a of the predetermined pattern in the interlayer film 24 by etching is used. I use it.

That is, by forming the wiring layer 33 using the CMP (Chemical Mechanical Polishing) method, it is possible to finely process the wiring layer 33 containing copper, which is difficult to perform anisotropic etching.

Further, as the photoresist 34 used in the step of forming the aluminum wiring layer 32 in a predetermined pattern, a photoresist having a pattern obtained by inverting the photoresist 26 used in the step of forming the wiring recess 24a of the predetermined pattern in the interlayer film 24 is used. Thus, the aluminum wiring layer 32 that substantially and completely covers the copper wiring layer 30 can be formed.

In this manufacturing method, the step of forming the interlayer film 24, the step of forming the wiring recesses 24a having a predetermined pattern in the interlayer film 24, and the barrier metal layer 28 on the interlayer film 24 including the wiring recesses 24a are formed. Forming the copper wiring layer 30 on the barrier metal layer 28, and removing the copper wiring layer 30 by polishing until a portion of the barrier metal layer 28 other than the wiring recess 24a is exposed. The step of forming the copper wiring layer 30 in a predetermined pattern, the step of forming the aluminum wiring layer 32 on the copper wiring layer 30 formed in the predetermined pattern and the exposed barrier metal layer 28, the aluminum wiring layer 32 and the exposed Forming the barrier metal layer 28 in a predetermined pattern.

Therefore, by forming the barrier metal layer 28 between the copper wiring layer 30 and the interlayer film 24, it is possible to prevent copper contained in the copper wiring layer 30 from diffusing into the interlayer film 24.

Further, in the step of forming the copper wiring layer 30 having a predetermined pattern by polishing, the barrier metal layer 28 that is hard to be polished as compared with the copper wiring layer 30 is left without polishing, and then the aluminum wiring layer 32 is formed into a predetermined pattern. At the time of formation, the barrier metal layer 28 is formed in a predetermined pattern at the same time, so that dishing is less likely to occur in the copper wiring layer 30 in the step of forming the copper wiring layer 30 of the predetermined pattern by polishing. Therefore, the wiring layer 33 having a more uniform thickness can be obtained.

That is, it is possible to prevent the copper contained in the wiring layer 33 from diffusing into the interlayer film 24 and to obtain the wiring layer 33 having a more uniform thickness that is less likely to cause dishing.

Incidentally, according to the conventional manufacturing method, as shown in FIG. 7B, unnecessary portions of the barrier metal layer 4 and the copper wiring layer 6 are simultaneously removed by using the CMP method. As described above, since the copper wiring layer 6 is more easily polished than the barrier metal layer 4, dishing (a concave recess) 6 a is formed on the copper wiring layer 6 in such a conventional method. End up. In particular, the dishing becomes deep in a portion where the projected area of the wiring is large, such as the pad portion 8a. For this reason, a portion in which the thickness of the wiring 8 is considerably thin is generated, resulting in inconvenience such as a decrease in the reliability of the wiring.

In the manufacturing method according to the present embodiment, the low temperature heat treatment in the state where the wiring layer 33 is exposed is included as the treatment performed in the atmosphere containing oxygen.

Therefore, when performing low-temperature heat treatment such as annealing for adjusting crystal grains of the copper wiring layer 30 or heat treatment using hydrogen for removing crystal defects, the copper wiring layer 30 is covered with the aluminum wiring layer 32. Therefore, the copper wiring layer 30 is not corroded by the oxygen involved in such processing.

In this manufacturing method, the ashing process of the photoresist in the state where the wiring layer 33 is exposed is included as the process performed in the atmosphere containing oxygen.

Therefore, even if the photoresist 38 used in the process of exposing the pad portion 33a for bonding the wire 40 which is an external wiring is subjected to an ashing process using oxygen plasma, the copper wiring layer 30 is made of an aluminum wiring. Since it is covered with the layer 32, the exposed copper wiring layer 30 is not corroded by oxygen.

In this manufacturing method, the aluminum wiring layer 32 is made of aluminum or an aluminum alloy.

Therefore, the wiring layer 33 having a laminated structure covering the copper wiring layer 30 is formed by the aluminum wiring layer 32 made of aluminum or aluminum alloy, which is easier to alloy with gold (Au) than the copper wiring layer 30. Therefore, the wire 40 made of gold (Au) can be easily and reliably bonded to the pad portion 33a.

In the above-described embodiment, the low temperature heat treatment and the ashing treatment of the photoresist are exemplified as the treatment performed in the atmosphere containing the copper corrosive substance. However, the treatment is performed in the atmosphere containing the copper corrosive substance in the present invention. The processing is not limited to this.

In the above-described embodiment, the wiring layer having the barrier metal layer 28 and the barrier metal layer 31 has been described. However, the present invention is a wiring that does not have one or both of the barrier metal layer 28 and the barrier metal layer 31. It can also be applied to layers.

Moreover, in the above-described embodiment, the metal layer made of aluminum or an aluminum alloy has been described as an example of the second conductor layer. However, the second conductor layer is made of aluminum or an aluminum alloy. It is not limited to the metal layer. In short, the second conductor layer may be any conductor layer that is less corroded in an atmosphere containing a copper corrosive substance than the first conductor layer.

Moreover, in the above-mentioned embodiment, although oxygen was illustrated as a copper corrosive substance, a copper corrosive substance is not limited to oxygen.

In the above-described embodiment, the case where the wiring layer is formed using the CMP method has been described as an example. However, the present invention is not limited to this. The present invention can also be applied when the wiring layer is formed using a method other than the CMP method.

1A to 1B are cross-sectional views for explaining a method for manufacturing a semiconductor device 18 according to an embodiment of the present invention. 2A to 2B are cross-sectional views for explaining the method for manufacturing the semiconductor device 18 according to the embodiment of the present invention. 3A to 3B are cross-sectional views for explaining the method for manufacturing the semiconductor device 18 according to the embodiment of the present invention. 4A to 4B are cross-sectional views for explaining the method for manufacturing the semiconductor device 18 according to the embodiment of the present invention. 5A to 5B are cross-sectional views for explaining the method for manufacturing the semiconductor device 18 according to the embodiment of the present invention. 1 is a diagram illustrating a part of a cross-sectional configuration of a semiconductor device 18 according to an embodiment of the present invention. 7A to 7C are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device. 8A to 8B are cross-sectional views for explaining a conventional method for manufacturing a semiconductor device.

Explanation of symbols

20 ... Interlayer film (first interlayer insulation film)
22 ... Wiring layer (first wiring layer)
24 .. Interlayer film (second interlayer insulating film)
24a... Wiring recess 24b... Contact hole 28... Barrier metal layer 30... Copper wiring layer (second wiring layer)
31 ... Barrier metal layer (conductive layer)
32 ... Aluminum wiring layer (conductive layer)
33a: Pad part 36: Passivation film 36a: Opening (opening)

Claims (7)

A method of manufacturing a semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film,
Forming a second interlayer insulating film on the first interlayer insulating film having the first wiring layer by a single continuous process;
Providing a wiring recess on the second interlayer insulating film so as not to reach the first interlayer insulating film;
Providing a contact hole for connecting to the first wiring layer of the first interlayer insulating film at the bottom of the wiring recess;
Providing a second wiring layer on the wiring recess and the contact hole;
And a step of polishing the second wiring layer by a CMP method. Before the step of providing the second wiring layer, the step of providing a barrier metal layer on the wiring recess and the contact hole,
In the step of polishing the second wiring layer by the CMP method, the second wiring layer is polished by the CMP method until the barrier metal layer is exposed, and then the pattern used in the step of providing the wiring recess is formed. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing a barrier metal layer remaining on the second interlayer insulating film using a photoresist having an inverted pattern. A semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film,
A second interlayer insulating film of uniform material on the first interlayer insulating film having the first wiring layer;
A wiring recess provided on the second interlayer insulating film so as not to reach the first interlayer insulating film, and a bottom of the wiring recess provided to connect to the first wiring layer of the first interlayer insulating film. And a second wiring layer formed so as to fill the contact hole. A semiconductor device having a wiring layer made of copper or a copper alloy in an interlayer insulating film,
A second interlayer insulating film of uniform material on the first interlayer insulating film having the first wiring layer;
A wiring recess provided on the second interlayer insulating film so as not to reach the first interlayer insulating film, and a bottom of the wiring recess provided to connect to the first wiring layer of the first interlayer insulating film. A second wiring layer formed to fill the contact hole,
A passivation film on the second interlayer insulating film and the second wiring layer;
A semiconductor device having a pad portion made of a conductive layer provided on a second wiring layer in an opening of a passivation film.   The semiconductor device according to claim 4, wherein a conductive layer is provided so as to substantially cover the second wiring layer, and the conductive layer exposed from the opening is a pad portion.   6. The semiconductor device according to claim 3, wherein the copper alloy is a copper-magnesium alloy having a magnesium ratio of about 1 percent to about 5 percent. The conductive layer is aluminum, an aluminum-silicon alloy with a silicon ratio of about 0.5% to about 2%, a silicon ratio of about 0.5% to about 1.5%, and a copper ratio of about 0.5% 7. The semiconductor device according to claim 3, comprising an aluminum / silicon / copper alloy of about 1.5%, or an aluminum / copper alloy having a copper ratio of about 0.5% to about 3%. .