JPH0479146B2 - - Google Patents

Info

Publication number
JPH0479146B2
JPH0479146B2 JP57210158A JP21015882A JPH0479146B2 JP H0479146 B2 JPH0479146 B2 JP H0479146B2 JP 57210158 A JP57210158 A JP 57210158A JP 21015882 A JP21015882 A JP 21015882A JP H0479146 B2 JPH0479146 B2 JP H0479146B2
Authority
JP
Japan
Prior art keywords
layer
wiring
silicon
alloy
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57210158A
Other languages
Japanese (ja)
Other versions
JPS59100565A (en
Inventor
Ichiro Fujita
Akira Oooka
Hideaki Ootake
Tooru Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21015882A priority Critical patent/JPS59100565A/en
Publication of JPS59100565A publication Critical patent/JPS59100565A/en
Publication of JPH0479146B2 publication Critical patent/JPH0479146B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の構造に係り、特に浅い接
合を有する半導体装置に配設されるアルミニウム
電極配線の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor device, and particularly to the structure of an aluminum electrode wiring provided in a semiconductor device having a shallow junction.

(b) 技術の背景 高集積度のバイポーラICのエミツタ層等、浅
い接合を有するn型拡散領域は、通常、p型半導
体基体面に多結晶シリコン層を介して堆積された
りん珪酸ガラス(PSG)からりん(P)を固相
−固相・拡散させて形成する(ウオツシユド・エ
ミツタ法)。そして該浅い拡散層に対するアルミ
ニウム(Al)配線の接続に際しては、Alが拡散
層内にもぐり込んで接合を破壊するのを防止する
ために、前記多結晶シリコン層上にAl配線パタ
ーンが形成される。従つてこのような構造に於て
はAl配線パターンの下部には全域にわたつて多
結晶シリコン層が配設されているので、表面保護
絶縁膜の成長等配線パターンが形成されて後の
400〜450〔℃〕程度の熱処理工程に於て、多結晶
シリコンがAl配線中に過飽和に溶け込んで析出
し、配線抵抗を増大せしめるという問題がある。
(b) Technology background N-type diffusion regions with shallow junctions, such as the emitter layer of highly integrated bipolar ICs, are usually made of phosphosilicate glass (PSG) deposited on the surface of a p-type semiconductor substrate with a polycrystalline silicon layer interposed therebetween. ) is formed by solid phase-solid phase diffusion of phosphorus (P) (washed emitter method). When connecting aluminum (Al) wiring to the shallow diffusion layer, an Al wiring pattern is formed on the polycrystalline silicon layer to prevent Al from penetrating into the diffusion layer and destroying the junction. Therefore, in such a structure, since a polycrystalline silicon layer is provided over the entire area under the Al wiring pattern, it is difficult to prevent the growth of the surface protection insulating film, etc. after the wiring pattern is formed.
In the heat treatment process at about 400 to 450 degrees Celsius, there is a problem in that polycrystalline silicon melts into the Al wiring in a supersaturated state and precipitates, increasing the wiring resistance.

又一方ICの高集積化が進み、配線が微細化さ
れて配線に流れる電流密度が高まつて来ると、純
Alからなる配線に於ては、長時間通電を行つた
際公知のエレクトロ・マイグレーシヨン効果によ
り断線を生ずるという問題があり、該エレクト
ロ・マイグレーシヨン効果を減殺して配線寿命を
増加せしめる手段として、4〔%〕以下程度の銅
(Cu)若しくはマグネシウム(Mg)を含有せし
めたAl−Cu合金配線或るいはAl−Mg合金配線
が多く用いられるようになつて来た。
On the other hand, as ICs become more highly integrated, wiring becomes finer, and the density of current flowing through the wiring increases.
In wiring made of Al, there is a problem that wire breakage occurs due to the well-known electromigration effect when energized for a long time.As a means to reduce the electromigration effect and increase the wiring life, Al--Cu alloy wiring or Al--Mg alloy wiring containing copper (Cu) or magnesium (Mg) in an amount of 4% or less has come to be widely used.

しかしながら該Al−Cu合金配線若しくはAl−
Mg合金配線を、前述した方法で浅い接合を形成
したIC基板の多結晶シリコン層上に形成した際
には、前述したような配線形成後の熱処理によつ
て配線内へのシリコン結晶の析出が促進され、且
つ析出結晶の形状も純Alの場合に比べて大型化
するため、配線抵抗が大幅に増大してICの動作
速度を低下させるという問題を生ずる。第1図は
シリコン結晶が析出したAl−Cu若しくはAl−
Mg合金配線を模式的に示したもので、図中1は
Al−Cu若しくはAl−Mg合金配線、2はシリコ
ン析出結晶、3は多結晶シリコン層を表わしてい
る。
However, the Al-Cu alloy wiring or Al-
When Mg alloy interconnects are formed on the polycrystalline silicon layer of an IC substrate on which shallow junctions have been formed using the method described above, the heat treatment after forming the interconnects as described above may cause precipitation of silicon crystals within the interconnects. In addition, the shape of the precipitated crystals becomes larger than in the case of pure Al, resulting in a problem of significantly increasing wiring resistance and reducing the operating speed of the IC. Figure 1 shows Al-Cu or Al- with silicon crystals precipitated.
This is a schematic diagram of Mg alloy wiring, and 1 in the figure is
Al--Cu or Al--Mg alloy wiring, 2 represents a silicon precipitated crystal, and 3 represents a polycrystalline silicon layer.

(c) 従来技術と問題点 そこでAl−Cu合金配線若しくはAl−Mg合金
配線を用いた場合、析出シリコン結晶を多結晶シ
リコン層に接する下層部のみに閉じ込めるため
に、従来第2図に示すように例えばAl−Cu合金
配線1の下層に近い部分に高融点線材料として多
用されているチタン・タングステン(Ti−W)
合金層4からなる500〜1500〔Å〕程度の厚さのブ
ロツキング層を挾み込んだ構造が試みられ、Al
−Cu合金配線1に於ける下層部5以外でのシリ
コン結晶の析出は防止された。
(c) Conventional technology and problems Therefore, when using Al-Cu alloy wiring or Al-Mg alloy wiring, in order to confine the precipitated silicon crystal only in the lower layer in contact with the polycrystalline silicon layer, conventional techniques as shown in Fig. 2 are used. For example, titanium/tungsten (Ti-W), which is often used as a high melting point wire material, is used in the lower layer of the Al-Cu alloy wiring 1.
A structure in which a blocking layer of about 500 to 1500 [Å] thick consisting of alloy layer 4 is sandwiched has been attempted;
- Precipitation of silicon crystals in areas other than the lower layer portion 5 of the Cu alloy wiring 1 was prevented.

しかしこの構造に於てはTi−W合金のシリコ
ンに対する反応性が極めて強いため、電極コンタ
クト部に於て多結晶シリコン層の下部の例えば浅
いエミツタ層のシリコンまで該Ti−W合金層に
食われ、エミツタ層の接合が破壊されてエミツタ
−ベース(E−B)シヨート障害が誘起されると
いう問題があつた。
However, in this structure, the reactivity of the Ti-W alloy with silicon is extremely strong, so even silicon in the shallow emitter layer below the polycrystalline silicon layer at the electrode contact part is eaten away by the Ti-W alloy layer. However, there was a problem in that the junction of the emitter layer was destroyed and emitter-base (E-B) shot failure was induced.

(d) 発明の目的 本発明は上記問題点に鑑み、シリコンに対する
反応性がなく、且つ遮蔽効果が充分なシリコンの
ブロツク層を底部近傍に配設したAl−Cu若しく
はAl−Mg層からなる配線構造を提供するもので
あり、その目的とするところは配線の品質及び信
頼性を高めて、半導体ICの性能及び信頼性を向
上せしめるにある。
(d) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a wiring made of an Al-Cu or Al-Mg layer in which a silicon blocking layer that is not reactive to silicon and has a sufficient shielding effect is disposed near the bottom. Its purpose is to improve the quality and reliability of interconnects, thereby improving the performance and reliability of semiconductor ICs.

(e) 発明の構成 上記目的は本発明により、シリコンよりなる半
導体基板上にはアルミニウムまたはアルミニウム
合金膜からなる第1層と窒化チタンからなる第2
層と、銅もしくはマグネシウムを含むアルミニウ
ム合金膜からなり主導電層である第3層が下部よ
り順次積層されて金属配線を構成し、かつ第1層
の厚さは第3層より小で、シリコン基体とのオー
ミツクコンタクトをとるに必要にして十分でかつ
シリコンの適当な溶け込み量を規定する薄さに選
ばれ、また第2層は配線抵抗に影響を及ぼさない
薄さに選ばれていることを特徴とする半導体装置
によつて達成される。
(e) Structure of the Invention According to the present invention, the above object is achieved by providing a first layer made of aluminum or an aluminum alloy film and a second layer made of titanium nitride on a semiconductor substrate made of silicon.
layer and a third layer, which is a main conductive layer and is made of an aluminum alloy film containing copper or magnesium, are laminated sequentially from the bottom to form a metal wiring, and the thickness of the first layer is smaller than that of the third layer, and the third layer is made of an aluminum alloy film containing copper or magnesium. The thickness of the second layer must be selected to be necessary and sufficient to establish ohmic contact with the substrate and to specify an appropriate amount of silicon penetration, and the second layer must be selected to be thin enough not to affect wiring resistance. This is achieved by a semiconductor device characterized by:

(f) 発明の実施例 以下本発明を実施例について、図を用い詳細に
説明する。
(f) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.

第3図は本発明に於ける金属配線構造の一実施
例を示す断面図、第4図は本発明の半導体装置に
於ける一実施例の要部断面図である。
FIG. 3 is a cross-sectional view showing an embodiment of a metal wiring structure according to the present invention, and FIG. 4 is a cross-sectional view of essential parts of an embodiment of a semiconductor device according to the present invention.

本発明の特徴とする金属配線は、該配線が直に
接するシリコン(Si)基板、エピタキシヤル層、
拡散層、多結晶Si層等の半導体基体とオーミツ
ク・コンタクトをとるための純Al若しくはAl−
Cu、Al−Mg等のAl合金層からなる第1層と、
該第1層内に過飽和に溶け込んだSiを該第1層内
のみに閉じ込めておくための遮蔽効果を持ち、か
つシリコンに対する反応性の弱い窒化チタン
(TiN)からなる第2層と、主たる導電層であり
Al−Cu若しくはAl−Mg等のAl合金層を用いAl
のマイグレーシヨンを防止した第3層が下部から
順次積層された三層構造を有してなつている。
The metal wiring that is a feature of the present invention includes a silicon (Si) substrate, an epitaxial layer,
Pure Al or Al- for making ohmic contact with semiconductor substrates such as diffusion layers and polycrystalline Si layers.
A first layer consisting of an Al alloy layer such as Cu or Al-Mg;
A second layer made of titanium nitride (TiN), which has a shielding effect to confine the supersaturated Si dissolved in the first layer only within the first layer and has weak reactivity to silicon, and a second layer that is a main conductor. layer
Al using an Al alloy layer such as Al-Cu or Al-Mg
It has a three-layer structure in which a third layer that prevents migration is laminated sequentially from the bottom.

第3図はその断面を示したもので、オーミツク
コンタクトをとるための第1層は500〜1500〔Å〕
程度の厚さに、Siの拡散を阻止するための第2層
は500〜1500〔Å〕程度の厚さに、又主たる導電層
である第3層は4000〜8000〔Å〕程度の厚さにそ
れぞれ形成される。
Figure 3 shows its cross section, and the first layer for making ohmic contact is 500 to 1500 [Å] thick.
The second layer for preventing Si diffusion is approximately 500 to 1,500 [Å] thick, and the third layer, which is the main conductive layer, is approximately 4,000 to 8,000 [Å] thick. are formed respectively.

なおここで必ずAl−Cu若しくはAl−Mg合金
を用いなければならないのは主たる導電層である
第3層で、Alマイグレーシヨンを防止するため
で、且つ組織を不均一化させないためには、0.5
〜4〔%〕程度のCu若しくはMgを含むAl合金が
望ましい。
Note that Al-Cu or Al-Mg alloy must be used in the third layer, which is the main conductive layer, in order to prevent Al migration and to prevent the structure from becoming non-uniform.
An Al alloy containing approximately 4% of Cu or Mg is desirable.

又第1層の材料にAl−Cu、Al−Mg等のAl合
金を含めたのは、第3層と同材料にして形成工程
の簡略化を図つたもので、機能的には純Alで充
分である。
In addition, the reason why Al alloys such as Al-Cu and Al-Mg are included in the material of the first layer is to simplify the formation process by using the same material as the third layer, and functionally it is pure Al. That's enough.

更に又、Siの遮蔽層として用いたTiN層は80
〔μΩ−Cm〕程度の比較的高い抵抗率を有するが、
層の厚さが極めて薄いので、配線抵抗に及ぼす影
響は極めて少ない。
Furthermore, the TiN layer used as the Si shielding layer was 80
Although it has a relatively high resistivity of about [μΩ-Cm],
Since the layer thickness is extremely thin, the effect on wiring resistance is extremely small.

第4図は上記配線が形成された浅いエミツタ層
を有するバイポーラICの要部断面を示したもの
で、図中11はn型コレクタ領域、12はp型ベ
ース領域、13はn+型エミツタ領域、14は二
酸化シリコン(SiO2)膜、15は多結晶Si層、
16はAl−Cu合金・オーミツク・コンタクト層、
17はTiN層、18はAl−Cu合金・主導電層、
19はエミツタ配線、20はベース配線、21は
カバー絶縁膜を表わしている。
FIG. 4 shows a cross section of a main part of a bipolar IC having a shallow emitter layer on which the above-mentioned wiring is formed. In the figure, 11 is an n-type collector region, 12 is a p-type base region, and 13 is an n + type emitter region. , 14 is a silicon dioxide (SiO 2 ) film, 15 is a polycrystalline Si layer,
16 is Al-Cu alloy ohmic contact layer,
17 is a TiN layer, 18 is an Al-Cu alloy main conductive layer,
Reference numeral 19 represents an emitter wiring, 20 represents a base wiring, and 21 represents a cover insulating film.

そしてエミツタ配線19、ベース配線20等本
発明の構造を有する金属配線を形成する際には、
DCマグネトロン・スパツタ法若しくはRFマグネ
トロン・スパツタ法を用いて基体上にAl−Cu合
金層16、TiN層17、Al−Cu合金層18を順
次積層形成し、三塩化硼素(BCl3)、四塩化炭素
(CCl4)等塩素系のガスを用いるドライエツチン
グ法により、前記積層膜を一気にパターンニング
すれば良い。
When forming metal wiring having the structure of the present invention, such as the emitter wiring 19 and the base wiring 20,
Using the DC magnetron sputtering method or the RF magnetron sputtering method, an Al-Cu alloy layer 16, a TiN layer 17, and an Al-Cu alloy layer 18 are sequentially laminated on the substrate, and boron trichloride (BCl 3 ), tetrachloride The laminated film may be patterned all at once by a dry etching method using a chlorine-based gas such as carbon (CCl 4 ).

なおTiN層17は窒素(N2)、或るいはN2
アルゴン(Ar)をまぜた雰囲気中に於けるTiの
反応性スパツタによつて形成することもできる。
Note that the TiN layer 17 can also be formed by reactive sputtering of Ti in an atmosphere of nitrogen (N 2 ) or N 2 mixed with argon (Ar).

(g) 発明の効果 以上説明したように本発明に於けるアルミニウ
ム配線は、アルミニウム若しくはアルミニウム合
金からなるオーミツク・コンタクト層と、アルミ
ニウム・銅若しくはアルミニウム・マグネシウム
合金からなりアルミニウムのマイグレーシヨンを
防止した主導電層とがシリンコンの拡散を阻止す
る窒化チタン層によつて分離されてなつている。
従つてオーミツク・コンタクト層に溶け込んだシ
リコンは該オーミツク・コンタクト層内に閉じ込
められて析出し、主導電層内でのシリコンの析出
は皆無になる。
(g) Effect of the Invention As explained above, the aluminum wiring in the present invention consists of an ohmic contact layer made of aluminum or an aluminum alloy, and an ohmic contact layer made of aluminum/copper or an aluminum/magnesium alloy to prevent aluminum migration. The conductive layer is separated by a titanium nitride layer that prevents silicon diffusion.
Therefore, the silicon dissolved in the ohmic contact layer is confined and deposited within the ohmic contact layer, and no silicon is deposited within the main conductive layer.

またTiN層はシリコンに対する反応性は弱い
のでシリコン層の例えばエミツタ層の接合がTi
でQ破壊されることはない。
In addition, the TiN layer has weak reactivity with silicon, so the junction of the silicon layer, for example the emitter layer, is made of Ti.
It will not be destroyed by Q.

従つて本発明によれば、低配線抵抗を有し、且
つアルミニウムのマイグレーシヨンによる断線が
防止されたアルミニウム配線が提供されるので、
半導体装置の性能及び信頼性が向上する。
Therefore, according to the present invention, an aluminum wiring having low wiring resistance and preventing disconnection due to aluminum migration is provided.
Performance and reliability of semiconductor devices are improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はアルミニウム・銅若しくはアルミニウ
ム・マグネシウム合金配線に於けるシリコン結晶
の析出状態を示す模式図、第2図は従来のアルミ
ニウム合金配線の断面図、第3図は本発明に於け
る金属配線の一実施例の断面図、第4図は本発明
の半導体装置に於ける一実施例の要部断面図であ
る。 図に於て、11はn型コレクタ領域、12はp
型ベース領域、13はn+型エミツタ領域、14
は二酸化シリコン膜、15は多結晶シリコン層、
16はアルミニウム−銅合金・オーミツク・コン
タクト層17は窒化チタン層、18はアルミニウ
ム−銅合金・主導電層、19はエミツタ配線、2
0はベース配線、21はカバー絶縁膜を示す。
Fig. 1 is a schematic diagram showing the state of silicon crystal precipitation in aluminum-copper or aluminum-magnesium alloy wiring, Fig. 2 is a cross-sectional view of conventional aluminum alloy wiring, and Fig. 3 is a metal wiring according to the present invention. FIG. 4 is a sectional view of a main part of an embodiment of the semiconductor device of the present invention. In the figure, 11 is an n-type collector region, 12 is a p-type collector region, and 12 is a p-type collector region.
Type base region, 13 is n + type emitter region, 14
15 is a silicon dioxide film, 15 is a polycrystalline silicon layer,
16 is an aluminum-copper alloy ohmic contact layer 17 is a titanium nitride layer, 18 is an aluminum-copper alloy main conductive layer, 19 is an emitter wiring, 2
0 indicates a base wiring, and 21 indicates a cover insulating film.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコンよりなる半導体基板上にはアルミニ
ウムまたはアルミニウム合金膜からなる第1層と
窒化チタンからなる第2層と、銅もしくはマグネ
シウムを含むアルミニウム合金膜からなり主導電
層である第3層が下部より順次積層されて金属配
線を構成し、かつ第1層の厚さは第3層より小
で、シリコン基体とのオーミツクコンタクトをと
るに必要にして十分でかつシリコンの適当な溶け
込み量を規定する薄さに選ばれ、また第2層は配
線抵抗に影響を及ぼさない薄さに選ばれているこ
とを特徴とする半導体装置。
1 On a semiconductor substrate made of silicon, a first layer made of aluminum or an aluminum alloy film, a second layer made of titanium nitride, and a third layer which is a main conductive layer made of an aluminum alloy film containing copper or magnesium are formed from below. They are sequentially laminated to constitute a metal wiring, and the thickness of the first layer is smaller than the third layer, is necessary and sufficient to establish ohmic contact with the silicon substrate, and defines an appropriate amount of silicon penetration. A semiconductor device characterized in that the second layer is selected to be thin and the second layer is selected to be thin enough not to affect wiring resistance.
JP21015882A 1982-11-30 1982-11-30 Semiconductor device Granted JPS59100565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21015882A JPS59100565A (en) 1982-11-30 1982-11-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21015882A JPS59100565A (en) 1982-11-30 1982-11-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59100565A JPS59100565A (en) 1984-06-09
JPH0479146B2 true JPH0479146B2 (en) 1992-12-15

Family

ID=16584720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21015882A Granted JPS59100565A (en) 1982-11-30 1982-11-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59100565A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6190445A (en) * 1984-10-09 1986-05-08 Nec Corp Semiconductor device
JPS63129662A (en) * 1986-11-20 1988-06-02 Fujitsu Ltd Semiconductor device
JPH02159064A (en) * 1988-12-13 1990-06-19 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH04186728A (en) * 1990-11-20 1992-07-03 Nec Corp Semiconductor integrated circuit device
JP7027066B2 (en) 2017-08-24 2022-03-01 ルネサスエレクトロニクス株式会社 Semiconductor devices and their manufacturing methods

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272570A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Formation of electrode of semiconductor deviced

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272570A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Formation of electrode of semiconductor deviced

Also Published As

Publication number Publication date
JPS59100565A (en) 1984-06-09

Similar Documents

Publication Publication Date Title
US5266521A (en) Method for forming a planarized composite metal layer in a semiconductor device
JPH06140399A (en) Manufacture of metal wire
JP3296708B2 (en) Multilayer Al alloy structure for metal conductor
JPH02222148A (en) Semiconductor device
JPH06105706B2 (en) Semiconductor device
US4999160A (en) Aluminum alloy containing copper, silicon and titanium for VLSI devices
JPH0479146B2 (en)
JP3106493B2 (en) Semiconductor device
JPH06204218A (en) Manufacturing method of semiconductor device
JPH0418760A (en) Semiconductor device
JP3178605B2 (en) Semiconductor device
JP3035945B2 (en) Semiconductor device
JP3368629B2 (en) Semiconductor device
JPH0448854B2 (en)
JPH0448855B2 (en)
JP3337758B2 (en) Method for manufacturing semiconductor device
JP2754653B2 (en) Aluminum wiring formation method
JP2893794B2 (en) Semiconductor device
JP2945010B2 (en) Semiconductor device
JPS6244813B2 (en)
JP2949752B2 (en) Wiring body and method of forming the same
JPH04309229A (en) Semiconductor integrated circuit device
JPH0220142B2 (en)
JPH0334545A (en) Manufacture of semiconductor device
JPH04155867A (en) Semiconductor device