JPS63129662A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63129662A JPS63129662A JP27697186A JP27697186A JPS63129662A JP S63129662 A JPS63129662 A JP S63129662A JP 27697186 A JP27697186 A JP 27697186A JP 27697186 A JP27697186 A JP 27697186A JP S63129662 A JPS63129662 A JP S63129662A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alloy
- solid phase
- phase epitaxial
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000010936 titanium Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 7
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007790 solid phase Substances 0.000 abstract description 27
- 229910045601 alloy Inorganic materials 0.000 abstract description 23
- 239000000956 alloy Substances 0.000 abstract description 23
- 229910018575 Al—Ti Inorganic materials 0.000 abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 229910018182 Al—Cu Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000002244 precipitate Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000010349 pulsation Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の多層電極配線において、第１層にＡｌ−Ｔ
ｉ合金を、第２層に高融点金属の窒化物を、第３層にＡ
ＩあるいはＡ１合金を使用するもので、コンタクト抵抗
を低減出来、ＳＢＤの順方向立上り電圧をＴｉ含有量で
調整出来る。[Detailed Description of the Invention] [Summary] In a multilayer electrode wiring of a semiconductor device, Al-T is used in the first layer.
i alloy, high melting point metal nitride in the second layer, and A in the third layer.
By using I or A1 alloy, the contact resistance can be reduced, and the forward rising voltage of the SBD can be adjusted by adjusting the Ti content.
本発明は半導体装置の電極配線の構造に係り、詳しくは
、第１層にアルミニウム・チタン（ＡｔＴｉ）を、第２
層には高融点金属の窒化物を、第３層にはＡ１あるいは
Ａ１合金層をもつ多層電極配線に関する。The present invention relates to the structure of electrode wiring of a semiconductor device, and more specifically, the present invention relates to the structure of electrode wiring of a semiconductor device, and more particularly, aluminum titanium (AtTi) is used as the first layer, and aluminum titanium (AtTi) is used as the second layer.
The present invention relates to a multilayer electrode wiring having a layer made of high-melting point metal nitride and a third layer made of A1 or an A1 alloy layer.
ＬＳＩ、超ＬＳＩ等の半導体装置の電極配線材料として
は、ＡＩ若しくはＡ１合金が多く使用されている。AI or A1 alloy is often used as an electrode wiring material for semiconductor devices such as LSI and VLSI.
＾ｌは電気抵抗が小さく、且つ半導体例えばシリコン（
Ｓｉ ）との接触抵抗を小さくなし得る等の長所を有す
るが、その反面Ｓｉと反応し易く、電極配線形成後のア
ニール工程等の加熱処理工程において、ＡＩ中へＳｉが
容易に析出し、その結果、固相エピタキシャル、ＡＩス
パイク等の好ましくない現象が起こる。^l has low electrical resistance and is a semiconductor such as silicon (
It has the advantage of being able to reduce the contact resistance with Si (Si), but on the other hand, it easily reacts with Si, and Si easily precipitates into the AI during heat treatment steps such as annealing steps after electrode wiring formation. As a result, undesirable phenomena such as solid phase epitaxial growth and AI spikes occur.
このような問題を防止するため、チタン・タングステン
（ＴｉＷ）がＡｔとも、またＳｉとも反応し難いことを
利用し、電極配線層を多層となし、第１層と第３層はＡ
ＩもしくはＡ１合金層とし、その間に第２層としてＴｉ
Ｗの中間層を形成する。第１層は薄く形成し、Ｓｉと反
応するＡＩ量を少量に限定し、もってＳｔの析出量を一
定量以下に制限し得るようにしたものがある。In order to prevent such problems, the electrode wiring layer is made into a multilayer structure by taking advantage of the fact that titanium/tungsten (TiW) hardly reacts with At or Si, and the first and third layers are made of A.
I or A1 alloy layer, with Ti as a second layer between them.
A W intermediate layer is formed. The first layer is formed thinly, and the amount of AI that reacts with Si is limited to a small amount, thereby making it possible to limit the amount of St precipitated to a certain amount or less.
しかしながら、上記ＴｉＷ層を形成するには、通常スパ
ッタリング法によるが、ＴｉＷは合金でなく複合物であ
るため、ＴｉとＷのスパッタレートが一定でなく、また
ＴｉＷの焼結体ターゲットから微粉末が発生飛散し、基
板表面に付着する等の問題がある。However, sputtering is usually used to form the TiW layer, but since TiW is not an alloy but a composite, the sputtering rate of Ti and W is not constant, and fine powder is collected from the TiW sintered target. There are problems such as generation, scattering, and adhesion to the substrate surface.
従って、本発明者等はさきに特願昭５６−１４４３９３
において、前記ＴｉＷ層形成時の問題点を解決するもの
として、ＴｉＷの替わりにＴｉＮ等の高融点金属の窒化
物を用いた“ＡＩ（或いはＡＩ合金）−高融点金属の窒
化物−ＡＩ（或いはＡＩ合金）”系の３層電極配線層を
発明した。Therefore, the present inventors first applied for patent application No. 56-144393.
In order to solve the problems in forming the TiW layer, "AI (or AI alloy) - nitride of high melting point metal - AI (or We have invented a three-layer electrode wiring layer based on AI alloy).
即ち、高融点金属の窒化物はＳｉと合金を作らず、また
Ａｌとも反応しない性質を有し、しかもその被膜形成は
、金属単体よりなるターゲットを用いアルゴン（Ａｒ）
と窒素（Ｎ２）の混合雰囲気中でスパツクを行えば、良
質の被膜を安定して得ることが出来る。In other words, nitrides of high-melting metals do not form alloys with Si or react with Al, and the film can be formed using argon (Ar) using a target made of a single metal.
If sprinkling is performed in a mixed atmosphere of nitrogen (N2) and nitrogen (N2), a high quality film can be stably obtained.
然しなから、この場合、Ｓｉ基板のＳｉとコンタクトす
る第１層として用いられる金属はＡＩ或いはＡＩ合金で
、ここにおけるＡＩ合金は通常のＡｌ−３ｉ等で、第１
層とＳｉ基板面との間で生起する固相エピタキシャルの
問題に対しては未だ充分なる解決を与える至っていなか
った。However, in this case, the metal used as the first layer in contact with the Si of the Si substrate is AI or an AI alloy, and the AI alloy here is ordinary Al-3i etc.
No satisfactory solution has yet been provided to the problem of solid phase epitaxial growth occurring between the layer and the Si substrate surface.
本発明は、Ｓｉ基板面との間の固相エピタキシャル発生
の少ない第１層用ＡＩ合金をもつ多層電極配線を有する
半導体装置を提供しようとするものである。The present invention aims to provide a semiconductor device having a multilayer electrode interconnection using an AI alloy for the first layer that is less likely to cause solid phase epitaxial formation between the first layer and the Si substrate surface.
第５図は従来例における電極配線構造模式図を示す。 FIG. 5 shows a schematic diagram of an electrode wiring structure in a conventional example.
この図に示すものは、前述の特願昭５６−１４４３９３
におけるものであるが、Ｓｉ基板１面上のＳｉＯ□膜２
に電極窓を開口し、スパッタリング法により第１層のＡ
Ｉ膜層６を厚さ約１５０μｍ被着する。ついで、Ｔｉを
ターゲットとしてＡｒとＮＺの雰囲気中でのりアクティ
ブスパッタリング法により、厚さ約２０００人の第２層
のＴｉＮ膜層４を形成する。What is shown in this figure is the above-mentioned patent application No. 56-144393.
, the SiO□ film 2 on one surface of the Si substrate
An electrode window is opened in the first layer A by sputtering.
An I film layer 6 is deposited to a thickness of approximately 150 μm. Next, a second TiN film layer 4 having a thickness of approximately 2000 layers is formed by active sputtering using Ti as a target in an atmosphere of Ar and NZ.
ついで、第３層のＡＩ膜層５を厚さ約６０００人形成す
る。Next, a third AI film layer 5 is formed to a thickness of about 6,000 layers.
その後、通常のりソグラフィ技術と異方性エツチングに
より、配線層を工・ノチングしてバターニングする。Thereafter, the wiring layer is processed, notched, and patterned using normal lithography technology and anisotropic etching.
第２層に使用したＴｉＮ膜層４はＳｔおよびＡＩと反応
し難く且つ導電性も良好であり、被膜形成時のターゲッ
ト粉末の付着等の問題もない。The TiN film layer 4 used as the second layer does not easily react with St and AI, has good conductivity, and has no problems such as adhesion of target powder during film formation.
しかし、第１層に厚さ１５０人のＡ１膜層６を使用して
いるので、電極形成後の熱処理によりＳｉ基板ｌ中のＳ
ｔがＡＩ膜層６との界面において、Ａ１の中に析出する
。これが冷えるとき界面に、ＡＩを含有したＳｉのエピ
タキシャル層が形成される固相エピタキシャル現象が発
生し、これがコンタクト抵抗を変化増大せしめる。これ
によりコンタクト抵抗が大きくなり且つコンタクト抵抗
のバラツキの原因となる。However, since the A1 film layer 6 with a thickness of 150 μm is used as the first layer, the S in the Si substrate 1 is removed by heat treatment after electrode formation.
t precipitates in A1 at the interface with the AI film layer 6. When this cools, a solid-phase epitaxial phenomenon occurs in which an epitaxial layer of Si containing AI is formed at the interface, which changes and increases the contact resistance. This increases contact resistance and causes variations in contact resistance.
又第１層をＡｌ−５ｉ（Ｓｉ １％）の合金層としても
、ＡＩスパイクについては効果があるも、固相エピタキ
シャル化に対しては、殆ど純ＡＩの場合とかわりない。Even if the first layer is an alloy layer of Al-5i (Si 1%), it is effective for AI spikes, but it is almost the same as pure AI for solid phase epitaxialization.
このような電極配線は、例えば、ショットキーバリアダ
イオード（ＳＢＤ）に使用した場合、熱処理工程により
順方向電圧が大きくなり、且つそのバラツキも大きくな
るので、特性の揃った半導体装置を得るためには好まし
くない。For example, when such electrode wiring is used in a Schottky barrier diode (SBD), the forward voltage increases due to the heat treatment process, and its variation also increases, so it is necessary to obtain a semiconductor device with uniform characteristics. Undesirable.
第１層の金属として固相反応の起こり難い材料を使用し
、コンタクト抵抗を小さくする。A material that is unlikely to undergo a solid phase reaction is used as the first layer metal to reduce contact resistance.
上記問題点の解決は、シリコン基板表面より導出された
電極配線層が第１層がチタンを０．１〜１％を含有する
アルミニウム合金でなり、第２層が高融点金属の窒化物
膜層でなり、第３Ｎがアルミニウムあるいはアルミニウ
ム合金層よりなるものを有している本発明による半導体
装置により達成される。The solution to the above problem is that the first layer of the electrode wiring layer led out from the silicon substrate surface is made of an aluminum alloy containing 0.1 to 1% titanium, and the second layer is a nitride film layer of a high melting point metal. This is achieved by the semiconductor device according to the present invention, in which the third N is made of aluminum or an aluminum alloy layer.
電極配線のコンタクト窓において、第１層のＡｌ−Ｔｉ
合金層とＳｉとの同相エピタキシャル反応が起こり難く
、コンタクト抵抗を低減することが出来る。In the contact window of the electrode wiring, the first layer of Al-Ti
In-phase epitaxial reaction between the alloy layer and Si is less likely to occur, and contact resistance can be reduced.
第１図は本発明における電極配線構造模式図を示す。 FIG. 1 shows a schematic diagram of the electrode wiring structure in the present invention.
この図において、第５図と同じ対象物は同じ符号で示す
。In this figure, the same objects as in FIG. 5 are designated by the same reference numerals.
Ｓｉ基板１面上のＳｉｎｇ膜２に電極窓を開口し、Ｔｉ
含有量０．１〜１％のＡｔ−Ｔｉ合金をターゲットとし
たスパッタリング法により第１層のＡｌ−Ｔｉ合金膜層
３を厚さ約１５０μｍ被着する。An electrode window is opened in the Sing film 2 on the Si substrate 1 surface, and the Ti
A first Al-Ti alloy film layer 3 having a thickness of about 150 μm is deposited by sputtering using an At-Ti alloy with a content of 0.1 to 1% as a target.
ＴｉをターゲットとしてＡｒとＮ２の雰囲気中でのりア
クティブスパッタリング法により、厚さ約２０ＯＯ人の
第２層のＴｉＮ膜層４を形成する。A second TiN film layer 4 having a thickness of about 200 mm is formed by active sputtering using Ti as a target in an atmosphere of Ar and N2.
ついで、第３層のＡＩ膜層５を厚さ約６０００人形成す
る。Next, a third AI film layer 5 is formed to a thickness of about 6,000 layers.
また、第３層５としてはＡＩ−Ｃｕ（Ｃｕ １％）等の
Ａ１合金層を使用してもよい。Further, as the third layer 5, an A1 alloy layer such as AI-Cu (Cu 1%) may be used.
その後、通常のりソグラフィ技術と異方性エツチングに
より、配線層をエツチングしてパターニングする。Thereafter, the wiring layer is etched and patterned using normal lithography technology and anisotropic etching.
この場合、第１ＨにＡｌ−Ｔｉ合金を使用しているので
、Ｓｉ基板１と第１層の間で発生ずる固相エピタキシャ
ル現象を少なくすることが出来る。この状況を第２図に
示す。In this case, since an Al--Ti alloy is used for the first H, it is possible to reduce the solid phase epitaxial phenomenon that occurs between the Si substrate 1 and the first layer. This situation is shown in Figure 2.
第２図は電極厚さと固相エピタキシャル率関係図を示す
。FIG. 2 shows a relationship between electrode thickness and solid phase epitaxial rate.
この図において、横軸は電極配線の厚さ、縦軸は固相エ
ピタキシャル率を示す。図中、Ａ−１２はＴｉ含有Ｎ０
８１％および０．５％のＡｌ−Ｔｉ合金の電極配線を形
成後、４５０℃、３０分の熱処理工程を１２回行ったも
のである。又、Ｂ−６は純Ａｔの電極配線を形成後、同
様な４５０℃、３０分の熱処理工程を６凹行ったもので
、Ｂ−１２は純Ａ１電極配線を形成後、４５０℃、３０
分の熱処理工程を１２回行ったものである。In this figure, the horizontal axis shows the thickness of the electrode wiring, and the vertical axis shows the solid phase epitaxial rate. In the figure, A-12 is Ti-containing N0
After forming electrode wirings of 81% and 0.5% Al-Ti alloys, a heat treatment process of 450° C. for 30 minutes was performed 12 times. In addition, B-6 was formed by forming a pure At electrode wiring and then subjected to a similar heat treatment process at 450°C for 30 minutes, and B-12 was formed by forming a pure A1 electrode wiring and then subjected to a heat treatment process at 450°C for 30 minutes.
The heat treatment process was performed 12 times.
これらは、いずれも２μｍ角の大きさの電極窓をもつ試
料１００個についてのものであり、また電極窓の面積の
１７３以上が固相エピタキシャル化しているものをカウ
ントして、固相エピタキシャル率とした。These are all for 100 samples with electrode windows of 2 μm square size, and samples in which 173 or more of the area of the electrode windows are solid phase epitaxial are counted, and the solid phase epitaxial rate is calculated. did.
固相エピタキシャルの判定は熱処理後、電極配線をエツ
チング除去して顕微鏡で目視する方法によった。Solid phase epitaxiality was determined by a method of removing electrode wiring by etching after heat treatment and visually observing it with a microscope.
この図でわかるように、Ａｌ−Ｔｉ合金のものは、Ｔｉ
量０．１％、１％の両方共、１２回熱処理しても尚、純
ＡＩの６回のものより固相エピタキシャル率が低いこと
を示している。As you can see in this figure, the Al-Ti alloy has Ti
Both amounts of 0.1% and 1% show that even after 12 heat treatments, the solid phase epitaxial rate is still lower than that of pure AI with 6 heat treatments.
又、同じ組成の電極配線では厚さが厚くなると同相エピ
タキシャル率が増大しているが、これは、ＡＩまたはＡ
１合金の電極配線が厚い程、より多くのＳｉが溶は込み
、析出するためである。In addition, the in-phase epitaxial rate increases as the thickness increases for electrode wirings with the same composition, but this is due to the fact that AI or
This is because the thicker the electrode wiring of 1 alloy, the more Si penetrates and precipitates.
第３図は固相エピタキシャル面積率と抵抗比の関係図で
ある。FIG. 3 is a diagram showing the relationship between the solid phase epitaxial area ratio and the resistance ratio.
この図において、横軸は固相エピタキシャル面積率を、
縦軸は抵抗比を示す。電極窓に固相エピタキシャルが認
められない場合の固相エピタキシャル面積率はＯで、こ
のときの抵抗を１として固相エピタキシャル面積率と抵
抗との関係を示すもので、固相エピタキシャル面積率が
１となると、即ち全面が固相エピタキシャル化すると、
抵抗比は略５程度となることを示す。In this figure, the horizontal axis represents the solid phase epitaxial area ratio,
The vertical axis shows the resistance ratio. The solid phase epitaxial area ratio when no solid phase epitaxial is observed in the electrode window is O, and the relationship between the solid phase epitaxial area ratio and resistance is shown assuming that the resistance at this time is 1, and the solid phase epitaxial area ratio is 1. In other words, when the entire surface becomes solid-phase epitaxial,
This indicates that the resistance ratio is about 5.
また、第２図に示すように電極配線層の膜厚を薄くする
と固相エピタキシャル率は小さくなっているが、５０μ
ｍ以下に薄くすると、別の問題が生ずる。即ち３層構造
とした場合でも、第２層はＴｉＮ層であるため、コンタ
クト抵抗が高くなって了う。Furthermore, as shown in Fig. 2, when the thickness of the electrode wiring layer is made thinner, the solid phase epitaxial rate becomes smaller;
When the thickness is reduced to less than m, another problem arises. That is, even in the case of a three-layer structure, since the second layer is a TiN layer, the contact resistance becomes high.
従って、第１層の厚さとしては５０〜１５０μｍ程度と
するのが最もコンタクト抵抗の低い電極配線層を得るこ
とが出来る。Therefore, it is possible to obtain an electrode wiring layer with the lowest contact resistance by setting the thickness of the first layer to about 50 to 150 μm.
このＡｌ−Ｔｉ合金で−Ｔｉ含有量を０．１〜１％に限
定する理由は、０．１％以下ではＴｉを含有せしめる効
果が少ないためであり、また１％以上とすると、ターゲ
ット材料のＡｌ−Ｔｉ合金に偏析が生じ均一組成のもの
が作りにくいためである。The reason why the -Ti content is limited to 0.1 to 1% in this Al-Ti alloy is that if it is less than 0.1%, the effect of containing Ti is small, and if it is more than 1%, the target material This is because segregation occurs in the Al-Ti alloy, making it difficult to produce one with a uniform composition.
第４図はＳＢＤにおけるＡｌ−Ｔｉ電極のＴｉ含有量と
ＶＦとの関係図である。FIG. 4 is a diagram showing the relationship between the Ti content of the Al-Ti electrode and VF in SBD.
この図は、横軸は順方向電流、縦軸は順方向電圧ＶＦ、
パラメーターとしてＡｔ−Ｔｉ電極配線のＡｔ含有量を
とって示している。In this figure, the horizontal axis is the forward current, the vertical axis is the forward voltage VF,
The At content of the At-Ti electrode wiring is taken as a parameter.
この図によると、Ｔｉ量が増すに従って順方向立上り電
圧を小さくすることが出来るので、Ｔｉ量を加減するこ
とによって、順方向立上り電圧を調節することが可能と
なり、ＳＢＤの設計が容易となる。According to this figure, as the amount of Ti increases, the forward rising voltage can be reduced, so by adjusting the amount of Ti, the forward rising voltage can be adjusted, which facilitates the design of the SBD.
また、この実施例では、第２層として、ＴｉＮなるＴｉ
の窒化物としたが、これは他の高融点金属、例えば、Ｔ
ａ、、 Ｗ％ Ｈｆ、、 ＭＯ％ Ｚｒ、、 Ｎｂ、■
およびＣｒの中の一つの金属の窒化物を使用しても、同
様な固相エピタキシャル率の小さい、コンタクト抵抗の
低い電極配線層を得ることが出来る。In addition, in this embodiment, the second layer is made of TiN.
The nitride of T
a,, W% Hf,, MO% Zr,, Nb, ■
Even if a nitride of one metal among Cr and Cr is used, it is possible to obtain a similar electrode wiring layer with a low solid phase epitaxial rate and a low contact resistance.
以上詳細に説明したように、本発明の電極配線を有する
半導体装置によれば、電極コンタクト部における固相エ
ピタキシャルの少なくすることが出来、従って、コンタ
クト抵抗が低減出来る。As described above in detail, according to the semiconductor device having the electrode wiring of the present invention, it is possible to reduce solid phase epitaxial formation in the electrode contact portion, and therefore, the contact resistance can be reduced.
また、ＳＢＤに適用すれば、Ｔｉ量により順方向立上り
電圧を調節することが可能となる。Moreover, if applied to SBD, it becomes possible to adjust the forward rising voltage by adjusting the amount of Ti.
第１図は本発明における電極配線構造模式図、第２図は
電極厚さと固相エピタキシャル率関係図、
第３図は固相エピタキシャル面積率と抵抗比の関係図、
第４図はＳＢＤにおける旧−Ｔｉ電極のＴｉ含を量とＶ
Ｆとの関係図、
第５図は従来例における電極配線構造模式図を示す。
これら図において１．
１はシリコン基板（Ｓｉ基板）、
２は酸化シリコン膜（ＳｉＯｚｌｌ莫）、３は第１層（
ＡＩ−Ｔｉ）、
４は第２層（ＴｉＮ）、
脈発日月（こお゛けろ電ｌｊ面己繰構１模式回第１ 図
厚：？ ＜Ａ＞ −
屯感厚ゴビ固相エビタＡンヤル率関係口第２ 回
因相工じ９モジでル位目ｉ牢ヒオ医１毘じし力団任図嘱
３ ｍ
・・項方向東５ＬＣｐＡ）
ＳＢＤに８【アろへ！−丁し１ヒタシβ丁しイ計塙１璽
＝Ｔｈヒ力関係日 毛４回
右り贋（イ々・１１（ス・１する１Ｌ極白乙繰力４ヱＬ
模に日射５ 圓Fig. 1 is a schematic diagram of the electrode wiring structure in the present invention, Fig. 2 is a relation diagram between electrode thickness and solid phase epitaxial ratio, Fig. 3 is a relation diagram between solid phase epitaxial area ratio and resistance ratio, and Fig. 4 is a diagram showing the relationship between solid phase epitaxial area ratio and resistance ratio. - Ti content of Ti electrode and V
FIG. 5 shows a schematic diagram of the electrode wiring structure in a conventional example. In these figures, 1. 1 is a silicon substrate (Si substrate), 2 is a silicon oxide film (SiOzllmo), and 3 is a first layer (
AI-Ti), 4 is the second layer (TiN), pulsation sun and moon (Ko-o-kero-kero-lj-plane-regeneration-structure-1-schematic-1st Figure thickness: ? <A> - Thickness of solid phase Evita A Nyaru rate related mouth 2nd time, 9th mod, 1st time, 1st time, 3 m...7 direction East 5LCpA) 8 to SBD [Arohe! -Dish 1 Hitashi β Dish I Keihan 1 Sei = Th power related day Hair 4 times right counterfeit (I, 11 (S, 1 Suru 1L Gokuhaku Otsuri force 4ヱL)
Simulated solar radiation 5 circles
Claims (1)
第１層（３）がチタンを０．１〜１％を含有するアルミ
ニウム合金でなり、 第２層（４）が高融点金属の窒化物膜層でなり、第３層
（５）がアルミニウムあるいはアルミニウム合金層より
なるものを有している ことを特徴とする半導体装置。[Claims] In the electrode wiring layer led out from the surface of the silicon substrate (1), the first layer (3) is made of an aluminum alloy containing 0.1 to 1% titanium, and the second layer (4) is made of an aluminum alloy containing 0.1 to 1% titanium. 1. A semiconductor device comprising a nitride film layer of a high melting point metal, the third layer (5) comprising an aluminum or aluminum alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27697186A JPS63129662A (en) | 1986-11-20 | 1986-11-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27697186A JPS63129662A (en) | 1986-11-20 | 1986-11-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63129662A true JPS63129662A (en) | 1988-06-02 |
Family
ID=17576964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27697186A Pending JPS63129662A (en) | 1986-11-20 | 1986-11-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63129662A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03178131A (en) * | 1989-12-06 | 1991-08-02 | Nec Corp | Semiconductor device |
| US5747361A (en) * | 1991-05-01 | 1998-05-05 | Mitel Corporation | Stabilization of the interface between aluminum and titanium nitride |
| KR100279011B1 (en) * | 1991-05-02 | 2001-01-15 | 데이브 브라운 | Stabilization of interface between aluminum and titanium nitride |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169363A (en) * | 1980-05-29 | 1981-12-26 | Fujitsu Ltd | Semiconductor device |
| JPS59100565A (en) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | Semiconductor device |
| JPS60251663A (en) * | 1984-05-28 | 1985-12-12 | Mitsubishi Electric Corp | Semiconductor device |
| JPS618971A (en) * | 1984-06-23 | 1986-01-16 | Nippon Gakki Seizo Kk | Semiconductor device |
-
1986
- 1986-11-20 JP JP27697186A patent/JPS63129662A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169363A (en) * | 1980-05-29 | 1981-12-26 | Fujitsu Ltd | Semiconductor device |
| JPS59100565A (en) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | Semiconductor device |
| JPS60251663A (en) * | 1984-05-28 | 1985-12-12 | Mitsubishi Electric Corp | Semiconductor device |
| JPS618971A (en) * | 1984-06-23 | 1986-01-16 | Nippon Gakki Seizo Kk | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03178131A (en) * | 1989-12-06 | 1991-08-02 | Nec Corp | Semiconductor device |
| US5747361A (en) * | 1991-05-01 | 1998-05-05 | Mitel Corporation | Stabilization of the interface between aluminum and titanium nitride |
| KR100279011B1 (en) * | 1991-05-02 | 2001-01-15 | 데이브 브라운 | Stabilization of interface between aluminum and titanium nitride |
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