JPS6388843A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6388843A JPS6388843A JP23503086A JP23503086A JPS6388843A JP S6388843 A JPS6388843 A JP S6388843A JP 23503086 A JP23503086 A JP 23503086A JP 23503086 A JP23503086 A JP 23503086A JP S6388843 A JPS6388843 A JP S6388843A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- film
- insulating film
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010949 copper Substances 0.000 claims abstract description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052802 copper Inorganic materials 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 12
- 230000005012 migration Effects 0.000 abstract description 7
- 238000013508 migration Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000005360 phosphosilicate glass Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
上面及び下面をアルミニウム(^l)層で覆うことによ
って、被覆絶縁膜等の気相成長時の熱処理における、酸
化による配線抵抗の増大及び拡散による素子特性の劣化
を防止した銅(Cu)配線を用い、配線抵抗を減少させ
、且つエレクトロマイグレーション及びストレスマイグ
レーションによる断線を防止した半導体装置。[Detailed description of the invention] [Summary] By covering the upper and lower surfaces with an aluminum (^l) layer, it is possible to increase wiring resistance due to oxidation and improve device characteristics due to diffusion during heat treatment during vapor phase growth of a covering insulating film, etc. A semiconductor device that uses copper (Cu) wiring that prevents deterioration, reduces wiring resistance, and prevents disconnection due to electromigration and stress migration.
本発明は半導体装置に係り、特に半導体装置の配線構造
の改良に関する。The present invention relates to semiconductor devices, and particularly to improvements in the wiring structure of semiconductor devices.
半導体集積回路装置(IC)は、LSI、超Lsrと大
規模高集積化が進んでおり、回路を形成する配線の幅も
極度に縮小されて来ている。2. Description of the Related Art Semiconductor integrated circuit devices (ICs) are becoming increasingly large-scale and highly integrated, such as LSIs and ultra-LSRs, and the width of wiring forming circuits is also becoming extremely narrow.
そして配線幅の縮小に伴って、配線抵抗の増大や断線発
生率の増大等による半導体装置の性能や信頼度寿命の低
下が問題になっており、改善が要望されている。As the wiring width decreases, the performance and reliability life of the semiconductor device decreases due to an increase in wiring resistance, an increase in the incidence of disconnection, etc., and improvements are desired.
半導体装置の配線材料には、形成が容易で耐酸化性を有
し、且つ電気抵抗が低い等の理由からアルミニウム(A
I)が一般に用いられている。Aluminum (A) is used as a wiring material for semiconductor devices because it is easy to form, has oxidation resistance, and has low electrical resistance.
I) is commonly used.
そして近年は、高集積化に伴い浅く形成されるようにな
った拡散領域との間に生ずるスピーリング現象、即ちA
I中へシリコン(St)が溶は込んでSi面に凹部が形
成される現象による接合破壊を防止する等の面から、1
〜3%程度のシリコン(Si)を含んだAl−Si合金
配線が特に多用されるようになっている。In recent years, the phenomenon of spilling that occurs between diffusion regions that have become shallower due to higher integration, or A
From the viewpoint of preventing bond breakdown due to the phenomenon that silicon (St) melts into I and forms a recess on the Si surface, 1.
Al--Si alloy wiring containing approximately 3% silicon (Si) has become particularly popular.
しかし上記Al−5上合金等A1を主成分とする配線に
おいては、配線幅が極度に狭められてその断面積が大幅
に縮小された際には、電流密度の増大によるエレクトロ
マイグレーション効果の増大、及び絶縁膜との間の熱膨
張率の差によって生ずる引張応力によるストレスマイグ
レーション等によって断線が発生し易くなり、半導体装
置の信頼度寿命の低下を招いている。However, in interconnects whose main component is A1, such as the above-mentioned Al-5 alloy, when the interconnect width is extremely narrowed and its cross-sectional area is significantly reduced, the electromigration effect increases due to the increase in current density. Disconnection is likely to occur due to stress migration due to tensile stress caused by the difference in coefficient of thermal expansion between the semiconductor device and the insulating film, resulting in a reduction in the reliability and life of the semiconductor device.
本発明が解決しようとする問題点は、上記のように半導
体装置において従来一般に用いられていたAl配線が、
配線幅が縮小された際に、エレクトロマイグレーション
やストレスマイグレーションによって断線を生じ易くな
り、半導体装置の信頼度寿命を低下させていたことであ
る。The problem to be solved by the present invention is that, as mentioned above, the Al wiring commonly used in semiconductor devices is
When the wiring width is reduced, wire breaks are more likely to occur due to electromigration or stress migration, reducing the reliability and lifetime of semiconductor devices.
上記問題点は、上面と下面がアルミニウム層(5) (
6)で覆われた銅被膜配線(7)を備えてなる本発明に
よる半導体装置によって解決される。The above problem is that the top and bottom surfaces are made of aluminum layers (5) (
The problem is solved by the semiconductor device according to the present invention, which includes a copper-coated wiring (7) covered with (6).
〔作 用〕
即ち本発明は、上面をA1層で被覆保護することにより
350〜430℃程度の高温で行われる被覆絶縁膜の気
相成長等、配線形成以後の酸化を伴う工程における酸化
による配線抵抗の増大を防止し、且つその下面にもA1
層を設けることにより該配線のSi基体とのコンタクト
部におけるSi基体内への上記高温における配線材料の
拡散による半導体素子性能の劣化を防止することによっ
て、電気抵抗力痛Iに対して2部3程度で配線抵抗の減
少に有利で、且つ八1に対して100倍程度のエレクト
ロマイグレーション耐性を有し、更にストレスマイグレ
ーション耐性にも優れたCuを配線材料に用いることを
可能にしたもので、これによって、半導体装置が高集積
化され配線幅が極度に狭められた際の配線抵抗の増大を
抑止し、且つ断線を防止して、該高集積半導体装置の性
能及び信頼度寿命の向上を図るものである。[Function] That is, the present invention protects the upper surface with an A1 layer to prevent wiring by oxidation in processes that involve oxidation after wiring formation, such as vapor phase growth of a covering insulating film performed at a high temperature of about 350 to 430°C. It prevents an increase in resistance and also has A1 on the bottom surface.
By providing a layer to prevent deterioration of semiconductor device performance due to the diffusion of the wiring material into the Si substrate at the high temperature at the contact portion of the wiring with the Si substrate, it is possible to This makes it possible to use Cu as a wiring material, which is advantageous in reducing wiring resistance and has an electromigration resistance that is about 100 times that of 81, and also has excellent stress migration resistance. This is intended to improve the performance, reliability, and lifespan of highly integrated semiconductor devices by suppressing an increase in wiring resistance and preventing disconnection when semiconductor devices become highly integrated and the wiring width becomes extremely narrow. It is.
以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.
第1図は本発明の一実施例を示す模式側断面図で、第2
図(a)〜(e)は本発明に係るCu配線の形成方法の
工程断面図である。FIG. 1 is a schematic side sectional view showing one embodiment of the present invention;
Figures (a) to (e) are process cross-sectional views of the method for forming Cu wiring according to the present invention.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
本発明に係る半導体装置は例えば第1図に示すように、
p型St基板1面に半導体素子を構成するn゛型拡散領
域2が形成され、該基板上に二酸化シリコン(S i
O2)下層絶縁膜3が形成され、該下層絶縁膜3に前記
n゛型拡散領域2を表出する配線コンタクト窓4が形成
され、下面に厚さ1000人程度0第1のへ1層5を有
し且つ上面が厚さ1000人程度0第2のAl16で覆
われた厚さ6000〜8000人程度のCu被膜入定7
が、前記配線コンタクト窓4部においてn“型拡散領域
2に接し且つ下層絶縁膜3上に延在して配設され、該C
u被膜配線7の配設面上に燐珪酸ガラス(PSG)より
なる被覆絶縁膜8が形成されてなっている。The semiconductor device according to the present invention, for example, as shown in FIG.
An n-type diffusion region 2 constituting a semiconductor element is formed on one surface of a p-type St substrate, and silicon dioxide (Si) is formed on the substrate.
O2) A lower insulating film 3 is formed, a wiring contact window 4 exposing the n-type diffusion region 2 is formed in the lower insulating film 3, and a first layer 5 with a thickness of about 1000 is formed on the lower surface. and the upper surface is covered with a second Al16 layer with a thickness of about 6000 to 8000 mm.7
is disposed in the wiring contact window 4 portion in contact with the n" type diffusion region 2 and extending on the lower layer insulating film 3, and the C
A covering insulating film 8 made of phosphosilicate glass (PSG) is formed on the surface on which the u-covered wiring 7 is provided.
なお、上記Cu被膜配線7の上面に設けられる第2のへ
1層6は被覆絶縁膜8を気相成長により形成する際のC
u被膜配線7上面の酸化を防止する保護機能を有し、下
面に設けられる第1のA1層5はCu被膜配線7からC
uがn゛型拡散領域2等のSi基体内に拡散するのを阻
止するバリア機能を有し、上記保護機能及びバリア機能
を充分に果たすためには、第1、第2のA1層5.6の
厚さは少なくとも1000Å以上必要である。The second layer 6 provided on the upper surface of the Cu-coated wiring 7 is made of carbon when the coating insulating film 8 is formed by vapor phase growth.
The first A1 layer 5 provided on the lower surface has a protective function of preventing oxidation of the upper surface of the U-coated wiring 7, and the
In order to have a barrier function of preventing u from diffusing into the Si substrate such as the n-type diffusion region 2, and to sufficiently fulfill the above protection function and barrier function, the first and second A1 layers 5. The thickness of 6 is required to be at least 1000 Å or more.
また、Cuの比抵抗は前述のように八1の2部3程度で
あるので、従来の厚さ1μmのAl配線と同等の配線抵
抗を得るためのCu被膜配線7の厚さは、上記第1、第
2のA1層5.6の存在を考慮して6000人程度以上
有れば充分である。In addition, since the specific resistance of Cu is about 81:2 parts 3 as mentioned above, the thickness of the Cu coated wiring 7 to obtain the same wiring resistance as the conventional 1 μm thick Al wiring is as follows. 1. Considering the existence of the second A1 layer 5.6, it is sufficient to have about 6,000 or more people.
上記本発明に係るCu被膜配線7は、例えば以下に第2
図(81〜(elを参照して説明する方法により形成さ
れる。The Cu coated wiring 7 according to the present invention described above can be used, for example, in the following manner.
It is formed by the method described with reference to FIGS.
第2図Fal参照
即ち先ず、p型Si基板1に通常の方法により半導体素
子を構成するn゛型被拡散領域2形成され、通常通り熱
酸化及び化学気相成長(CVD)により該基板上に例え
ば6000〜8000人程度の厚さのS入定□下層絶縁
膜3が形成され、通常のりソグラフィ技術により該下層
絶縁膜3にn゛型被拡散領域2表出する配線コンタクト
窓4が形成されてなる被処理基板上に、通常のスパッタ
リング法を用いて厚さ1000人程度0第1のAI層5
、厚さ6000〜8000人程度のCu被膜入定7、厚
さ1000人程度0第2の11層6を順次形成する。Refer to FIG. 2 Fal. That is, first, an n-type diffusion region 2 constituting a semiconductor element is formed on a p-type Si substrate 1 by a conventional method, and then a diffusion region 2 is formed on the substrate by thermal oxidation and chemical vapor deposition (CVD) as usual. For example, a lower layer insulating film 3 having a thickness of about 6,000 to 8,000 layers is formed, and a wiring contact window 4 exposing the n-type diffusion region 2 is formed in the lower layer insulating film 3 by ordinary lamination technology. A first AI layer 5 with a thickness of about 1,000 layers is deposited on the substrate to be processed using a normal sputtering method.
, a Cu coating 7 with a thickness of about 6,000 to 8,000 layers, and a second 11 layer 6 with a thickness of about 1,000 layers are sequentially formed.
第2図(b)参照
次いでCVD法により上記第2のA1層6上に厚さ20
00人程度0窒化チタン(TiN)膜109を形成し、
該TiN膜109上に配線パターンに対応する形状のレ
ジスト膜パターンIOを形成し、該レジスト膜パターン
IOをマスクにし、塩素系のガスを用いるリアクティブ
イオンエツチング(RIE)処理によりTiN膜109
と第2のA1層6とを選択的にエツチング除去する。Referring to FIG. 2(b), a thickness of 20 mm is then deposited on the second A1 layer 6 by the CVD method.
About 00 people form a titanium nitride (TiN) film 109,
A resist film pattern IO having a shape corresponding to the wiring pattern is formed on the TiN film 109, and using the resist film pattern IO as a mask, the TiN film 109 is etched by reactive ion etching (RIE) using chlorine gas.
and the second A1 layer 6 are selectively etched away.
第2図FC+参照
次いで、レジスト膜パターン10を除去した後、上記エ
ツチング処理によって形成された配線パターンに対応す
る形状を有するTiN膜109によるパターン即ちTi
N膜パターン9をマスクにし、通常のアルゴンを用いる
イオンビームエツチング(イオンミーリング)処理によ
りCu被膜107を選択エツチングする。ここでCu被
膜配線7のパターンが形成される。Refer to FIG. 2 FC+ Next, after removing the resist film pattern 10, a pattern of TiN film 109 having a shape corresponding to the wiring pattern formed by the above etching process, that is, a Ti
Using the N film pattern 9 as a mask, the Cu film 107 is selectively etched by ordinary ion beam etching (ion milling) using argon. Here, a pattern of Cu film wiring 7 is formed.
第2図(di参照
次いで更に上記TiN膜パターン9をマスクにし塩素系
のガスによるRIB処理により第1のAt層5を選択的
にエツチング除去し、続いてオーバエツチングを行って
TiN膜パターン9を除去することによって、下面に第
1のAI層5を有し上面が第2の41層6で覆われた本
発明に係るCu被膜配線7が形成される。FIG. 2 (see di) Next, using the TiN film pattern 9 as a mask, the first At layer 5 is selectively etched and removed by RIB treatment using chlorine-based gas, and then over-etching is performed to remove the TiN film pattern 9. By removing it, a Cu-coated wiring 7 according to the present invention having a first AI layer 5 on the lower surface and covered with a second 41 layer 6 on the upper surface is formed.
第2図tel参照
次いで該配線形成面上にCVD法によりPSG被覆絶縁
膜8が形成される。Refer to FIG. 2 (tel) Next, a PSG covering insulating film 8 is formed on the wiring formation surface by the CVD method.
そして以後図示しないポンディングパッドの表出、ダイ
シング、ボンディング等がなされて本発明に係る半導体
装置が完成せしめられる。Thereafter, the semiconductor device according to the present invention is completed by exposing the bonding pads (not shown), dicing, bonding, etc.
上記実施例に示されるように本発明に係る半導体装置に
おいては、上面に被覆絶縁膜気相成長時の高温処理にお
いてCuの酸化を防止する第2のAI層6を設け、且つ
下面に上記高温処理におけるCuのSi基体内への拡散
を阻止する第1のA1層5を設けることによって配線及
び半導体素子を劣化させる欠点を除去して、比抵抗がA
Iより小さく、且つエレクトロマイグレーション及びス
トレスマイグレーシロンに対する耐性がΔ1に比べて格
段に大きいCuを、回路形成用の被膜配線として用いた
。As shown in the above embodiments, in the semiconductor device according to the present invention, the second AI layer 6 is provided on the upper surface to prevent Cu from being oxidized during high-temperature treatment during vapor phase growth of a coating insulating film, and the lower surface is provided with the By providing the first A1 layer 5 that prevents Cu from diffusing into the Si substrate during processing, defects that degrade wiring and semiconductor elements can be eliminated, and specific resistance can be reduced to A1.
Cu, which is smaller than I and has much higher resistance to electromigration and stress migration than Δ1, was used as a film wiring for circuit formation.
従って配線抵抗が従来より低く形成できるので半導体装
置の性能は向上し、且つ断線が防止されるので半導体装
置の信頼度寿命が向上する。Therefore, the performance of the semiconductor device is improved because the wiring resistance can be lowered than in the past, and the reliability and life of the semiconductor device is improved because disconnection is prevented.
以上説明のように本発明によれば回路を構成する被膜配
線の抵抗が減少し、且つマイグレーションによる断線も
防止されるので、半導体装置の性能及び信頼度寿命が向
上する。As described above, according to the present invention, the resistance of the film wiring constituting the circuit is reduced, and disconnection due to migration is also prevented, thereby improving the performance and reliability of the semiconductor device.
第1図は本発明の一実施例を示す模式側断面図、
第2図(al〜(elは本発明に係るCu配線の形成方
法の工程断面図である。
図において、
1はp型St基板、 2はn゛゛拡散領域、3は下層
絶縁膜、 4ば配線コンタクト窓、5は第1のへ1層
、 6は第2のへ1層、7はCu被膜配線、 8
は被覆絶縁膜、9はTiN膜パターン、lOはレジスト
パターン、107はCu被膜、 109はTiN膜
ネ 1 図FIG. 1 is a schematic side cross-sectional view showing an embodiment of the present invention, and FIG. Substrate, 2 is an n diffusion region, 3 is a lower insulating film, 4 is a wiring contact window, 5 is a first layer, 6 is a second layer, 7 is a Cu film wiring, 8
1 is a coating insulating film, 9 is a TiN film pattern, 1O is a resist pattern, 107 is a Cu film, and 109 is a TiN film.
Claims (1)
被膜配線(7)を備えてなることを特徴とする半導体装
置。A semiconductor device comprising a copper film wiring (7) whose upper and lower surfaces are covered with aluminum layers (5) and (6).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23503086A JPS6388843A (en) | 1986-10-02 | 1986-10-02 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23503086A JPS6388843A (en) | 1986-10-02 | 1986-10-02 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6388843A true JPS6388843A (en) | 1988-04-19 |
Family
ID=16980040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23503086A Pending JPS6388843A (en) | 1986-10-02 | 1986-10-02 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6388843A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5430258A (en) * | 1991-10-09 | 1995-07-04 | Sony Corporation | Copper interconnection structure and method of preparing same |
-
1986
- 1986-10-02 JP JP23503086A patent/JPS6388843A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5430258A (en) * | 1991-10-09 | 1995-07-04 | Sony Corporation | Copper interconnection structure and method of preparing same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3149846B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH01202841A (en) | Semiconductor integrated circuit device and manufacture thereof | |
JPS6364057B2 (en) | ||
JP2600593B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2000068269A (en) | Semiconductor device and manufacture thereof | |
JPS6388843A (en) | Semiconductor device | |
JPH06177200A (en) | Formation of semiconductor integrated circuit device | |
JPH01255250A (en) | Forming method for multilayer interconnection | |
JP2900522B2 (en) | Semiconductor device | |
JP3014887B2 (en) | Semiconductor device and manufacturing method thereof | |
JPS5863150A (en) | Manufacture of semiconductor device | |
JP3510943B2 (en) | Method for manufacturing semiconductor device | |
JP2723023B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH02271628A (en) | Semiconductor device | |
KR0139599B1 (en) | Mechod of forming metal wiring in semiconducotr device | |
JPH0547764A (en) | Semiconductor device and its manufacture | |
JPS6160580B2 (en) | ||
JPH03250627A (en) | Semiconductor device and manufacture thereof | |
KR100240268B1 (en) | Method for forming metal wiring in semiconductor device | |
JPH04214630A (en) | Manufacture of semiconductor device | |
JPH10223753A (en) | Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device | |
JPH04186729A (en) | Semiconductor device | |
JPS63257268A (en) | Semiconductor integrated circuit | |
JPH06275725A (en) | Manufacture of semiconductor device | |
JPS61224415A (en) | Manufacture of semiconductor device |