JPH01255250A - Forming method for multilayer interconnection - Google Patents

Abstract

PURPOSE:To improve aluminium electromigration and stress migration resistance, and to obtain a forming method for multilayer interconnection, of Al-Si alloy for preventing the interconnection from disconnecting by covering Al-Si alloy interconnection of a lower layer with a cap layer made of Ti or Ti compound. CONSTITUTION:After low layer aluminium alloy interconnection 5 having a cap layer 9 on its upper face made of titanium or titanium compound is formed when a multilayer interconnections are formed of aluminium alloy interconnections containing silicon as lower and upper layer interconnections, an interlayer insulating film 6 is formed on the forming face of the interconnection 5 having the layer 9 on its upper face. Then, a contact window 7 for exposing the layer 9 on the interconnection 5 is formed at the film 6, the layer 9 exposed in the window 7 is removed to immediately expose the interconnection 5 in the window 7, upper layer aluminium alloy interconnection 8 in direct contact with the interconnection 5 is formed in the window 7 on the film 6.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a method for forming multilayer wiring, especially a method for forming multilayer wiring using upper and lower layer wiring made of an aluminum (AI) alloy containing silicon (Si), 8I. The purpose of this study is to provide a method for forming multilayer wiring using an Al-Si alloy that greatly improves electromigration and stress migration resistance and prevents the occurrence of disconnections. When forming a multilayer wiring, the lower layer A1 has a cap layer made of titanium (Ti) or a Ti compound on the upper surface.
After forming the alloy wiring, an interlayer insulating film is formed on the lower layer AI alloy wiring formation surface having the cap layer on the upper surface, and a contact window is formed in the interlayer insulating film to expose the cap layer on the lower layer ^1 alloy wiring. The cap layer exposed in the contact window is removed to directly expose the 1-alloy wiring to the lower layer in the contact window, and then the lower layer is formed on the interlayer insulating film in the contact window. The structure includes a step of forming a 1 alloy wiring in an upper layer directly in contact with the A1 alloy wiring.

[Industrial application field]

The present invention relates to a method for forming multilayer wiring, particularly to an improvement in a method for forming multilayer wiring using upper and lower layer wiring made of an AI alloy containing Si.

In highly integrated semiconductor ICs such as LSIs, short channel MO3I transistors are being used to improve the degree of integration and increase speed. In order to prevent this, source and drain regions are becoming extremely shallow.

On the other hand, pure AI, which has low resistance, is cheap, and is easy to form, has been mainly used for the wiring of semiconductor ICs;
Since the solid solubility of Si in I is relatively large, the AI
There is a problem that the Si base box in the part where the wiring contacts is eaten by the first wiring, and the interface between the old and Si moves to the deep side of the substrate.
If the junction in the drain region is formed shallowly, a problem arises in that the junction is destroyed by the solid solution reaction at the AI-5i interface and the device characteristics are impaired.

Therefore, in order to suppress the solid solution reaction that occurs at the contact area between the AI wiring and the Si substrate, the AI-5i (1-2%) alloy containing approximately 1-2% Si in AI is used. S is increasingly being used as a wiring material for highly integrated semiconductor ICs instead of S.
Not only the lower layer wiring directly in contact with the i-plane, but also the upper layer wiring are formed of Al-5i alloy, and the Si in all wiring is
By ensuring the content ratio of is at a required value, joint breakdown due to the solid solution reaction can be prevented.

However, as mentioned above, A1 alloy wiring containing Si has the property of causing precipitation of solid solution Si due to thermal history and mechanical stress. In the above, the AI due to the precipitation of Si is
There is a problem in that the reduction in the effective cross-sectional area of wiring makes it easier for wire breakage to occur due to electromigration or stress migration, and improvements are desired.

[Conventional technology]

Conventional multi-layer wiring using Al-5i alloy wiring in the above-mentioned semiconductor RC, etc., is described below with reference to figures (al to (C)). After forming a contact window 4 exposing the surface of the impurity diffusion region 2, a lower layer Al-5i (1 to 2%) alloy is formed on the lower layer insulating film 3 in contact with the impurity diffusion region 3 at the contact window 4. Wiring 5 is formed.

Next, an interlayer insulating film 6 is formed on the surface on which the 1-5i alloy wiring 5 is formed in the lower layer by vapor phase growth means, and then the upper surface of the lower Al-5i alloy wiring 5 is formed on the interlayer insulating film 6. A selectively exposed through hole 7 is formed.

Refer to Figure 1 (C). Next, an Al-3i (1 to 5%) alloy film, which is an upper layer wiring material, is formed on the core interlayer insulating film 6 by sputtering or the like, and the Al-5i The alloy film is patterned and the lower layer AI-5i alloy is deposited on the core interlayer insulating film ll through the through hole 7! This was a method of forming an upper layer Al-3i alloy wiring 8 connected to the 1A 5.

[Problem to be solved by the invention]

However, in the multilayer wiring structure made of Al-5i alloy formed by the above-mentioned conventional method, crystalline precipitation of Si dissolved in the Al-5i alloy wiring occurs due to the thermal history and mechanical stress history received after the wiring is formed. As a result, the effective cross-sectional area of the AI-5i alloy, which contributes to electrical conductivity and stress resistance in the wiring, decreases, resulting in electromigration of AI atoms caused by increased current density and stress migration of old atoms caused by repeated stress. A problem has arisen in that the multilayer wiring is susceptible to disconnection due to such phenomena.

Therefore, conventionally, about 0.1 to 1% of copper (Cu), which has the effect of suppressing the migration (movement) of A1, was added to the Al-
An AI-5i-Cu alloy added to the 5i alloy was also tried as a material for multilayer wiring, but it could not be said to be sufficiently effective in preventing disconnection due to the migration.

Therefore, an object of the present invention is to provide a method for forming a multilayer wiring using an AI-3i alloy, which greatly improves the electromigration and stress migration resistance of AI and prevents the occurrence of disconnection.

[Means to solve the problem]

The above problem is solved when forming a multilayer wiring using 11 alloy wiring containing Si for the lower layer and upper layer wiring.
After forming the No. 1 alloy wiring, an interlayer insulating film is formed on the No. 1 alloy wiring forming surface of the lower layer having the cap layer on the upper surface, and a contact is formed on the interlayer insulation film to expose the cap layer on the lower At alloy wiring. A window is formed, the cap layer exposed in the contact window is removed to expose the lower layer A1 alloy wiring directly in the contact window, and then the lower layer A1 alloy wiring is formed on the interlayer insulating film in the contact window portion. This problem is solved by a method of forming a multilayer wiring according to the present invention, which includes a step of forming an upper layer A1 alloy wiring in direct contact with a previous alloy wiring.

[For production]

That is, in the multilayer wiring forming method of the present invention, a cap layer made of Ti or a Ti compound is deposited on the upper surface of the lower layer Al-5i alloy wiring, which is particularly intended to be miniaturized.
The movement of AI atoms in the 5i wiring due to electromigration or stress migration is suppressed to improve the migration resistance of the wiring and prevent disconnection.

Further, by selectively removing the cap layer at the contact portion with the upper layer wiring, an increase in contact resistance between the wiring layers due to the provision of the cap layer is prevented.

In this way, migration resistance is high and wire breakage does not occur.
Moreover, an AI--Si alloy multilayer interconnection having a low interlayer contact resistance equivalent to that of a conventional Al-3i alloy multilayer interconnection is formed.

〔Example〕

The present invention will be described below with reference to FIGS.
This will be specifically explained with reference to the process cross-sectional diagram shown in FIG.

FIG. 1 (see al) When forming a multilayer wiring made of Al-3i alloy by the method of the present invention, for example, the semiconductor substrate 1 on which the impurity diffusion region 2 is formed is formed by conventional thermal oxidation or vapor growth means. Single layer or multiple layers, thickness 0.5~
A lower insulating film 3 of about 1 μm is formed, and then a contact window 4 exposing the impurity diffusion region 2 is formed in the lower insulating film 3 by conventional photolithography, and then a conventional sputtering method or the like is formed on the substrate. The thickness is 0.
For example, Al-5i (1-2%) in the lower layer of about 5-1 μm
An alloy film 105 is formed, and then the Al-5i (1 to 2%
) A titanium nitride (TiN) cap layer 9 having a thickness of, for example, about 100 to 1000 layers is formed on the alloy film 105 by sputtering.

Referring to FIG. 1(b), the TiN cap N is then
A resist pattern (not shown) corresponding to the lower layer wiring is formed on the 109, and using the resist pattern as a mask, reactive ion etching (
TiN cap layer 9 and lower layer Al-5 are formed by RIE) process.
i (1 to 2%) alloy film 105 is patterned to form a lower layer AI-3i (1 to 2 %) Form alloy wiring 5.

Referring to FIG. 1(C), an interlayer insulating film 6 made of phosphosilicate glass (PSG) or the like with a thickness of about 0.5 to 1 μm is then formed on the substrate by vapor phase growth in the conventional manner. A through pole 7 exposing the TiN cap layer 9 on the lower wiring 5 is formed in the interlayer insulating film 6 by conventional photolithography using R11'i treatment using methane fluoride (CIIFl).

Referring to FIG. 1(d), the TfN cap N9 exposed in the through hole 7 is removed by overetching by the RICE process using the above-mentioned carbon dioxide, and the lower layer Al-5i (1 ~2%) The upper surface of the alloy wiring 5 is directly exposed.

FIG. 1 (see nl) Then, as before, an upper layer of Al--3 with a thickness of about 1 μm is deposited on the substrate having the interlayer insulation layer 6 by sputtering or the like.
5i (1-2%) alloy film is formed, and the upper Al-3i (1-2%) alloy film is patterned by normal photolithography using RIIE treatment using chlorine gas as an etching means, and the interlayer Al-3i (1-2%) alloy film is patterned. On the insulating film 6, there is an upper qAI St (L ~ 2%) directly in contact with the lower layer Al-3i (1~2%) alloy wiring 5 surface at the through pole 7 portion.
An alloy film vA8 is formed to complete the Al-3i alloy multilayer wiring according to the present invention.

As shown in the above embodiments, in the At-3i alloy multilayer wiring according to the present invention, the upper surface of the lower layer AI-5i alloy wiring 5, which is particularly miniaturized and where AI migration is likely to occur, is coated with, for example, TiN, which is a Ti compound. A cap layer 9 consisting of the through hole 7 is deposited to suppress the migration of one atom to prevent disconnection due to migration of the through hole 7.
The cap layer 9 at the contact portion with the upper layer At-5i alloy wire 8 is selectively removed, and the lower layer At-5i alloy wire 5 and the upper layer AI-3i alloy wire 8 are directly connected. Low contact resistance is maintained.

If there is a possibility that AI migration may occur in the upper layer Al-5i alloy wiring, a cap layer made of Ti or a Ti compound and similar to the above embodiment is of course formed on the upper layer Al-3i alloy wiring.

〔Effect of the invention〕

As described above, according to the present invention, disconnection due to AI migration in a multilayer wiring made of an AI-3i alloy can be prevented, and the contact resistance between wiring layers can be maintained at a low value.

Therefore, the present invention is effective in improving the performance and reliability of semiconductor RCs and the like that use multilayer wiring made of Al-5i alloy.

[Brief explanation of the drawing]

FIG. 1 (al~(81) is a process cross-sectional view of an embodiment of the present invention, FIG. 2 (8)~(C+ is a process cross-sectional view of a conventional method. In the figure, l is a semiconductor substrate, 2 is an impurity 3 is a lower layer insulating film, 4 is a contact window, 5 is a lower layer Al-3i (1~2%) alloy wiring, 6 is an interlayer insulating film, 7 is a through hole, 8 is an upper layer old-5i (1~2%) %) alloy wiring, 9 indicates the TiN camp layer, and 105 indicates the lower layer AI-5i (1-2%) alloy film.

Claims (1)

[Claims] When forming a multilayer wiring using aluminum alloy wiring containing silicon for the lower layer and upper layer wiring, after forming the lower layer aluminum alloy wiring having a cap layer made of titanium or a titanium compound on the upper surface, An interlayer insulating film is formed on a lower aluminum alloy wiring formation surface having a cap layer on the upper surface, a contact window is formed in the interlayer insulating film to expose the cap layer on the lower aluminum alloy wiring, and a contact window is formed in the interlayer insulating film to expose the cap layer on the lower aluminum alloy wiring. The cap layer to be exposed is removed to directly expose the lower aluminum alloy wiring within the contact window, and then the upper aluminum alloy wiring is placed on the interlayer insulating film in direct contact with the lower aluminum alloy wiring at the contact window. A method for forming multilayer wiring, the method comprising the step of forming wiring.