JPH03262125A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03262125A JPH03262125A JP6194390A JP6194390A JPH03262125A JP H03262125 A JPH03262125 A JP H03262125A JP 6194390 A JP6194390 A JP 6194390A JP 6194390 A JP6194390 A JP 6194390A JP H03262125 A JPH03262125 A JP H03262125A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- alloy
- metallic
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 229910000676 Si alloy Inorganic materials 0.000 claims description 3
- WCCJDBZJUYKDBF-UHFFFAOYSA-N copper silicon Chemical compound [Si].[Cu] WCCJDBZJUYKDBF-UHFFFAOYSA-N 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 24
- 229910052751 metal Inorganic materials 0.000 abstract description 24
- 229910045601 alloy Inorganic materials 0.000 abstract description 13
- 239000000956 alloy Substances 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 12
- 230000005012 migration Effects 0.000 abstract description 8
- 238000013508 migration Methods 0.000 abstract description 8
- 229910016344 CuSi Inorganic materials 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、さらに詳しくは、半導
体装置における金属配線膜の改良構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an improved structure of a metal wiring film in a semiconductor device.
従来例における配線技術を適用した半導体回路装置のう
ち、ここでは、特に配線材料として、Ａｌ５ｆあるいは
Ａｌ５ｉＣｕを使用した場合のコンタクトホール部での
模式的な断面構成を第２図に示しである。FIG. 2 shows a schematic cross-sectional configuration at a contact hole portion of a semiconductor circuit device to which conventional wiring technology is applied, in which Al5f or Al5iCu is used as the wiring material.
すなわち、この第２図に示す従来例による装置構成にお
いて、１はシリコン半導体基板であり、２はこのシリコ
ン半導体基板１上に形成された、シリコン酸化膜からな
る第１層絶縁膜であり、３は層間絶縁膜であり、４はＡ
ｌＳｉあるいはＡｔ５ｉＣｕを材料として使用した金属
配線膜であり、５はゲートであり、６はコンタクトホー
ル部であり、８は素子間分離部である。That is, in the conventional device configuration shown in FIG. 2, 1 is a silicon semiconductor substrate, 2 is a first layer insulating film made of a silicon oxide film formed on this silicon semiconductor substrate 1, and 3 is a silicon semiconductor substrate. is an interlayer insulating film, and 4 is A
It is a metal wiring film using lSi or At5iCu as a material, 5 is a gate, 6 is a contact hole part, and 8 is an isolation part.
ここで、シリコン半導体基板１上での第１層絶縁膜２及
び層間絶縁膜３を選択的にエツチングし、そのエツチン
グマスクに用いたレジストを除去した後に、これらの上
に第１層金属配線膜４を形成することにより、前記第２
図に見られるような断面構造の装置構成が得られる。Here, after selectively etching the first layer insulating film 2 and interlayer insulating film 3 on the silicon semiconductor substrate 1 and removing the resist used as an etching mask, a first layer metal wiring film is formed on them. 4, the second
A device configuration having a cross-sectional structure as shown in the figure is obtained.
しかして、この装置構成の場合、素子構成の微細化の要
望にともない、配線断面積が減少し、金属配線部におい
て、エレクトロマイグレーションあるいは、ストレスマ
イグレーション等、配線の断線が生じ、信転性に係わる
問題が生じてきた。However, in the case of this device configuration, with the demand for miniaturization of the element configuration, the cross-sectional area of the wiring is reduced, and disconnection of the wiring due to electromigration or stress migration occurs in the metal wiring part, which affects reliability. A problem has arisen.
このように、従来のＡｌＳｉ、、Ａｌ５ｉＣｕを用いた
金属配線においては、素子の微細化に伴ない、電流密度
の上昇に伴なう、エレクトロマイグレーション、あるい
は、配線に加わる応力に起因するストレスマイグレーシ
ョンといった問題が生じてきた。In this way, in conventional metal wiring using AlSi, Al5iCu, as elements become smaller, electromigration occurs due to an increase in current density, or stress migration occurs due to stress applied to the wiring. A problem has arisen.
またコンタクトホールの微細化に伴ないコンタクト部に
おけるカバレージの問題や金属配線膜とシリコン半導体
基板間の相互拡散等による界面における安定性や密着性
の問題が生じてきた。Further, with the miniaturization of contact holes, problems of coverage at the contact portion and problems of stability and adhesion at the interface due to mutual diffusion between the metal wiring film and the silicon semiconductor substrate have arisen.
さらには、金属配線部におけるヒロック発生といった問
題が生じてきた。Furthermore, problems have arisen, such as the occurrence of hillocks in metal wiring sections.
この発明は、上記のような問題点を解消するためになさ
れたもので、金属配線における耐エレクトロマイグレー
ション特性及び耐ストレスマイグレーション特性の向上
が図れ、また配線の強度を高め、低抵抗化することがで
きる半導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to improve the electromigration resistance and stress migration resistance of metal wiring, and also to increase the strength of the wiring and reduce the resistance. The purpose is to obtain a semiconductor device that can be used.
この発明に係る半導体装置は、金属配線材として、シリ
コン元素を０．０５ないし１５ａｔ％含有する銅シリコ
ン合金を用いたものである。A semiconductor device according to the present invention uses a copper-silicon alloy containing 0.05 to 15 at% silicon element as a metal wiring material.
この発明においては、金属配線材料として、Ｃｕ５ｉ系
合金を用いることにより、配線の強度を向上させかつ、
低抵抗化することができ、また耐ストレスマイグレーシ
ョン特性及び耐エレクトロマイグレーション特性を向上
させることができる。In this invention, the strength of the wiring is improved by using a Cu5i alloy as the metal wiring material, and
The resistance can be lowered, and the stress migration resistance and electromigration resistance can be improved.
以下、この発明を適用した半導体装置の一実施例につき
第１図を参照して詳細に説明する。Hereinafter, one embodiment of a semiconductor device to which the present invention is applied will be described in detail with reference to FIG.
第１図は、この実施例を適用した半導体装置の概要を模
式的に示す断面構造図であり、この第１図の実施例にお
いて、前記第２図の構成と同一または相当部分を示して
いる。FIG. 1 is a cross-sectional structural diagram schematically showing the outline of a semiconductor device to which this embodiment is applied, and in the embodiment of FIG. 1, the same or equivalent parts as the structure of FIG. .
この第１図の実施例においても、シリコン半導体１上に
あって、まず、酸化膜層２を形成し、次にゲート電極３
を形成した後、層間絶縁膜としての第１層絶縁膜３を形
成し、その後、第１層絶縁膜を選択的にエツチングし、
そのマスクに用いたレジストを除去した後に、これらの
上層として配線材と異なる金属材料からなる金属層、例
えばバリアメタル７を形成し、更にその後スパッタある
いはＣＶＤ技術を用いてＣｕ５ｉにより金属配線４を形
成する。In the embodiment shown in FIG. 1, an oxide film layer 2 is first formed on a silicon semiconductor 1, and then a gate electrode 3 is formed.
After forming, a first layer insulating film 3 is formed as an interlayer insulating film, and then the first layer insulating film is selectively etched,
After removing the resist used for the mask, a metal layer made of a metal material different from the wiring material, for example, a barrier metal 7, is formed as an upper layer, and then a metal wiring 4 is formed of Cu5i using sputtering or CVD technology. do.
以上のように構成されるこの実施例装置においては、金
属配線部における強度を向上させることができる。同時
に、耐ストレスマイグレーション特性及び耐エレクトロ
マイグレーション特性を向上させることができる。また
例えばＣｕ−１ａｔ％Ｓｉの電気抵抗率は１．７３μΩ
ｃｍであり、Ａｌ−１ａｔ％Ｓｔの電気抵抗率は２．７
３μΩｃｍであり、Ｃｕ５ｉ合金は、ＡｌＳｉ合金に比
べ低抵抗であるので、金属配線部における電気信号の伝
達遅延及び発熱を抑えることができる。In this embodiment device configured as described above, the strength of the metal wiring portion can be improved. At the same time, stress migration resistance and electromigration resistance can be improved. For example, the electrical resistivity of Cu-1at%Si is 1.73μΩ
cm, and the electrical resistivity of Al-1at%St is 2.7
Since the Cu5i alloy has a lower resistance than the AlSi alloy, the electrical signal transmission delay and heat generation in the metal wiring can be suppressed.
また、コンタクトホール部において配線材料とは異なる
材料である’ｌ’ ｉ、Ｔａ、Ｍｏ、Ｗ等の高融点金属
あるいはこれらの金属の窒化物、珪素物、炭素物ホウ化
物等の金属材料よりなる金属層を配線膜の下層に形成す
ることにより、配線膜においてヒロックの発生を抑制し
、また配線膜にかかる応力を緩和し断線を防止し、耐ス
トレスマイグレーション特性及び耐エレクトロマイグレ
ーション特性を向上させることができる。更には、配線
膜と下層絶縁膜との界面における相互拡散を防止し、界
面における安定性及び密着性を向上させ、またヒロック
の発生を防止する。In addition, the contact hole portion is made of a high-melting point metal such as i, Ta, Mo, or W, which is a material different from the wiring material, or a metal material such as nitride, silicon, or carbon-based boride of these metals. By forming a metal layer under the wiring film, it is possible to suppress the occurrence of hillocks in the wiring film, alleviate the stress applied to the wiring film, prevent disconnection, and improve stress migration resistance and electromigration resistance. I can do it. Furthermore, mutual diffusion at the interface between the wiring film and the lower insulating film is prevented, stability and adhesion at the interface are improved, and hillocks are prevented from occurring.
更に金属配線材として、Ｃｕ５ｉ系合金にＣｕ。Furthermore, Cu is used as a metal wiring material in Cu5i alloy.
Ｓｔ以外の元素を添加した合金を用いることにより、結
晶粒界に不純物元素を析出させ、配線の強度を向上させ
ると共に、粒内の不純物含有量を低減し、低抵抗化する
ことができる。また、添加元素によるヒロックの発生の
低減もはかれる。By using an alloy to which an element other than St is added, impurity elements can be precipitated at grain boundaries, improving the strength of wiring, and reducing the content of impurities in the grains, resulting in lower resistance. Further, the occurrence of hillocks can be reduced due to the addition of elements.
ここで、本発明におけるＣｕ中へのＳｉ含有量をＱ、５
ａｔ％〜１５ａｔ％と規定したが、これは、以下に示す
理由による。Here, the Si content in Cu in the present invention is Q, 5
Although it was defined as at % to 15 at %, this is due to the following reasons.
第１の理由は、純銅（９９，９５％Ｃｕ）の引張強度は
２１．７ｋｇ／ｍ璽２であるのに対し、ＣｕＯ，５ａｔ
％Ｓｔ合金の引張強度は４０．０ｋｇＡ−程度とＳｉ含
有量がＱ、５ａｔ％を越えるあたりから、本発明に有効
な効果を発揮しだすからである。The first reason is that the tensile strength of pure copper (99.95% Cu) is 21.7 kg/m2, whereas CuO, 5at
This is because the tensile strength of the %St alloy starts to exhibit an effective effect in the present invention when the Si content exceeds Q, 5 at% and the tensile strength of the %St alloy is about 40.0 kgA-.
第２の理由は、第３図に示すＣｕ５ｉ系合金の平衡状態
図から明らかなように、Ｃｕを１）．２５％以上含有さ
れた場合、β相あるいはＴ、δ。The second reason is that Cu is 1). If it is contained in an amount of 25% or more, it becomes β phase or T, δ.
に等の組織が析出し、配線強度は上昇するが、Ｃｕ−１
５ａｔ％Ｓｉ合金の電気抵抗率は３．２μΩｃｍとなり
、Ｃｕ中のＳｉｓ度が１５ａｔ％を越えると、配線材と
して使用するのは困難となるからである。A structure such as Cu-1 precipitates, and the wiring strength increases, but
This is because the electrical resistivity of a 5 at% Si alloy is 3.2 μΩcm, and if the degree of Sis in Cu exceeds 15 at%, it becomes difficult to use it as a wiring material.
以上の理由により、ＣｕＳ ｉ合金中のＳｉ濃度を０．
５〜１５ａｔ％と定めた。For the above reasons, the Si concentration in the CuSi alloy was reduced to 0.
It was determined to be 5 to 15 at%.
なお、上記実施例では、第−層金属配線の場合について
説明したが、多層配線の場合にも上記実施例と同様の効
果を奏する。In addition, in the above embodiment, the case of the first layer metal wiring was explained, but the same effects as in the above embodiment can be obtained also in the case of multilayer wiring.
また、上記実施例では基板にシリコン基板を用いた場合
について説明したが、基板として石英・サファイア等を
使用した場合、また下層導体層としてｐｏｌｙ Ｓｉ
、高融点金属及びそのシリサイドを使用した場合にも、
上記実施例と同様の効果を奏する。Furthermore, in the above embodiments, the case where a silicon substrate is used as the substrate is explained, but when quartz, sapphire, etc. are used as the substrate, and polySi is used as the lower conductor layer.
, even when using high melting point metals and their silicides,
The same effects as in the above embodiment are achieved.
更に、上記実施例では、金属配線材としてＣｕ５ｉ（０
〜１５ａｔ％Ｓｉ）系合金を用いた場合について説明し
たが、Ｃｕ５ｉに第３元素として添加する元素としては
、Ｔｉ、Ｔｅ、Ｔａ、Ａｇ。Furthermore, in the above embodiment, Cu5i (0
Although the case where a Si-based alloy (~15 at% Si) is used has been described, the elements added to Cu5i as a third element include Ti, Te, Ta, and Ag.
ｐｔ等を添加した場合、上記実施例に示した効果が得ら
れる。なお、添加量は０．０１ａｔ％程度から上記実施
例に述べた効果を発揮し、２ａｔ％程度以上添加すると
配線材が脆化するため、０゜０１〜２ａｔ％と規定する
。When pt or the like is added, the effects shown in the above examples can be obtained. Note that the addition amount is specified to be 0.01 to 2 at.% since the effect described in the above example is exhibited from about 0.01 at.%, and the wiring material becomes brittle when added at about 2 at.% or more.
以上のように、この発明に係る半導体装置によれば、金
属配線材料としてＣｕ５ｉ （０，０５〜１５ａｔ％
Ｓｉ）系合金を用いたので、配線の強度を高め、かつ低
抵抗化することができる。同時に耐ストレスマイグレー
ション特性及び耐エレクトロマイグレーション特性の向
上が図れる。As described above, according to the semiconductor device according to the present invention, Cu5i (0.05 to 15 at%
Since the Si) based alloy is used, the strength of the wiring can be increased and the resistance can be reduced. At the same time, stress migration resistance and electromigration resistance can be improved.
第１Ｍはこの発明の実施例を適用した半導体装置の概要
を模式的に示す断面構造図、第２図は従来例による同上
半導体装置の概要を模式的に示す断面構造図、また第３
図は、Ｃｕ−３ｉ系合金の平衡状態図である。
１・・・シリコン半導体基板、２・・・Ｓｉ酸化膜、３
・・・層間絶縁膜、４・・・第１層金属配線膜、５・・
・ゲート電極、６・・・コンタクトホール、７・・・金
属層、８・・・素子間分離部。
なお図中同一符号は同−又は相当部分を示す。1M is a cross-sectional structural diagram schematically showing the outline of a semiconductor device to which an embodiment of the present invention is applied; FIG. 2 is a cross-sectional structural diagram schematically showing the outline of the same semiconductor device according to a conventional example;
The figure is an equilibrium state diagram of a Cu-3i alloy. 1... Silicon semiconductor substrate, 2... Si oxide film, 3
... Interlayer insulating film, 4... First layer metal wiring film, 5...
- Gate electrode, 6... Contact hole, 7... Metal layer, 8... Inter-element isolation section. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
れた半導体装置において、 上記配線層がシリコン元素を０．０５ないし１５ａｔ％
含む銅・シリコン合金よりなることを特徴とする半導体
装置。(1) In a semiconductor device in which an element and a wiring layer thereof are formed on a semiconductor substrate, the wiring layer contains silicon element by 0.05 to 15 at%.
A semiconductor device characterized by being made of a copper-silicon alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06194390A JP3178605B2 (en) | 1990-03-12 | 1990-03-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06194390A JP3178605B2 (en) | 1990-03-12 | 1990-03-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03262125A true JPH03262125A (en) | 1991-11-21 |
| JP3178605B2 JP3178605B2 (en) | 2001-06-25 |
Family
ID=13185778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06194390A Expired - Fee Related JP3178605B2 (en) | 1990-03-12 | 1990-03-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3178605B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227958A (en) * | 2002-05-08 | 2007-09-06 | Nec Electronics Corp | Semiconductor device |
| US7687917B2 (en) | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102573524B1 (en) * | 2021-08-12 | 2023-08-31 | 김기영 | Patch with blood circulation improvement fuction |
-
1990
- 1990-03-12 JP JP06194390A patent/JP3178605B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227958A (en) * | 2002-05-08 | 2007-09-06 | Nec Electronics Corp | Semiconductor device |
| US7687917B2 (en) | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
| US7737555B2 (en) | 2002-05-08 | 2010-06-15 | Nec Electronics Corporation | Semiconductor method having silicon-diffused metal wiring layer |
| US7842602B2 (en) | 2002-05-08 | 2010-11-30 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
| US8115318B2 (en) | 2002-05-08 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
| US8642467B2 (en) | 2002-05-08 | 2014-02-04 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3178605B2 (en) | 2001-06-25 |
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