JPS59148350A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59148350A
JPS59148350A JP2350283A JP2350283A JPS59148350A JP S59148350 A JPS59148350 A JP S59148350A JP 2350283 A JP2350283 A JP 2350283A JP 2350283 A JP2350283 A JP 2350283A JP S59148350 A JPS59148350 A JP S59148350A
Authority
JP
Japan
Prior art keywords
film
aluminum
wiring layer
thin film
titanium nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2350283A
Other languages
Japanese (ja)
Inventor
Ichiro Fujita
一郎 藤田
Hideaki Otake
秀明 大竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2350283A priority Critical patent/JPS59148350A/en
Publication of JPS59148350A publication Critical patent/JPS59148350A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a conductive film of high reliability with good efficiency by adhering an aluminum film on a substrate, adhering a titanium nitride thin film, and changing said films into a wiring layer by patterning. CONSTITUTION:The first aluminum film 12 is adhered on the semiconductor substrate 11, and further the titanium nitride thin film 13 is formed. The thin film 13 and the aluminum film 12 are selectively dry-etched and thus patterned, resulting in the formation of the wiring layer. After forming an insulation film 14 on this wiring layer, a desired connection window 15 is selectively etched, and said films 14 and 13 are removed. An aluminum wiring layer 16 is adhered over the entire surface by a sputtering method, and a resist film 17 is applied.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置の製造方法に係り、特に半導体集積
回路素子表面に形成する導電配線層の形成方法の改善に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a conductive wiring layer formed on the surface of a semiconductor integrated circuit element.

(b)  従来技術と問題点 半導体集積回路(工0)は多数の能動調子や受動素子が
半導体基板に設けられ、これら相互間は導電配線層で接
続嘔れる。その導電配線層としてアルミニウム膜が良く
用いられておシ、該ア/レミニクム膜は層間絶縁膜を介
在させて高集積化のため多層構造に形成されている。
(b) Prior Art and Problems In a semiconductor integrated circuit (process 0), a large number of active elements and passive elements are provided on a semiconductor substrate, and these elements are connected to each other through conductive wiring layers. An aluminum film is often used as the conductive wiring layer, and the aluminum film is formed into a multilayer structure with an interlayer insulating film interposed therebetween for high integration.

このような多層構造のアルミニウム配線層は従来方法に
おいては第1図に示すごとく通常の7バツタ法などによ
って半導体基板1上に全面にアルミニウム配線層を被着
させた後、レジスト膜をマスクとして通常のドライエツ
チング法によって選択的にエツチングして第17μミニ
ウム(Al)配線パターン2を形成し、該第1Al配線
パターン2を含む半導体基板1上に通常の(、VD法な
どによって層間絶縁膜たとえば燐シリゲートガラス膜(
PSG膜)3を形成する。しかしながらこの場合PSG
膜3を成長する際に前記第1A[配線パターンは約42
5℃の高温処理されるため、アルミニウム結晶は縦方向
に再配列して図示したように該AI配線パターン2上に
突超4を生ずる現象がある。そのため第2図に示すよう
に前記絶縁膜8の所定位置に接続窓5を選択的にプラズ
マエツチングによって開口した後、第2kl配線層6を
被着し該第21ffi線層をパターンニングするため、
レジスト膜7を壁布し、マスク合わせを行なう際にII
I記朶起4上のA点のレジスト膜7が。
In the conventional method, an aluminum wiring layer with such a multilayer structure is formed by depositing an aluminum wiring layer on the entire surface of the semiconductor substrate 1 by the usual 7-butter method or the like as shown in FIG. A 17-μm aluminum (Al) wiring pattern 2 is formed by selectively etching using the dry etching method of Silicate glass film (
A PSG film) 3 is formed. However, in this case PSG
When growing the film 3, the first A [wiring pattern is about 42
Because of the high temperature treatment at 5° C., the aluminum crystals are rearranged in the vertical direction, resulting in the formation of protrusions 4 on the AI wiring pattern 2, as shown in the figure. Therefore, as shown in FIG. 2, after connecting windows 5 are selectively opened in predetermined positions of the insulating film 8 by plasma etching, the second kl wiring layer 6 is deposited and the 21st ffi wiring layer is patterned.
II when applying the resist film 7 and performing mask alignment.
The resist film 7 at point A on I-note 4.

ガラスマスクと突起の接触によって破損し、第2Ad配
線層6のバクーンニング工程において第3図に示すよう
に第2AA配線層6の一部(A点)が断線することがあ
った。このような第1Ad配線パターン2上に生ずる突
起4を防止する方法として1色々提案されているが、た
とえば第1i配線パターンを形成した後、その表面を陽
極酸化法によって酸化アルミニウム膜を形成する方法が
その一つとして提案されている。しかしながらとの陽厘
酸化法l−1,ガ!、17−)な調整を要し、酸化アル
ミニウム膜の薄い場合はかえって逆効果となυ後工程処
理で大きな突起を生ずる危険があり、該酸化アルミニウ
ムの厚い場合には前記接続窓5における第2Aβ配線層
6とのコンタクトがとれず該接続窓5内の酸化アルミニ
ウムを希弗酸でエツチング除去する後工程を追加すると
該接続窓5の断面形状が逆i−パー型となって第2AI
配線層6のメテツデカパレージが悪<、tυ第2A[配
線層6の断線のおそれがあった。その他の方法において
も同様に信頼性上不具合を生ずる問題があった。
It was damaged due to contact between the glass mask and the protrusions, and a part of the second AA wiring layer 6 (point A) was sometimes disconnected as shown in FIG. Various methods have been proposed to prevent such protrusions 4 from forming on the first Ad wiring pattern 2. For example, after forming the first i wiring pattern, an aluminum oxide film is formed on the surface thereof by anodizing. is proposed as one of them. However, the positive oxidation method l-1, Ga! , 17-), and if the aluminum oxide film is thin, there is a risk of producing large protrusions in the post process. If contact with the wiring layer 6 cannot be made and a post-process is added to remove the aluminum oxide in the connection window 5 by etching with dilute hydrofluoric acid, the cross-sectional shape of the connection window 5 becomes an inverted i-par type, and the second AI
If the wiring layer 6 had insufficient capacity, there was a possibility that the wiring layer 6 would be disconnected. Other methods also have similar problems in terms of reliability.

((3)  発明の目的 本発明の目的はかかる問題点に鑑みなされたもoで陽極
酸化の工程を必要とせず、アlレミニウム膜上に生ずる
突起を防止して、能率よく高信頼性導電膜を形成しうる
半導体装置の製造方法の提供にある。
((3) Purpose of the Invention The purpose of the present invention was made in view of the above problems, and it is possible to efficiently and highly reliable conductive material by eliminating the need for an anodic oxidation process and preventing protrusions from forming on the aluminum film. An object of the present invention is to provide a method for manufacturing a semiconductor device in which a film can be formed.

■ 発明の構成 その目的を達成するため2本発明の半導体装置の製造方
法は基板上にアルミニウム膜を被着シ。
■Structure of the Invention In order to achieve the object, the method for manufacturing a semiconductor device of the present invention consists of depositing an aluminum film on a substrate.

更に窒化チタン薄膜を被着した後、該量化チタン薄膜お
よびアルミニウム膜をパターンニンクシテ配線層とする
工程が含まれてなることを特徴とする。
It is characterized in that it further includes a step of forming a patterned wiring layer from the quantized titanium thin film and the aluminum film after depositing the titanium nitride thin film.

(e)  発明の実施例 以下本発明の実施例について図面を参照して説明する。(e) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

第4図乃至第7図は本発明の一実施例を説明するための
工程要部断面図である。第4図において半導体基板11
上に通常のスパッタ法にょつで約1μmの厚さの第1の
アルミニウム膜12を被着し、更に窒化チタン(TtN
)薄膜18をスパッタ法にて約1000″Aの厚さに、
該アルミニウム膜12上に被着する。この場合同一チャ
ンバ内にて形成する方がこのましい。次いで第6図に示
すようにレジスト[(図示せず)をマスクとして塩紫系
の反応ガス、たとえば四塩化炭素(CC14)或は三塩
化硼素(BO6B) l又は前記二種の混合ガスを用い
て前記窒化チタン薄膜18及びアルミニウム膜12を選
択的にドフィエッチングしてパターンニングし配線層を
形成した後レジスト膜を除去する。この場合窪化チタン
薄膜Bとアルミニウム膜12との反応ガスに対するエツ
チングレートをほぼ同一にえらべるため良好なパターン
ニングの形成が可能である、次いで半導体基板11上に
形成された配線層上通常のCVD法にょうて燐ンリクー
トグッス(PSG ) よりなる絶縁膜14を形成した
後、該絶縁膜14に所望の接続窓15を四弗化炭素(O
F4)と酸素(0りの混合ガスによってレジスト膜(図
示せず)をマスクとして選択的にエツチングして該接続
窓15内の絶縁膜14及び窒化チタン薄膜13を除去す
る。この場合アルミニウム膜I2はPSG成長時におい
て約425しの高温にさらされるが1〜ルミニウム面に
アルミニウム(AJ?)とンリコン(Sx)ともKiし
ない窒化チタン薄膜18によって被覆されているため、
前述したようなA4原子の再配列による突起を生ずるこ
とはない。次いでレジスト膜を除去し、第7図に示すよ
うに第2のアルミニウムへ線層16を全面にスパッタ法
によって被着し、該アルミニウム配線層上にレジスト膜
17を塗布してマスク合わせを行なう際に前述した突起
がないため該レジスト膜17の破損を生ずることなくパ
ターンニングが可能となる。従って該パターンニングレ
ジスト膜17をマスクとして、第2層目のアルミニウム
配線層16は断線することなくパターンニング形成され
る。
FIG. 4 to FIG. 7 are cross-sectional views of important parts of the process for explaining one embodiment of the present invention. In FIG. 4, the semiconductor substrate 11
A first aluminum film 12 with a thickness of about 1 μm is deposited thereon by ordinary sputtering, and titanium nitride (TtN
) Thin film 18 is sputtered to a thickness of about 1000″A,
It is deposited on the aluminum film 12. In this case, it is preferable to form them in the same chamber. Next, as shown in FIG. 6, a salt-purple reactive gas such as carbon tetrachloride (CC14), boron trichloride (BO6B), or a mixture of the two gases is used using a resist (not shown) as a mask. Then, the titanium nitride thin film 18 and the aluminum film 12 are selectively etched and patterned to form a wiring layer, and then the resist film is removed. In this case, since the etching rates for the reactive gas of the titanium diluted thin film B and the aluminum film 12 are selected to be approximately the same, it is possible to form a good pattern. After forming an insulating film 14 made of phosphorous liquid gas (PSG), a desired connection window 15 is formed in the insulating film 14 using carbon tetrafluoride (O2).
The insulating film 14 and the titanium nitride thin film 13 within the connection window 15 are selectively etched using a resist film (not shown) as a mask using a mixed gas of F4) and oxygen (0).In this case, the aluminum film I2 is exposed to a high temperature of approximately 425°C during PSG growth, but the aluminum surface is covered with a titanium nitride thin film 18 that does not oxidize either aluminum (AJ?) or silicon (Sx).
Protrusions due to rearrangement of A4 atoms as described above do not occur. Next, the resist film is removed, and as shown in FIG. 7, a line layer 16 is deposited on the entire surface of the second aluminum wiring layer by sputtering, and a resist film 17 is applied on the aluminum wiring layer for mask alignment. Since there is no protrusion mentioned above, patterning can be performed without damaging the resist film 17. Therefore, using the patterning resist film 17 as a mask, the second aluminum wiring layer 16 is patterned without disconnection.

(ト)発明の詳細 な説明したごとく木発明罠よれば、陽極配酸化の工程を
必要とせず、1μミニウム膜上に生ずる突起を防止する
ことによって多層配線の断線事故を防止し、能率よく高
信頼性の導電膜を形成し半導体装置の信頼性向上に大き
な効果がめる。
(g) As described in detail, the invention does not require an anode oxidation process, prevents protrusions that occur on the 1 μm film, prevents disconnection accidents in multilayer wiring, and efficiently increases performance. It forms a reliable conductive film and has a great effect on improving the reliability of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は従来方法を説明するための工程要部
断面図、第4図乃至第7図は本発明の一実施例を説明す
るための工程要部断面図である。 図において11は半導体基#、12は第1の7 /V 
ミニラム膜、13は窒化チタン薄膜、14は絶縁膜15
は接続窓、16は第2のアルミニウム配線層。 17はレジスト膜を示す。 第 1 図 第2図 第3図 Δ
FIGS. 1 to 3 are sectional views of the main parts of the process for explaining the conventional method, and FIGS. 4 to 7 are sectional views of the main parts of the process for explaining one embodiment of the present invention. In the figure, 11 is the semiconductor group #, 12 is the first 7/V
13 is a titanium nitride thin film, 14 is an insulating film 15
16 is a connection window, and 16 is a second aluminum wiring layer. 17 indicates a resist film. Figure 1 Figure 2 Figure 3 Δ

Claims (1)

【特許請求の範囲】[Claims] 基板上にアルミニウム膜を被着し、更に窒化チタン薄膜
を被着した後、該窒化チタン薄膜およびアルミニウム膜
をパターンニングして配MW とfる工程が含まれてな
ることを特徴とする半導体装置の製造方法。
A semiconductor device comprising the steps of depositing an aluminum film on a substrate, further depositing a titanium nitride thin film, and then patterning the titanium nitride thin film and the aluminum film to form an MW. manufacturing method.
JP2350283A 1983-02-14 1983-02-14 Manufacture of semiconductor device Pending JPS59148350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2350283A JPS59148350A (en) 1983-02-14 1983-02-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2350283A JPS59148350A (en) 1983-02-14 1983-02-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59148350A true JPS59148350A (en) 1984-08-25

Family

ID=12112245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2350283A Pending JPS59148350A (en) 1983-02-14 1983-02-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59148350A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256654A (en) * 1985-05-09 1986-11-14 Nec Corp Formation of multilayer interconnection
JPH01255250A (en) * 1988-04-05 1989-10-12 Fujitsu Ltd Forming method for multilayer interconnection
JP2009029572A (en) * 2007-07-26 2009-02-12 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using this
JP2009126671A (en) * 2007-11-27 2009-06-11 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using the same device
JP2009126672A (en) * 2007-11-27 2009-06-11 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using the same device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256654A (en) * 1985-05-09 1986-11-14 Nec Corp Formation of multilayer interconnection
JPH01255250A (en) * 1988-04-05 1989-10-12 Fujitsu Ltd Forming method for multilayer interconnection
JP2009029572A (en) * 2007-07-26 2009-02-12 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using this
JP2009126671A (en) * 2007-11-27 2009-06-11 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using the same device
JP2009126672A (en) * 2007-11-27 2009-06-11 Panasonic Electric Works Co Ltd Material feeding device and manufacturing device of laminated plate using the same device

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