JPH01212439A - Processing of interlayer film - Google Patents
Processing of interlayer filmInfo
- Publication number
- JPH01212439A JPH01212439A JP3708588A JP3708588A JPH01212439A JP H01212439 A JPH01212439 A JP H01212439A JP 3708588 A JP3708588 A JP 3708588A JP 3708588 A JP3708588 A JP 3708588A JP H01212439 A JPH01212439 A JP H01212439A
- Authority
- JP
- Japan
- Prior art keywords
- material layer
- etching
- layer
- film
- interlayer film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011229 interlayer Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000011810 insulating material Substances 0.000 claims abstract 8
- 238000001312 dry etching Methods 0.000 claims abstract 3
- 229920000620 organic polymer Polymers 0.000 claims description 21
- 239000002861 polymer material Substances 0.000 claims description 19
- 238000001020 plasma etching Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract 3
- 239000012528 membrane Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005660 chlorination reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、層間膜の加工法に関するものであり、具体的
には、半導体層としての配線構造体における眉間膜の加
工法に関し、特に、眉間膜の平坦化に関するものである
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for processing an interlayer film, and specifically relates to a method for processing a glabella film in a wiring structure as a semiconductor layer, and in particular, It concerns flattening of the glabellar membrane.
配線構造体における眉間膜の平坦化の方法としては、種
々の方法が提案されているが、主要なものには■ガラス
フロー法、■バイアススパッタ法、■エッチバック法な
どが挙げられる。ガラスフロー法は配線層の凹凸を流動
性ガラスにより平坦化するものであるが、この方法では
ガラスの溶媒を放出するために、数百度の高温で加熱す
る必要があり、これにより配線層の膜質劣化をきたす可
能性がある。また、熱ストレスのためにガラス体にクラ
ックが生じることもある。絶縁膜のバイアススパッタ法
は、基板にバイアス電力を印加しながら絶縁物をスパッ
タするものであり、この方法の欠点は高バイアスを印加
しすぎるとデバイス特性を劣化させる危険性があること
、及び、スループットが悪いことである。また、エッチ
バック法は、配線膜上の絶縁膜凸部をレジストのエツチ
ングと同時に除去するものであり、この方法の従来技術
では、エツチング途中で絶縁物とレジストのエッチレー
トが1:1になるような条件に変えてエツチングするた
めに、レジストのエッチレートが絶縁膜の露出面積によ
り変化するということが生じ、その結果充分な平坦性が
得られないということをしばしば経験してきた。Various methods have been proposed for flattening the glabellar film in a wiring structure, and the main ones include (1) glass flow method, (2) bias sputtering method, and (2) etchback method. The glass flow method flattens the unevenness of the wiring layer using fluid glass, but this method requires heating at a high temperature of several hundred degrees in order to release the solvent in the glass, which deteriorates the film quality of the wiring layer. It may cause deterioration. Additionally, cracks may occur in the glass body due to thermal stress. The bias sputtering method for insulating films sputters an insulator while applying bias power to the substrate.The drawbacks of this method are that if too high a bias is applied, there is a risk of degrading device characteristics; The throughput is poor. In addition, the etch-back method removes the convex portion of the insulating film on the wiring film at the same time as etching the resist, and in the conventional technology of this method, the etch rate of the insulator and the resist becomes 1:1 during etching. Since etching is performed under such conditions, the etch rate of the resist varies depending on the exposed area of the insulating film, and as a result, it has often been experienced that sufficient flatness cannot be obtained.
眉間絶縁膜の表面段差が大きいと、この上に形成する配
線層のステップカバレージの悪化により配線層の断線を
きたし、歩留りを低下させる。If the surface level difference of the glabellar insulating film is large, the step coverage of the wiring layer formed thereon will deteriorate, resulting in disconnection of the wiring layer and lowering the yield.
本発明はこれらの問題点に着目してなされたもので、エ
ッチバック法により眉間膜を平坦化する工程において、
層間膜の表面段差を緩和し、完全平坦化に近い平坦性を
維持することが可能な技術を提供することにある。The present invention was made with attention to these problems, and in the process of flattening the glabellar membrane by an etch-back method,
It is an object of the present invention to provide a technique that can reduce the surface level difference of an interlayer film and maintain flatness close to perfect flatness.
本発明は、反応性イオンエツチング(RI E)を用い
て上層の有機高分子材層及び下層の層間膜をエッチバッ
クする際に、上層の有機高分子材層を途中までエツチン
グし、層間膜の頂点が表面に露出した時点で、RIEの
エツチング条件を有機高分子材層に対する層間膜のエッ
チレート比が1を越え、1.6以内の値になるように設
定し、引き続き所定の時間までエツチングすることを特
徴とするもの−である。従来の技術では、上記RIEの
エツチング条件を有機高分子材層に対する層間膜のエッ
チレート比が1になるように設定してエツチングを行な
っている。In the present invention, when etching back the upper organic polymer material layer and the lower interlayer film using reactive ion etching (RIE), the upper organic polymer material layer is etched halfway and the interlayer film is removed. When the apex is exposed to the surface, the RIE etching conditions are set so that the etch rate ratio of the interlayer film to the organic polymer material layer exceeds 1 and falls within 1.6, and etching is continued for a predetermined time. It is characterized by: In the conventional technique, etching is performed by setting the RIE etching conditions so that the etch rate ratio of the interlayer film to the organic polymer material layer is 1.
第1図A、B、Cは本発明の実施例の工程図を示す断面
図であり、以下に、本発明の加工法について説明する。FIGS. 1A, B, and C are cross-sectional views showing process diagrams of an embodiment of the present invention, and the processing method of the present invention will be explained below.
基板1の上に配線層2を形成した後、層間膜3を堆積し
、さらに、この上に有機高分子材層4を塗布し、これを
熱処理して平坦な表面を有する配線構造体を形成する(
第1図A)。After forming a wiring layer 2 on a substrate 1, an interlayer film 3 is deposited, and an organic polymer material layer 4 is further applied thereon, and this is heat-treated to form a wiring structure having a flat surface. do(
Figure 1A).
次に、このように構成された配線構造体の表面を反応性
イオンエツチング(RI E)によってエツチングし、
有機高分子材N4の表面が、眉間膜3の頂点に至るまで
エツチングを継続する0例えば、通常のRIE装置を用
い、エツチングガスにC)IF310□混合ガスを流量
比75/75SCCM、RF電力100 GW印加した
場合には、0FPRと呼ばれる有機高分子材層4のエッ
チレートは約850人/ m i mであ、る。層間膜
3の頂点から有機高分子材層4の表面までの膜厚が、例
えばlumの場合には、エツチング時間に約12分を要
する。有機高分子材層4のエツチング面が層間膜3の頂
点に達したら、次にRIHのエツチング条件を変え、有
機高分子材層4より層間膜3のエッチレートが若干大き
くなるような条件でエツチングを行なう(第1図B)、
即ち、CHF310、流量を75/40SCCM、RF
電力1250W、圧力50mTorrとすると、眉間膜
及び有機高分子材層のエッチレートはそれぞれ4001
360人/mimとなる。このような工゛ンチング条件
で眉間膜3をその頂点から0.8μm相当エツチングし
た後の眉間膜3表面の段差を観察したところ、段差はか
なり緩和されていることが明らかとなった(第1図C)
。Next, the surface of the wiring structure configured in this way is etched by reactive ion etching (RIE),
Continuing etching until the surface of the organic polymer material N4 reaches the top of the glabellar membrane 30 For example, using a normal RIE device, use C) IF310□ mixed gas as the etching gas, flow rate ratio 75/75SCCM, RF power 100. When GW is applied, the etch rate of the organic polymer material layer 4, called 0FPR, is about 850 etchings/m i m. If the film thickness from the top of the interlayer film 3 to the surface of the organic polymer material layer 4 is, for example, lum, the etching time requires about 12 minutes. When the etched surface of the organic polymer layer 4 reaches the top of the interlayer film 3, the RIH etching conditions are changed so that the etching rate of the interlayer film 3 is slightly higher than that of the organic polymer layer 4. (Figure 1B)
That is, CHF310, flow rate 75/40SCCM, RF
When the power is 1250 W and the pressure is 50 mTorr, the etch rate of the glabellar membrane and the organic polymer material layer is 4001, respectively.
360 people/mim. When observing the level difference on the surface of the glabellar membrane 3 after etching the glabellar membrane 3 by 0.8 μm from its apex under such etching conditions, it was found that the level difference was considerably reduced (first Figure C)
.
そこで、エツチング前の層間膜の表面段差をA、上述の
ような方法でエツチングした後の層間膜の表面段差をB
とし、表面平坦化率αを
α= 1−B/A
と定義し、有機高分子材WJ4に対する層間膜3のエッ
チレート比Rとαの関係を求めてみると、第2図のよう
になる。即ち、Rが1.1〜1.4の範囲ではαはほぼ
0.9の値を示しており、層間膜の表面は完全平坦化に
近いレベルにまで緩和されていることが明らかである。Therefore, the surface step of the interlayer film before etching is A, and the surface step of the interlayer film after etching by the method described above is B.
If the surface flattening rate α is defined as α=1-B/A and the relationship between α and the etch rate ratio R of the interlayer film 3 to the organic polymer material WJ4 is determined, the result will be as shown in Figure 2. . That is, when R is in the range of 1.1 to 1.4, α shows a value of approximately 0.9, and it is clear that the surface of the interlayer film is relaxed to a level close to completely flattened.
R=1のエツチング条件ではαは0.8以下であり1表
面段差は比較的大きい。実用に供するためにはαは0.
8以上必要であると考えられる。したがって、Rが1を
越え、1.6以内の値になるような条件で眉間膜3及び
有機高分子材層4をエツチングすれば平塩化に有効であ
る。Under the etching condition of R=1, α is 0.8 or less, and the level difference on one surface is relatively large. For practical use, α should be 0.
It is considered that 8 or more is necessary. Therefore, etching the glabellar membrane 3 and the organic polymer material layer 4 under conditions such that R exceeds 1 and falls within 1.6 is effective for flat chlorination.
以上説明したように1.眉間膜と有機高分子材層を同時
にエツチングする工程において、眉間膜/有機高分子材
層のエッチレート比を1を越える値、ないし、1.6以
下の値になるようにRIBのエツチング条件を設定し、
エツチングすることにより、層間膜表面の段差を著しく
軽減し、平坦性を確保できるので、上層に形成される配
線層の加工を容易にせしめ、且つ、LSIの製造歩留り
の向上を図ることができる。As explained above, 1. In the process of simultaneously etching the glabellar membrane and the organic polymer material layer, the RIB etching conditions are adjusted so that the etch rate ratio of the glabellar membrane/organic polymer material layer is greater than 1 or less than 1.6. Set,
By etching, it is possible to significantly reduce the level difference on the surface of the interlayer film and ensure flatness, thereby facilitating the processing of the wiring layer formed in the upper layer and improving the manufacturing yield of LSI.
第1図は本発明の実施例の工程を示す断面図、第2図は
有機高分子材層に対する眉間膜のエッチレート比Rと表
面平坦化率αの関係を示すものである。
1・・・基板、2・・・配線層、3・・・層間膜、4・
・・有機高分子材層
本発明の実施例の工程を示す断面図
第 1 図FIG. 1 is a sectional view showing the steps of an embodiment of the present invention, and FIG. 2 shows the relationship between the etch rate ratio R of the glabellar film to the organic polymer material layer and the surface flattening rate α. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring layer, 3... Interlayer film, 4...
...Organic polymer material layer Fig. 1 is a sectional view showing the steps of an embodiment of the present invention.
Claims (1)
この上に有機高分子材層を形成する工程と上記有機高分
子材層及び絶縁材層をドライエッチング処理する工程に
おいて、 絶縁材層の最上端に至るまで有機高分子材層をエッチン
グした後、有機高分子材に対する絶縁材のエッチレート
比が1を越え1.6以内となるようなエッチング条件で
、上記絶縁材層をドライエッチングすることを特徴とす
る層間膜の加工法。[Claims] An insulating material layer is formed on a substrate having a wiring layer, and further,
In the step of forming an organic polymer material layer thereon and the step of dry etching the organic polymer material layer and the insulating material layer, after etching the organic polymer material layer to the top of the insulating material layer, A method for processing an interlayer film, comprising dry etching the insulating material layer under etching conditions such that the etch rate ratio of the insulating material to the organic polymer material exceeds 1 and falls within 1.6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3708588A JPH01212439A (en) | 1988-02-19 | 1988-02-19 | Processing of interlayer film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3708588A JPH01212439A (en) | 1988-02-19 | 1988-02-19 | Processing of interlayer film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01212439A true JPH01212439A (en) | 1989-08-25 |
Family
ID=12487714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3708588A Pending JPH01212439A (en) | 1988-02-19 | 1988-02-19 | Processing of interlayer film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01212439A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
JPH05190684A (en) * | 1992-01-16 | 1993-07-30 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5461010A (en) * | 1994-06-13 | 1995-10-24 | Industrial Technology Research Institute | Two step etch back spin-on-glass process for semiconductor planarization |
JPH0897208A (en) * | 1995-08-11 | 1996-04-12 | Nec Corp | Plasma chemical vapor deposition method and its equipment and manufacture of multilayered interconnection |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6323337A (en) * | 1986-04-23 | 1988-01-30 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | Method of smoothening semiconductor substrate |
-
1988
- 1988-02-19 JP JP3708588A patent/JPH01212439A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6323337A (en) * | 1986-04-23 | 1988-01-30 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | Method of smoothening semiconductor substrate |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212114A (en) * | 1989-09-08 | 1993-05-18 | Siemens Aktiengesellschaft | Process for global planarizing of surfaces for integrated semiconductor circuits |
JPH05190684A (en) * | 1992-01-16 | 1993-07-30 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5461010A (en) * | 1994-06-13 | 1995-10-24 | Industrial Technology Research Institute | Two step etch back spin-on-glass process for semiconductor planarization |
JPH0897208A (en) * | 1995-08-11 | 1996-04-12 | Nec Corp | Plasma chemical vapor deposition method and its equipment and manufacture of multilayered interconnection |
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