JPS586306B2 - Handout Taisouchino Seizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for planarizing the surface of a semiconductor substrate that is uneven during the process of manufacturing a semiconductor device.

Generally, when manufacturing a semiconductor device using a semiconductor substrate, the surface of the semiconductor substrate is subjected to treatments such as impurity diffusion, formation of an insulating layer, and surface processing by photoetching.

During these treatments, the insulating layer and conductive layer on the surface of the substrate come to have raised portions or stepped portions (hereinafter, both are referred to as uneven surfaces).

When a conductive layer such as wiring or an insulating layer (hereinafter referred to as a forming layer) is further formed on such a substrate by vacuum evaporation, chemical vapor deposition, sputtering, etc., the formation layer deposited on top The layer should have a uniform thickness; it becomes thinner, especially on the sides of uneven areas, and in severe cases, it often breaks.

This significantly reduces the reliability of the deposited forming layer.

Conventionally, there is no effective method for removing such unevenness on a semiconductor substrate, and the reality is that the minimum necessary reliability is generally secured by methods such as increasing the thickness of the formation layer.

Next, the case where the above-mentioned step portion is produced in the conventional method will be explained using a planar transistor as an example.

FIG. 1 shows an outline of the manufacturing process.

Figure 1a shows the separation and diffusion process.

For example, an N-type Si layer having a conductivity opposite to that of the Si substrate 1 is provided on a Si substrate 1 having a P-type conductivity by vapor phase growth or the like.

Furthermore, a Si oxide film 4 is formed on the surface 9 of the Si layer 2 by a thermal oxidation method or the like, a part of the Si oxide film is removed by a photoetching technique, and an isolation diffusion layer having the same conductivity as the Si substrate 1 is applied to that part. A region 3 is provided.

At this time, a Si oxide film 4 is simultaneously formed on the isolation diffusion region 3.

Figure 1b shows the base diffusion step.

A part of the Si oxide film 4 on the N-type Si layer 2 separated by the isolation diffusion region 3 is removed by photoetching,
A diffusion region 5 having the same conductivity as the Si substrate 1 is provided in the N-type Si layer 2 under that portion.

At this time, a Si oxide film 4 is simultaneously formed on the diffusion region 5.

FIG. 1C shows the emitter diffusion process.

A part of the Si oxide film 4 above the diffusion region 5 is removed by photoetching, and S is added into the diffusion region 5 under that part.
A diffusion region 6 having the same conductivity as the i-layer 2 is provided.

At this time, a Si oxide film 4 is simultaneously formed on the diffusion region 6.

FIG. 1d shows the electrode wiring process, and represents the case of an emitter electrode section.

A part of the Si oxide film 4 on the diffusion region 6 is removed by photoetching, and a metal layer such as aluminum is deposited on the exposed diffusion region 6 and the oxide film 4 by a vacuum evaporation method. A state in which predetermined electrode wiring 7 has been formed is shown.

The base, collector, etc. are also wired in the same manner.

Such planar technology involves a continuous process of selective diffusion using a Si oxide film.

In order to perform this selective diffusion, it is necessary to generate a Si oxide film each time.

For this reason, the cross section of the oxide film on the surface of the semiconductor substrate inevitably has a stepped structure as shown in FIG. 1C.

The surface of the oxide film having such an uneven surface poses a major problem as a cause of disconnection during electrode wiring.

That is, at the corner portion 8 of the stepped oxide film, the metal wiring layer 7
becomes thinner, causing a disconnection accident and lowering the reliability of the semiconductor device.

In order to solve this problem, in order to provide a plurality of metal vapor deposition sources or to make the Si oxide film 4 with a stepped cross section slope,
Efforts have been made to improve the etching solution and etching method used in photoetching, but these efforts have not yet produced sufficiently satisfactory results.

Further, during exposure of the photoresist in the photoetching process, pattern accuracy is significantly reduced due to reflection of light from the step portion, which also becomes a cause of hindering improvement in the degree of integration.

Further, FIG. 2, which explains the case where the above-mentioned raised portion is produced by taking an isoplanar device as an example, shows an outline of the manufacturing process thereof.

Figure 2a shows a thin S layer formed by thermal oxidation etc. on the Si substrate 21.
A state in which an i-oxide film 22 is formed and a mask film 24 made of silicon nitride (Si3N4) having a window 23 is further provided thereon is shown.

The Si3N4 mask film 23 is normally formed by selectively etching the Si3N4 film using a Si oxide film mask (for example, by plasma etching using Freon gas).
It is formed by

FIG. 2b shows S through the window 23 of the Si3N4 mask film 24.
A state in which a portion 25 of the i-substrate 21 has been selectively removed by etching is shown.

For etching, a mixed solution of HF:HN03:water in a ratio of 1:4:4 is used.

FIG. 2C shows a state in which a SiO2 layer 26 has been selectively formed in the Si substrate 21 exposed in the above process by a thermal oxidation method.

Thermal oxidation conditions were approximately 1000°C and 20°C in dry oxygen.
Heating takes about an hour.

At this time, a raised portion 27 is generated around the selectively formed Sin2 layer 26.

This is a phenomenon that occurs due to a volume change when SiO2 is generated from Si, and is a phenomenon that cannot be avoided in isoplanar technology.

Usually, the height of the raised portion 27 is about 0.5 to 1.2 μm.

In the iso-planar technology, an active element is formed between the above SiO2 layers 26 arranged at intervals, and a metal wiring layer is further formed with an insulating film interposed therebetween.

Therefore, the wiring layer becomes thinner on the side surface of the raised portion 27.
Sometimes there is a disconnection.

In view of the above-mentioned points, the present invention is aimed at removing unevenness on a substrate that occurs in the process of manufacturing a semiconductor device, as necessary, or reducing it significantly to the extent that it does not cause any problems in practice, and forming a semiconductor device on the unevenness. It is an object of the present invention to provide a method for improving the reliability of a layer and, by extension, the reliability of a semiconductor device obtained.

In order to achieve this object, the present invention employs the method described below.

FIG. 3 is a process explanatory diagram for explaining the principle of the present invention.

First, as shown in FIG. 3a, a coating layer 32 is applied to the surface of a semiconductor substrate (or a forming layer provided on the semiconductor substrate) 310 having an uneven surface so as to fill the raised portions 33 and the stepped portions 34.
form.

The material used for the coating layer 32 is in a liquid state (including a dispersion solution) at the time of coating, and when solidified by drying etc., the material used for the coating layer 32 has an etching rate comparable to that of the semiconductor substrate (or a forming layer provided thereon) 31. It is necessary that the material has an etching rate.

Applying such a coating material to the surface of the substrate (or a layer formed thereon) 310 having an uneven surface to such an extent that it fills the uneven surface,
Once solidified, the surface of the coating layer 320 becomes flat.

Next, as shown in FIG. 3b, when the semiconductor substrate 31 on which the coating layer 32 is formed is etched using a physical etching method from the coating layer 32 side, the surface layer portion of the coating layer 320 is first removed, and then the surface layer of the coating layer 320 is removed. In addition to the coating layer 32, the raised portions 33 and stepped portions 34 are also removed at the same time.

If etching is continued further, most of the raised parts 33 and stepped parts 34 will be removed, and the surface of the substrate 310 will be flattened. As shown in FIG. If the formation layer 35 is deposited by a vapor deposition method or a sputtering method, accidents such as disconnection will not occur.

In general, materials forming the surface of a semiconductor substrate include silicon (Si), silicon oxide (Sin2), phosphosilicate glass (PSG), borosilicate glass (BSG), silicon nitride (Si3N4), wiring metal, such as aluminum (Al) is considered.

Therefore, the materials forming the surface of these semiconductor substrates and the coating layer used in the present invention need to have the same etching rate as described above.

Naturally, it is preferable that this difference in etching rate be smaller for the purpose of the present invention.

However, if the etching rate of the coating material is within a range of approximately ±50% from the etching rate of the material forming the surface of the semiconductor substrate as described above, it is within a practically usable range, and within a range of ±30%. The range is a particularly preferred range.

For example, consider a case where the difference in etching rates is 30%.

The height of a raised portion formed on a substrate during the manufacturing process of a semiconductor device is often about 0.5 to 1.2 μm.

When the present invention is applied to this raised part, the height of the raised part is approximately 0.
．． It can be 15 to 0.36 μm.

It can be said that the uneven surface of this degree is sufficiently flat for practical use in manufacturing various semiconductor devices.

Examples of such coating materials include cyclized rubber materials such as KTFR and KMBR (trade name manufactured by Kodak) OM.
Negative photoresist such as R (trade name manufactured by Tokyo Ohka Kogyo Co., Ltd.), AZI350, AZ which is a phenolic resin material
1350H, AZ111 (product name manufactured by Shipley)
Typical examples include positive photoresists such as and polyimide resins.

It goes without saying that coatable inorganic materials can also be used as long as they satisfy the properties of the coated layer.

Among these materials, those having an etching rate comparable to that of the material constituting the unevenness on the substrate surface are selected and used in appropriate combination.

The present invention will be explained in detail below using examples.

Example 1 When manufacturing a semiconductor device using a Si substrate as a semiconductor substrate, impurity diffusion and SiO2 film formation are usually performed one or more times.

During these steps, irregularities are formed on the surface of the Si substrate due to the SiO2 film.

FIG. 4a is a diagram showing an example thereof.

This figure shows a state in which an uneven SiO2 film 42 is formed on a Si substrate 41 used as a semiconductor substrate by a thermal oxidation method, a vacuum evaporation method, or a sputtering method.

In the figure, 43 is Si for impurity diffusion, for example.
Reference numeral 44 indicates a concave portion resulting from an opening formed in the O2 film, and a convex portion resulting from forming a thick locally thermally oxidized SiO2 film on the substrate.

Usually, the step h of the recess 43 is about 0.2 to 0.7 μm, and the height k of the convex portion 44 is about 0.5 to 1.2 μm.

For such a semiconductor substrate, as shown in FIG. 4b,
For example, KTF with a thickness of about 1.5 μm can be formed by coating.
A coating layer 45 of R photoresist is formed.

The coating layer may be formed by applying a coating material using a spinner or the like, and the film thickness can be controlled by adjusting the rotational speed of the spinner.

The coating layer is formed to fill in the irregularities of the SiO2 film 42, and its surface is flattened.

Next, A is applied to this Si substrate 41 from the coating layer 45 side.
Sputter etching is performed using r gas.

For example, for sputter etching under the same conditions, S
The iO2 film was etched at a rate of 5-7 Å/sec, and the KTFR photoresist was etched at a rate of about 6.5 Å/sec.
Since the etching rates of both are approximately the same, the etching progresses while the surface remains approximately flat, as shown in FIG. 4C.

When etching is carried out for about 40 minutes under the above sputter etching conditions, the entire coating layer 45 and the steps and convex portions 44 of the concave portions 43 of the SiO2 film 42 are completely removed, as shown in FIG. 4(d). The surface of the SiO2 film 42 on the Si substrate 41 is flattened.

After that, if a forming layer 46 such as a conductive layer or an insulating layer is formed thereon by, for example, a vacuum evaporation method, the forming layer will become thinner at the uneven portions as in the case of the conventional method.
No cutting defects occur, and reliability is significantly improved compared to conventional methods.

Embodiment 2 The present invention is also effective as a method for forming planar multilayer wiring.

FIG. 5a shows SiO2 formed on the surface of a semiconductor substrate 510.
A first conductor wiring layer 5 made of metal such as Al is formed on the film 52.
3, and an interlayer insulating layer 5 made of SiO2 or phosphor glass deposited thereon by a vacuum evaporation method or the like.
4 shows the state of a single layer wiring formed to a thickness of 0.5 to 1.5 μm.

Next, as shown in FIG. 5B, a coating layer 55 is formed on the interlayer insulating layer 54 using a photoresist such as KTFR or OMR or a polyimide resin to a thickness of 1 to 2 μm.

Next, the substrate 51 is etched from the surface of the coating layer 55 by sputter etching or ion milling, resulting in the result as shown in FIG. 4C.

Typical conditions for ion mm/g using Ar ions are ion energy: 7key, ion current 1.4mA
/cm2, and the substrate temperature was 150°C.

When the etching is continued further, the upper surface of the first conductor wiring layer 53 is exposed and the coating layer 55 is completely removed, as shown in FIG. 4d.

After that, the interlayer insulating layer 54 including the first conductor wiring layer 53 is
A planar type two-layer wiring is formed by depositing a second conductor wiring layer 56 thereon.

Further, the physical etching is completed in the state shown in FIG. A semi-planar type second layer wiring may be formed by forming two conductor wiring layers.

Thereafter, this method is repeated to form a planar or semi-planar multilayer wiring.

From what has been described in detail above, it is clear that these multilayer wirings formed by the present invention are extremely superior in reliability compared to multilayer wirings having large steps formed by conventional methods.

In the above embodiments, even when 8 1 3N4 or the like is used in addition to SiO2 as the interlayer insulating layer, the present invention can be applied by appropriately combining the coating materials described above.

In addition, in the above embodiments, the case where the interlayer insulating layer is etched has been explained, but in contrast, a groove or opening is formed in the insulating layer, and a conductive layer is formed on top of the groove. The present invention can also be applied to the case where conductor layers other than the above are removed and planar wiring is formed embedded in an insulating layer.

As explained above, the present invention prevents non-uniform thickness or disconnection of insulating layers and conductive layers formed on the surface of a substrate in the manufacturing process of semiconductor devices, and improves their reliability. This method has characteristics such as improving the reliability of the obtained semiconductor device, and further reducing the film thickness, interconnect spacing, and interconnect width of metal interconnects, thereby making it possible to miniaturize the semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the manufacturing process of a conventional planar transistor, FIG. 2 is a diagram explaining the manufacturing process of a conventional iso-planar semiconductor device, FIG. 3 is a diagram for explaining the principle of the present invention, and FIG. The drawings and FIG. 5 are explanatory diagrams of the manufacturing process of the embodiment of the present invention. In the figure, 31: semiconductor substrate, 32: coating layer, 33:
Raised portion, 34: Stepped portion, 35: Forming layer, 41: Si substrate, 42: SiO2 film, 43: Recessed portion, 44: Convex portion, 45:
Coating layer, 46: Forming layer, 51: Semiconductor substrate, 52: Si
O2 film, 53: first layer conductor wiring layer, 54: interlayer insulating layer,
55: Coating layer, 56: Second layer conductor wiring layer.

Claims (1)

[Claims] 1 In the manufacturing process of a semiconductor device, an uneven surface formed on an insulating layer or a conductive layer (hereinafter both referred to as a forming layer) formed on a semiconductor substrate is physically etched at an etching rate comparable to that of the forming layer. and flattening the surface of the forming layer by removing at least a portion of the applied film and the convex portions of the forming layer by a physical etching method. A method for manufacturing a featured semiconductor device.