JPH04356944A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH04356944A
JPH04356944A JP7091491A JP7091491A JPH04356944A JP H04356944 A JPH04356944 A JP H04356944A JP 7091491 A JP7091491 A JP 7091491A JP 7091491 A JP7091491 A JP 7091491A JP H04356944 A JPH04356944 A JP H04356944A
Authority
JP
Japan
Prior art keywords
film
silicon oxide
oxide film
insulating film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7091491A
Other languages
Japanese (ja)
Inventor
Shuji Mizoguchi
修二 溝口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP7091491A priority Critical patent/JPH04356944A/en
Publication of JPH04356944A publication Critical patent/JPH04356944A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To provide a semiconductor device and its manufacturing method wherein, when a contact hole is made in a layer insulating film and a wiring is formed of an Al alloy film, it is possible to restrain that impurities of baron, phosphorus or the like in the layer insulating film are diffused to the Al alloy layer or an Si substrate. CONSTITUTION:A first SiO2 film 9, a first SiN film 10 and an SiO2 film 11 which contains boron or phosphorus are grown on an Si substrate 8 in this order. This assembly is heat-treated; after that, a second SiN film 12 is grown on the SiO2 film 11. A layer insulating film composed of four layers is formed. Then, the layer insulating film is dry-etched via a resist pattern 13; a contact hole is formed; the resist pattern 13 is removed; after that a third SiN film 14 and a second SiO2 film 15 are grown sequentially; an anisotropic etching operation is executed; a sidewall insulating film by the third SiN film 14 and the second SiO2 film 15 is formed on the sidewall of the contact hole. Lastly, an Al alloy film 16 is vapor-deposited; the Al alloy film 16 is dry-etched via a resist pattern 17; an inter-connection is formed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、高信頼性の配線を形成
する半導体装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device forming highly reliable wiring and a method of manufacturing the same.

【0002】0002

【従来の技術】近年、半導体集積回路が微細化するにつ
れて、層間絶縁膜中に含まれる不純物が配線やシリコン
基板に及ぼす影響も無視できなくなってきている。従っ
て、配線を形成する際に、層間絶縁膜中に含まれる不純
物が配線やシリコン基板に影響を与えないような半導体
装置の製造方法が切望されている。
2. Description of the Related Art In recent years, as semiconductor integrated circuits have become smaller, the influence of impurities contained in interlayer insulating films on wiring and silicon substrates cannot be ignored. Therefore, there is a strong need for a method of manufacturing a semiconductor device in which impurities contained in an interlayer insulating film do not affect the wiring or the silicon substrate when wiring is formed.

【0003】図2(a)〜(f)は従来の半導体装置の
製造方法の工程断面図を示すものである。まず図2(a
)に示すようにシリコン基板1上に酸化シリコン膜2、
窒化シリコン膜3、ボロンおよび燐あるいはその一方を
含む酸化シリコン膜4をこの順に成長させて、熱処理を
行い、図2(b),(c)に示すようにフォトレジスト
パターン5を介してコンタクトホールを形成する。 次に、フォトレジストパターン5を除去後、図2(d)
〜(f)に示すようにアルミニウム合金膜6を蒸着し、
フォトレジストパターン7を介してこのアルミニウム合
金膜6をドライエッチングして配線を形成するものであ
り、層間絶縁膜を構成するボロンおよび燐あるいはその
一方を含む酸化シリコン膜4と配線を構成するアルミニ
ウム合金膜6は直接接触していた。
FIGS. 2A to 2F are cross-sectional views showing steps in a conventional method for manufacturing a semiconductor device. First, Figure 2 (a
), a silicon oxide film 2,
A silicon nitride film 3 and a silicon oxide film 4 containing boron and/or phosphorus are grown in this order, heat treated, and a contact hole is formed through a photoresist pattern 5 as shown in FIGS. 2(b) and 2(c). form. Next, after removing the photoresist pattern 5, as shown in FIG.
As shown in ~(f), an aluminum alloy film 6 is deposited,
Wiring is formed by dry etching this aluminum alloy film 6 through a photoresist pattern 7, and the silicon oxide film 4 containing boron and/or phosphorus forming an interlayer insulating film and the aluminum alloy forming the wiring. Membrane 6 was in direct contact.

【0004】0004

【発明が解決しようとする課題】しかしながら、上記の
ような従来の半導体装置の製造方法においては、ボロン
および燐あるいはその一方を含む酸化シリコン膜4に含
まれる不純物が、アルミニウム合金膜6に拡散し、アル
ミニウム合金膜6のボイドを引き起こしたり、またこの
アルミニウム合金膜6を通してシリコン基板1中に拡散
してトランジスタの特性を変動させるという課題があっ
た。
However, in the conventional semiconductor device manufacturing method as described above, impurities contained in the silicon oxide film 4 containing boron and/or phosphorus diffuse into the aluminum alloy film 6. However, there are problems in that it causes voids in the aluminum alloy film 6 and also diffuses into the silicon substrate 1 through the aluminum alloy film 6, causing variations in the characteristics of the transistor.

【0005】本発明は、上記従来の課題を解決しようと
するもので、ボロンおよび燐あるいはその一方を含む酸
化シリコン膜4に含まれる不純物が、アルミニウム合金
膜6に拡散することを抑えることができる優れた半導体
装置およびその製造方法を提供することを目的としてい
る。
The present invention is an attempt to solve the above-mentioned conventional problems, and is capable of suppressing impurities contained in the silicon oxide film 4 containing boron and/or phosphorus from diffusing into the aluminum alloy film 6. The purpose is to provide an excellent semiconductor device and its manufacturing method.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置は、第1酸化シリコン膜、第1窒
化シリコン膜、ボロンおよび燐のうち少なくとも一つを
含む酸化シリコン膜および第2窒化シリコン膜、ボロン
および燐のうち少なくとも一つを含む酸化シリコン膜お
よび第2窒化シリコン膜の4層の層間絶縁膜構成よりな
る半導体装置とその層間絶縁膜に形成したコンタクトホ
ールと、そのコンタクトホール側壁に形成された第3窒
化シリコン膜および第2酸化シリコン膜からなる側壁絶
縁膜と、前述の層間絶縁膜上に形成され前述のコンタク
トホールを介して半導体基板表面に接続された配線とを
有する構成の半導体装置等よりなる。
Means for Solving the Problems In order to achieve this object, a semiconductor device of the present invention includes a first silicon oxide film, a first silicon nitride film, a silicon oxide film containing at least one of boron and phosphorus, and a first silicon oxide film containing at least one of boron and phosphorus. A semiconductor device having a four-layer interlayer insulating film structure including a second silicon nitride film, a silicon oxide film containing at least one of boron and phosphorus, and a second silicon nitride film, a contact hole formed in the interlayer insulating film, and the contact. A side wall insulating film made of a third silicon nitride film and a second silicon oxide film formed on the side wall of the hole, and a wiring formed on the above-mentioned interlayer insulating film and connected to the surface of the semiconductor substrate through the above-mentioned contact hole. It consists of a semiconductor device, etc. having a configuration as follows.

【0007】[0007]

【作用】この構成によって、ボロンおよび燐のうち少な
くとも一つを含む酸化シリコン膜上部は第2窒化シリコ
ン膜で覆われ、またコンタクトホールの側壁は第3窒化
シリコン膜と第2酸化シリコン膜からなる側壁絶縁膜で
覆われているために、ボロンおよび燐のうち少なくとも
一つを含む酸化シリコン膜中に含まれる不純物が、アル
ミニウム合金膜あるいはシリコン基板へ拡散することを
抑えることが可能となる。
[Operation] With this configuration, the upper part of the silicon oxide film containing at least one of boron and phosphorus is covered with the second silicon nitride film, and the sidewall of the contact hole is made of the third silicon nitride film and the second silicon oxide film. Being covered with the sidewall insulating film makes it possible to suppress impurities contained in the silicon oxide film containing at least one of boron and phosphorus from diffusing into the aluminum alloy film or the silicon substrate.

【0008】[0008]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1(a)〜(i)は、本発明の
一実施例における半導体装置の製造方法の断面図を示す
ものである。まず図1(a)に示すようにトランジスタ
等がすでに形成されたシリコン基板8上に膜厚5〜30
nmの第1酸化シリコン膜、膜厚10〜60nmの第1
窒化シリコン膜10、膜厚400〜1,000nmのボ
ロン及び燐あるいはその一方を含む酸化シリコン膜11
をこの順に成長させた後に、800〜950℃で熱処理
を行う。続いて図1(b)に示すように第2窒化シリコ
ン膜12を成長させて、上記の4層から構成される層間
絶縁膜を形成し、図1(C)に示すフォトレジストパタ
ーン13を介して、弗素系ガスにより4層から構成され
る層間絶縁膜をドライエッチングして、図1(d)に示
すようにコンタクトホールを形成する。次に図1(e)
に示すように、膜厚50〜100nmの第3窒化シリコ
ン膜14、膜厚50〜200nmの第2酸化シリコン膜
15をこの順に成長させて、弗素系ガスを用いてコンタ
クトホール底部の第3窒化シリコン膜14と第2酸化シ
リコン膜15がエッチングされてシリコン基板8が露出
するまで異方性ドライエッチングを行い、図1(f)に
示すような、コンタクトホールの側壁に第3窒化シリコ
ン膜14と第2酸化シリコン膜15からなる側壁絶縁膜
を形成し、図1(g)〜(i)に示すように膜厚600
〜1,000nmのアルミニウム合金膜16を蒸着し、
フォトレジストパターン17を介してアルミニウム合金
膜16を塩素および臭素系ガスを用いてドライエッチン
グして配線を形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A to 1I show cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), a film with a thickness of 5 to 30 mm is coated on a silicon substrate 8 on which transistors and the like have already been formed.
first silicon oxide film with a thickness of 10 to 60 nm;
a silicon nitride film 10; a silicon oxide film 11 containing boron and/or phosphorus with a film thickness of 400 to 1,000 nm;
After growing in this order, heat treatment is performed at 800 to 950°C. Subsequently, as shown in FIG. 1(b), a second silicon nitride film 12 is grown to form an interlayer insulating film composed of the four layers described above, and a second silicon nitride film 12 is grown through a photoresist pattern 13 as shown in FIG. 1(c). Then, the interlayer insulating film composed of four layers is dry-etched using a fluorine-based gas to form a contact hole as shown in FIG. 1(d). Next, Figure 1(e)
As shown in the figure, a third silicon nitride film 14 with a thickness of 50 to 100 nm and a second silicon oxide film 15 with a thickness of 50 to 200 nm are grown in this order, and a third nitride film at the bottom of the contact hole is grown using a fluorine-based gas. Anisotropic dry etching is performed until the silicon film 14 and the second silicon oxide film 15 are etched and the silicon substrate 8 is exposed, and a third silicon nitride film 14 is formed on the side wall of the contact hole as shown in FIG. 1(f). A sidewall insulating film consisting of a second silicon oxide film 15 is formed to have a film thickness of 600 mm as shown in FIGS. 1(g) to 1(i).
Depositing an aluminum alloy film 16 of ~1,000 nm,
Wiring is formed by dry etching the aluminum alloy film 16 through the photoresist pattern 17 using chlorine and bromine gas.

【0009】以上のように本実施例によれば、ボロンお
よび燐あるいはその一方を含む酸化シリコン膜11上部
は第2窒化シリコン膜12で覆われ、またコンタクトホ
ールの側壁は第3窒化シリコン膜14と第2酸化シリコ
ン膜15からなる側壁絶縁膜で覆われているために、ボ
ロンおよび燐あるいはその一方を含む酸化シリコン膜1
1中に含まれる不純物が、アルミニウム合金膜16ある
いはシリコン基板8へ拡散することを抑えることができ
、これによりアルミニウム合金膜16のボイドやシリコ
ン基板8に形成されたトランジスタへの影響を抑えるこ
とができる。
As described above, according to this embodiment, the upper part of the silicon oxide film 11 containing boron and/or phosphorus is covered with the second silicon nitride film 12, and the side wall of the contact hole is covered with the third silicon nitride film 14. Since the silicon oxide film 1 containing boron and/or phosphorus is covered with the sidewall insulating film made of the second silicon oxide film 15
1 can be suppressed from diffusing into the aluminum alloy film 16 or the silicon substrate 8, thereby suppressing the effect on voids in the aluminum alloy film 16 and the transistors formed on the silicon substrate 8. can.

【0010】なお、上記実施例では配線はアルミニウム
合金膜の一層から構成されるとしたが、バリアメタル合
金とアルミニウム合金から構成される配線を適用しても
よい。
[0010] In the above embodiment, the wiring is made up of a single layer of an aluminum alloy film, but wiring made of a barrier metal alloy and an aluminum alloy may also be used.

【0011】またアルミニウム合金膜以外の配線でもよ
い。
[0011] Also, wiring other than an aluminum alloy film may be used.

【0012】0012

【発明の効果】以上のように本発明は第1酸化シリコン
膜、第1窒化シリコン膜、ボロンおよび燐のうち少なく
とも一つを含む酸化シリコン膜、第2窒化シリコン膜の
4層から構成される層間絶縁膜と、その層間絶縁膜に形
成されたコンタクトホールと、そのコンタクトホールの
側壁に形成された第3窒化シリコン膜と第2酸化シリコ
ン膜からなる側壁絶縁膜と、コンタクトホールを介して
半導体基板表面に接続して形成されたアルミニウム合金
膜等の配線とを有する構成であるのでボロンおよび燐の
うち少なくとも一つを含む酸化シリコン膜中に含まれる
不純物が、アルミニウム合金膜等あるいはシリコン基板
へ拡散することを抑えることができ、これによりアルミ
ニウム合金膜等のボイドやシリコン基板に形成されたト
ランジスタへの影響を抑えることができる優れた半導体
装置およびその製造方法を提供できる。
As described above, the present invention is composed of four layers: a first silicon oxide film, a first silicon nitride film, a silicon oxide film containing at least one of boron and phosphorus, and a second silicon nitride film. An interlayer insulating film, a contact hole formed in the interlayer insulating film, a sidewall insulating film made of a third silicon nitride film and a second silicon oxide film formed on the sidewall of the contact hole, and a semiconductor through the contact hole. Since the structure has a wiring such as an aluminum alloy film connected to the substrate surface, impurities contained in the silicon oxide film containing at least one of boron and phosphorus may be transferred to the aluminum alloy film or the silicon substrate. It is possible to provide an excellent semiconductor device and a method for manufacturing the same, which can suppress diffusion, thereby suppressing effects on voids in an aluminum alloy film, etc., and transistors formed on a silicon substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における半導体装置の製造方
法の工程順の断面図
FIG. 1 is a cross-sectional view of the process order of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法の工程順の断面図
[Figure 2] Cross-sectional view of the process order of a conventional semiconductor device manufacturing method

【符号の説明】[Explanation of symbols]

8    シリコン基板(半導体基板)9    第1
酸化シリコン膜 10  第1窒化シリコン膜 11  ボロンおよび燐のうち少なくとも一つを含む酸
化シリコン膜 12  第2窒化シリコン膜 13  フォトレジストパターン 14  第3窒化シリコン膜 15  第2酸化シリコン膜 16  アルミニウム合金膜(配線) 17  フォトレジストパターン
8 Silicon substrate (semiconductor substrate) 9 1st
Silicon oxide film 10 First silicon nitride film 11 Silicon oxide film 12 containing at least one of boron and phosphorus Second silicon nitride film 13 Photoresist pattern 14 Third silicon nitride film 15 Second silicon oxide film 16 Aluminum alloy film ( Wiring) 17 Photoresist pattern

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  トランジスタ等が形成された半導体基
板上に順次形成された第1酸化シリコン膜、第1窒化シ
リコン膜、ボロンおよび燐のうち少なくとも一つを含む
酸化シリコン膜および第2窒化シリコン膜の4層で構成
された層間絶縁膜を有する半導体装置。
1. A first silicon oxide film, a first silicon nitride film, a silicon oxide film containing at least one of boron and phosphorus, and a second silicon nitride film, which are sequentially formed on a semiconductor substrate on which a transistor or the like is formed. A semiconductor device having an interlayer insulating film composed of four layers.
【請求項2】  半導体基板上に順次パターン形成され
た第1酸化シリコン膜、第1窒化シリコン膜、ボロンお
よび燐のうち少なくとも一つを含む酸化シリコン膜およ
び第2シリコン膜の4層で構成された層間絶縁膜と、そ
の層間絶縁膜の一部分をエッチングして形成されたコン
タクトホールと、そのコンタクトホールの側壁に順次形
成された第3窒化シリコン膜および第2酸化シリコン膜
からなる側壁絶縁膜と、前記層間絶縁膜上に形成され前
記コンタクトホールを介して前記前記半導体基板表面に
接続された配線とを少なくとも有する半導体装置。
2. Consisting of four layers: a first silicon oxide film, a first silicon nitride film, a silicon oxide film containing at least one of boron and phosphorus, and a second silicon film, which are sequentially patterned on a semiconductor substrate. a contact hole formed by etching a portion of the interlayer insulating film; and a sidewall insulating film consisting of a third silicon nitride film and a second silicon oxide film sequentially formed on the sidewall of the contact hole. and a wiring formed on the interlayer insulating film and connected to the surface of the semiconductor substrate via the contact hole.
【請求項3】  トランジスタ等の形成されたシリコン
基板上に第1酸化シリコン膜、第1窒化シリコン膜、ボ
ロンおよび燐のうち少なくとも一つを含む酸化シリコン
膜を順次形成して、熱処理を行った後、そのボロンおよ
び燐のうち少なくとも一つを含む酸化シリコン膜上に第
2窒化シリコン膜を成長させてなる4層構造の層間絶縁
膜を形成する工程を少なくとも有する半導体装置の製造
方法。
3. A first silicon oxide film, a first silicon nitride film, and a silicon oxide film containing at least one of boron and phosphorus are sequentially formed on a silicon substrate on which a transistor or the like is formed, and then heat treated. A method for manufacturing a semiconductor device, which includes at least the step of: forming an interlayer insulating film having a four-layer structure by growing a second silicon nitride film on the silicon oxide film containing at least one of boron and phosphorus;
【請求項4】  請求項3記載の半導体装置の製造方法
の4層構造の層間絶縁膜を形成した後、その層間絶縁膜
の一部分をフォトレジストパターンを用いてドライエッ
チングし、コンタクトホールを形成する工程と、そのフ
ォトレジストパターンを除去した後、全表面に第3窒化
シリコン膜、第2酸化シリコン膜を順次形成する工程と
、その第3窒化シリコン膜及び第2酸化シリコン膜を異
方性ドライエッチングして、前記コンタクトホールの側
壁に前記3窒化シリコン膜と第2酸化シリコン膜からな
る側壁絶縁膜を形成する工程と、前記層間絶縁膜上に前
記コンタクトホールを介して前記半導体基板表面に接続
された配線をパターン形成する工程とを少なくとも有す
る半導体装置の製造方法。
4. The method for manufacturing a semiconductor device according to claim 3, wherein after forming an interlayer insulating film having a four-layer structure, a part of the interlayer insulating film is dry-etched using a photoresist pattern to form a contact hole. After removing the photoresist pattern, a step of sequentially forming a third silicon nitride film and a second silicon oxide film on the entire surface, and anisotropic drying of the third silicon nitride film and second silicon oxide film. etching to form a sidewall insulating film made of the third silicon nitride film and a second silicon oxide film on the sidewall of the contact hole; and connecting to the semiconductor substrate surface through the contact hole on the interlayer insulating film. A method for manufacturing a semiconductor device, comprising at least a step of patterning the wires formed in the pattern.
JP7091491A 1991-04-03 1991-04-03 Semiconductor device and its manufacture Pending JPH04356944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7091491A JPH04356944A (en) 1991-04-03 1991-04-03 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7091491A JPH04356944A (en) 1991-04-03 1991-04-03 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH04356944A true JPH04356944A (en) 1992-12-10

Family

ID=13445258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7091491A Pending JPH04356944A (en) 1991-04-03 1991-04-03 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH04356944A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158765A (en) * 2015-04-24 2016-11-23 旺宏电子股份有限公司 Semiconductor element and manufacture method thereof
US10607848B2 (en) 2015-05-08 2020-03-31 Macronix International Co., Ltd. Method of fabricating semiconductor device

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JPS63236317A (en) * 1987-03-25 1988-10-03 Toshiba Corp Manufacture of semiconductor device
JPS6482653A (en) * 1987-09-25 1989-03-28 Nec Corp Semiconductor integrated circuit
JPH01122139A (en) * 1987-11-05 1989-05-15 Fujitsu Ltd Semiconductor device
JPH0225026A (en) * 1988-06-06 1990-01-26 Philips Gloeilampenfab:Nv Manufacture of semiconductor device
JPH02239625A (en) * 1989-03-13 1990-09-21 Sharp Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158765A (en) * 2015-04-24 2016-11-23 旺宏电子股份有限公司 Semiconductor element and manufacture method thereof
US10607848B2 (en) 2015-05-08 2020-03-31 Macronix International Co., Ltd. Method of fabricating semiconductor device

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