JPS6482653A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6482653A JPS6482653A JP24210387A JP24210387A JPS6482653A JP S6482653 A JPS6482653 A JP S6482653A JP 24210387 A JP24210387 A JP 24210387A JP 24210387 A JP24210387 A JP 24210387A JP S6482653 A JPS6482653 A JP S6482653A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- film
- insulating film
- sidewall
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To prevent gas from generating from an opening formed at an interlayer insulating film and to improve the reliability of multilayer interconnections by covering the sidewall of the opening with an insulating film. CONSTITUTION:Lower layer wirings 3 are provided on an insulating film 2 on a semiconductor substrate 1. Then, a PSG film 5 is formed by rotatable coating on a deposited silicon oxide film 4, and flattened. Then, a silicon nitride film 6 is deposited thereon, and an interlayer insulating film made of the silicon films 4, 6 and the film 5 is formed. Thereafter, an opening 7 is formed in the interlayer insulating film, and a thermally stable silicon nitride film 8 is deposited on the film 6 including the opening 7. The film 8 remains only on the sidewall of the opening 7, and the surface of the wirings 3 of the opening 7 is exposed. Subsequently, upper layer wirings 9 to be connected to the wirings 3 are formed. Thus, the sidewall of the opening is covered with the insulating film, thereby preventing gas generated in later steps from discharging into the opening, and a semiconductor device having multilayer interconnections with high reliability is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24210387A JPS6482653A (en) | 1987-09-25 | 1987-09-25 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24210387A JPS6482653A (en) | 1987-09-25 | 1987-09-25 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6482653A true JPS6482653A (en) | 1989-03-28 |
Family
ID=17084345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24210387A Pending JPS6482653A (en) | 1987-09-25 | 1987-09-25 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6482653A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5066612A (en) * | 1990-01-05 | 1991-11-19 | Fujitsu Limited | Method of forming wiring of a semiconductor device |
JPH04356944A (en) * | 1991-04-03 | 1992-12-10 | Matsushita Electron Corp | Semiconductor device and its manufacture |
US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
US5612572A (en) * | 1993-12-28 | 1997-03-18 | Lg Semicon Co., Ltd. | Semiconductor device with an insulation groove |
US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
US6284584B1 (en) * | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
KR100317501B1 (en) * | 1998-12-29 | 2002-02-19 | 박종섭 | A forming method of flash memory device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594057A (en) * | 1982-06-30 | 1984-01-10 | Toshiba Corp | Formation of contact hole |
JPS59155128A (en) * | 1983-02-23 | 1984-09-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS63262856A (en) * | 1987-04-20 | 1988-10-31 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-09-25 JP JP24210387A patent/JPS6482653A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594057A (en) * | 1982-06-30 | 1984-01-10 | Toshiba Corp | Formation of contact hole |
JPS59155128A (en) * | 1983-02-23 | 1984-09-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS63262856A (en) * | 1987-04-20 | 1988-10-31 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5066612A (en) * | 1990-01-05 | 1991-11-19 | Fujitsu Limited | Method of forming wiring of a semiconductor device |
JPH04356944A (en) * | 1991-04-03 | 1992-12-10 | Matsushita Electron Corp | Semiconductor device and its manufacture |
US5592024A (en) * | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
US6794286B2 (en) | 1993-10-29 | 2004-09-21 | Kabushiki Kaisha Toshiba | Process for fabricating a metal wiring and metal contact in a semicondutor device |
US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
US6284584B1 (en) * | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
US6514811B2 (en) | 1993-12-17 | 2003-02-04 | Stmicroelectronics, Inc. | Method for memory masking for periphery salicidation of active regions |
US6661064B2 (en) | 1993-12-17 | 2003-12-09 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
US5612572A (en) * | 1993-12-28 | 1997-03-18 | Lg Semicon Co., Ltd. | Semiconductor device with an insulation groove |
KR100317501B1 (en) * | 1998-12-29 | 2002-02-19 | 박종섭 | A forming method of flash memory device |
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