JPS6466953A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6466953A JPS6466953A JP22464787A JP22464787A JPS6466953A JP S6466953 A JPS6466953 A JP S6466953A JP 22464787 A JP22464787 A JP 22464787A JP 22464787 A JP22464787 A JP 22464787A JP S6466953 A JPS6466953 A JP S6466953A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating films
- wiring
- deposited onto
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
PURPOSE:To smooth the shape of an opening section, and to improve the coatability of an upper layer wiring by forming inter-layer insulating films with opening sections for a contact in multilayer structure in which insulating films are laminated in a manner that the etching rate of an uppermost-layer insulating film is most increased and etching rates toward an upper layer are decreased in succession. CONSTITUTION:An silicon oxide film 2, a polycrystalline silicon layer 3, and an aluminum layer 4 are deposited onto an silicon substrate 1 in succession, and a lower layer wiring is formed through selective etching. Silicon oxide PSG films 5, 6, 7, the content of phosphorus of which is reduced successively to 12 or 4mol%, are deposited onto the surface of the lower layer wiring and inter-layer insulating films are shaped, and a deep cone-shaped opening section 9 is formed through isotropic etching, using a photo-resist film 8 as a mask. An aluminum layer is deposited onto the surface including the opening section 9, and brought into contact with the lower layer wiring, and an aluminum wiring 10 extending on the inter-layer insulating films is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22464787A JPS6466953A (en) | 1987-09-07 | 1987-09-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22464787A JPS6466953A (en) | 1987-09-07 | 1987-09-07 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6466953A true JPS6466953A (en) | 1989-03-13 |
Family
ID=16816998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22464787A Pending JPS6466953A (en) | 1987-09-07 | 1987-09-07 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6466953A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5169800A (en) * | 1989-12-26 | 1992-12-08 | Fujitsu Limited | Method of fabricating semiconductor devices by laser planarization of metal layer |
US5246880A (en) * | 1992-04-27 | 1993-09-21 | Eastman Kodak Company | Method for creating substrate electrodes for flip chip and other applications |
KR100380281B1 (en) * | 2000-12-28 | 2003-04-18 | 주식회사 하이닉스반도체 | Method for forming via hole in semiconductor device |
US6729938B2 (en) | 2000-05-29 | 2004-05-04 | Koyo Machine Industries Co., Ltd. | Centerless grinding machine |
-
1987
- 1987-09-07 JP JP22464787A patent/JPS6466953A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5169800A (en) * | 1989-12-26 | 1992-12-08 | Fujitsu Limited | Method of fabricating semiconductor devices by laser planarization of metal layer |
US5246880A (en) * | 1992-04-27 | 1993-09-21 | Eastman Kodak Company | Method for creating substrate electrodes for flip chip and other applications |
US6729938B2 (en) | 2000-05-29 | 2004-05-04 | Koyo Machine Industries Co., Ltd. | Centerless grinding machine |
KR100380281B1 (en) * | 2000-12-28 | 2003-04-18 | 주식회사 하이닉스반도체 | Method for forming via hole in semiconductor device |
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